Merge tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc into next

Pull ARM SoC driver changes from Olof Johansson:
 "SoC-near driver changes that we're merging through our tree.  Mostly
  because they depend on other changes we have staged, but in some cases
  because the driver maintainers preferred that we did it this way.

  This contains a largeish cleanup series of the omap_l3_noc bus driver,
  cpuidle rework for Exynos, some reset driver conversions and a long
  branch of TI EDMA fixes and cleanups, with more to come next release.

  The TI EDMA cleanups is a shared branch with the dmaengine tree, with
  a handful of Davinci-specific fixes on top.

  After discussion at last year's KS (and some more on the mailing
  lists), we are here adding a drivers/soc directory.  The purpose of
  this is to keep per-vendor shared code that's needed by different
  drivers but that doesn't fit into the MFD (nor drivers/platform)
  model.  We expect to keep merging contents for this hierarchy through
  arm-soc so we can keep an eye on what the vendors keep adding here and
  not making it a free-for-all to shove in crazy stuff"

* tag 'drivers-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits)
  cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM
  tty: serial: msm: Remove direct access to GSBI
  power: reset: keystone-reset: introduce keystone reset driver
  Documentation: dt: add bindings for keystone pll control controller
  Documentation: dt: add bindings for keystone reset driver
  soc: qcom: fix of_device_id table
  ARM: EXYNOS: Fix kernel panic when unplugging CPU1 on exynos
  ARM: EXYNOS: Move the driver to drivers/cpuidle directory
  ARM: EXYNOS: Cleanup all unneeded headers from cpuidle.c
  ARM: EXYNOS: Pass the AFTR callback to the platform_data
  ARM: EXYNOS: Move S5P_CHECK_SLEEP into pm.c
  ARM: EXYNOS: Move the power sequence call in the cpu_pm notifier
  ARM: EXYNOS: Move the AFTR state function into pm.c
  ARM: EXYNOS: Encapsulate the AFTR code into a function
  ARM: EXYNOS: Disable cpuidle for exynos5440
  ARM: EXYNOS: Encapsulate boot vector code into a function for cpuidle
  ARM: EXYNOS: Pass wakeup mask parameter to function for cpuidle
  ARM: EXYNOS: Remove ifdef for scu_enable in pm
  ARM: EXYNOS: Move scu_enable in the cpu_pm notifier
  ARM: EXYNOS: Use the cpu_pm notifier for pm
  ...

5 files changed, 0 insertions, 91 deletions

diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 56ea41d5f849..b85b781b05fd 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -134,13 +134,6 @@ struct platform_device da8xx_serial_device[] = {
         }
 };
 
-static s8 da8xx_queue_tc_mapping[][2] = {
-        /* {event queue no, TC no} */
-        {0, 0},
-        {1, 1},
-        {-1, -1}
-};
-
 static s8 da8xx_queue_priority_mapping[][2] = {
         /* {event queue no, Priority} */
         {0, 3},
@@ -148,12 +141,6 @@ static s8 da8xx_queue_priority_mapping[][2] = {
         {-1, -1}
 };
 
-static s8 da850_queue_tc_mapping[][2] = {
-        /* {event queue no, TC no} */
-        {0, 0},
-        {-1, -1}
-};
-
 static s8 da850_queue_priority_mapping[][2] = {
         /* {event queue no, Priority} */
         {0, 3},
@@ -161,12 +148,6 @@ static s8 da850_queue_priority_mapping[][2] = {
 };
 
 static struct edma_soc_info da830_edma_cc0_info = {
-        .n_channel              = 32,
-        .n_region               = 4,
-        .n_slot                 = 128,
-        .n_tc                   = 2,
-        .n_cc                   = 1,
-        .queue_tc_mapping       = da8xx_queue_tc_mapping,
         .queue_priority_mapping = da8xx_queue_priority_mapping,
         .default_queue          = EVENTQ_1,
 };
@@ -177,22 +158,10 @@ static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
 
 static struct edma_soc_info da850_edma_cc_info[] = {
         {
-                .n_channel              = 32,
-                .n_region               = 4,
-                .n_slot                 = 128,
-                .n_tc                   = 2,
-                .n_cc                   = 1,
-                .queue_tc_mapping       = da8xx_queue_tc_mapping,
                 .queue_priority_mapping = da8xx_queue_priority_mapping,
                 .default_queue          = EVENTQ_1,
         },
         {
-                .n_channel              = 32,
-                .n_region               = 4,
-                .n_slot                 = 128,
-                .n_tc                   = 1,
-                .n_cc                   = 1,
-                .queue_tc_mapping       = da850_queue_tc_mapping,
                 .queue_priority_mapping = da850_queue_priority_mapping,
                 .default_queue          = EVENTQ_0,
         },
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 07381d8cea62..2f3ed3a58d57 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -569,14 +569,6 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 /*----------------------------------------------------------------------*/
 
 static s8
-queue_tc_mapping[][2] = {
-        /* {event queue no, TC no} */
-        {0, 0},
-        {1, 1},
-        {-1, -1},
-};
-
-static s8
 queue_priority_mapping[][2] = {
         /* {event queue no, Priority} */
         {0, 3},
@@ -585,12 +577,6 @@ queue_priority_mapping[][2] = {
 };
 
 static struct edma_soc_info edma_cc0_info = {
-        .n_channel              = 64,
-        .n_region               = 4,
-        .n_slot                 = 128,
-        .n_tc                   = 2,
-        .n_cc                   = 1,
-        .queue_tc_mapping       = queue_tc_mapping,
         .queue_priority_mapping = queue_priority_mapping,
         .default_queue          = EVENTQ_1,
 };
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 08a61b938333..0ae8114f5cc9 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -853,16 +853,6 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 
 /* Four Transfer Controllers on DM365 */
 static s8
-dm365_queue_tc_mapping[][2] = {
-        /* {event queue no, TC no} */
-        {0, 0},
-        {1, 1},
-        {2, 2},
-        {3, 3},
-        {-1, -1},
-};
-
-static s8
 dm365_queue_priority_mapping[][2] = {
         /* {event queue no, Priority} */
         {0, 7},
@@ -873,12 +863,6 @@ dm365_queue_priority_mapping[][2] = {
 };
 
 static struct edma_soc_info edma_cc0_info = {
-        .n_channel              = 64,
-        .n_region               = 4,
-        .n_slot                 = 256,
-        .n_tc                   = 4,
-        .n_cc                   = 1,
-        .queue_tc_mapping       = dm365_queue_tc_mapping,
         .queue_priority_mapping = dm365_queue_priority_mapping,
         .default_queue          = EVENTQ_3,
 };
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 5debffba4b24..dc52657909c4 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -499,14 +499,6 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 /*----------------------------------------------------------------------*/
 
 static s8
-queue_tc_mapping[][2] = {
-        /* {event queue no, TC no} */
-        {0, 0},
-        {1, 1},
-        {-1, -1},
-};
-
-static s8
 queue_priority_mapping[][2] = {
         /* {event queue no, Priority} */
         {0, 3},
@@ -515,12 +507,6 @@ queue_priority_mapping[][2] = {
 };
 
 static struct edma_soc_info edma_cc0_info = {
-        .n_channel              = 64,
-        .n_region               = 4,
-        .n_slot                 = 128,
-        .n_tc                   = 2,
-        .n_cc                   = 1,
-        .queue_tc_mapping       = queue_tc_mapping,
         .queue_priority_mapping = queue_priority_mapping,
         .default_queue          = EVENTQ_1,
 };
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 332d00d24dc2..6c3bbea7d77d 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -533,16 +533,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 
 /* Four Transfer Controllers on DM646x */
 static s8
-dm646x_queue_tc_mapping[][2] = {
-        /* {event queue no, TC no} */
-        {0, 0},
-        {1, 1},
-        {2, 2},
-        {3, 3},
-        {-1, -1},
-};
-
-static s8
 dm646x_queue_priority_mapping[][2] = {
         /* {event queue no, Priority} */
         {0, 4},
@@ -553,12 +543,6 @@ dm646x_queue_priority_mapping[][2] = {
 };
 
 static struct edma_soc_info edma_cc0_info = {
-        .n_channel              = 64,
-        .n_region               = 6,    /* 0-1, 4-7 */
-        .n_slot                 = 512,
-        .n_tc                   = 4,
-        .n_cc                   = 1,
-        .queue_tc_mapping       = dm646x_queue_tc_mapping,
         .queue_priority_mapping = dm646x_queue_priority_mapping,
         .default_queue          = EVENTQ_1,
 };