diff options
author | Philip Avinash <avinashphilip@ti.com> | 2013-03-25 03:49:48 -0400 |
---|---|---|
committer | Sekhar Nori <nsekhar@ti.com> | 2013-04-01 07:47:10 -0400 |
commit | bb170e6118e76903bf03fc14ab60a34c26aac747 (patch) | |
tree | 6f2373bbea3e26ba1256a269ed783547bbc983fc /arch/arm/mach-davinci | |
parent | c6007ffe842892484027a40b6ac18d29ac11e2ce (diff) |
ARM: davinci: da850: add ECAP & EHRPWM clock nodes
Add ECAP and EHRPWM module clock nodes. Also add a clock
node for TBCLK for EHRWPM.
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'arch/arm/mach-davinci')
-rw-r--r-- | arch/arm/mach-davinci/da850.c | 46 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/da8xx.h | 1 |
2 files changed, 47 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 0c4a26ddebba..2a2f60c54ec6 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c | |||
@@ -383,6 +383,49 @@ static struct clk dsp_clk = { | |||
383 | .flags = PSC_LRST | PSC_FORCE, | 383 | .flags = PSC_LRST | PSC_FORCE, |
384 | }; | 384 | }; |
385 | 385 | ||
386 | static struct clk ehrpwm_clk = { | ||
387 | .name = "ehrpwm", | ||
388 | .parent = &pll0_sysclk2, | ||
389 | .lpsc = DA8XX_LPSC1_PWM, | ||
390 | .gpsc = 1, | ||
391 | .flags = DA850_CLK_ASYNC3, | ||
392 | }; | ||
393 | |||
394 | #define DA8XX_EHRPWM_TBCLKSYNC BIT(12) | ||
395 | |||
396 | static void ehrpwm_tblck_enable(struct clk *clk) | ||
397 | { | ||
398 | u32 val; | ||
399 | |||
400 | val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG)); | ||
401 | val |= DA8XX_EHRPWM_TBCLKSYNC; | ||
402 | writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG)); | ||
403 | } | ||
404 | |||
405 | static void ehrpwm_tblck_disable(struct clk *clk) | ||
406 | { | ||
407 | u32 val; | ||
408 | |||
409 | val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG)); | ||
410 | val &= ~DA8XX_EHRPWM_TBCLKSYNC; | ||
411 | writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG)); | ||
412 | } | ||
413 | |||
414 | static struct clk ehrpwm_tbclk = { | ||
415 | .name = "ehrpwm_tbclk", | ||
416 | .parent = &ehrpwm_clk, | ||
417 | .clk_enable = ehrpwm_tblck_enable, | ||
418 | .clk_disable = ehrpwm_tblck_disable, | ||
419 | }; | ||
420 | |||
421 | static struct clk ecap_clk = { | ||
422 | .name = "ecap", | ||
423 | .parent = &pll0_sysclk2, | ||
424 | .lpsc = DA8XX_LPSC1_ECAP, | ||
425 | .gpsc = 1, | ||
426 | .flags = DA850_CLK_ASYNC3, | ||
427 | }; | ||
428 | |||
386 | static struct clk_lookup da850_clks[] = { | 429 | static struct clk_lookup da850_clks[] = { |
387 | CLK(NULL, "ref", &ref_clk), | 430 | CLK(NULL, "ref", &ref_clk), |
388 | CLK(NULL, "pll0", &pll0_clk), | 431 | CLK(NULL, "pll0", &pll0_clk), |
@@ -430,6 +473,9 @@ static struct clk_lookup da850_clks[] = { | |||
430 | CLK("vpif", NULL, &vpif_clk), | 473 | CLK("vpif", NULL, &vpif_clk), |
431 | CLK("ahci", NULL, &sata_clk), | 474 | CLK("ahci", NULL, &sata_clk), |
432 | CLK("davinci-rproc.0", NULL, &dsp_clk), | 475 | CLK("davinci-rproc.0", NULL, &dsp_clk), |
476 | CLK("ehrpwm", "fck", &ehrpwm_clk), | ||
477 | CLK("ehrpwm", "tbclk", &ehrpwm_tbclk), | ||
478 | CLK("ecap", "fck", &ecap_clk), | ||
433 | CLK(NULL, NULL, NULL), | 479 | CLK(NULL, NULL, NULL), |
434 | }; | 480 | }; |
435 | 481 | ||
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h index de439b7b9af1..be77ce269cb0 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx.h +++ b/arch/arm/mach-davinci/include/mach/da8xx.h | |||
@@ -55,6 +55,7 @@ extern unsigned int da850_max_speed; | |||
55 | #define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) | 55 | #define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x)) |
56 | #define DA8XX_JTAG_ID_REG 0x18 | 56 | #define DA8XX_JTAG_ID_REG 0x18 |
57 | #define DA8XX_CFGCHIP0_REG 0x17c | 57 | #define DA8XX_CFGCHIP0_REG 0x17c |
58 | #define DA8XX_CFGCHIP1_REG 0x180 | ||
58 | #define DA8XX_CFGCHIP2_REG 0x184 | 59 | #define DA8XX_CFGCHIP2_REG 0x184 |
59 | #define DA8XX_CFGCHIP3_REG 0x188 | 60 | #define DA8XX_CFGCHIP3_REG 0x188 |
60 | 61 | ||