diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-08-05 11:14:15 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-08-07 04:55:48 -0400 |
commit | a09e64fbc0094e3073dbb09c3b4bfe4ab669244b (patch) | |
tree | 69689f467179891b498bd7423fcf61925173db31 /arch/arm/mach-davinci | |
parent | a1b81a84fff05dbfef45b7012c26e1fee9973e5d (diff) |
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
This just leaves include/asm-arm/plat-* to deal with.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-davinci')
27 files changed, 856 insertions, 19 deletions
diff --git a/arch/arm/mach-davinci/board-evm.c b/arch/arm/mach-davinci/board-evm.c index 7497619e4a8a..134355787814 100644 --- a/arch/arm/mach-davinci/board-evm.c +++ b/arch/arm/mach-davinci/board-evm.c | |||
@@ -20,13 +20,13 @@ | |||
20 | #include <asm/setup.h> | 20 | #include <asm/setup.h> |
21 | #include <asm/io.h> | 21 | #include <asm/io.h> |
22 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
23 | #include <asm/arch/hardware.h> | 23 | #include <mach/hardware.h> |
24 | 24 | ||
25 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
27 | #include <asm/mach/flash.h> | 27 | #include <asm/mach/flash.h> |
28 | 28 | ||
29 | #include <asm/arch/common.h> | 29 | #include <mach/common.h> |
30 | 30 | ||
31 | /* other misc. init functions */ | 31 | /* other misc. init functions */ |
32 | void __init davinci_psc_init(void); | 32 | void __init davinci_psc_init(void); |
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index 0014fb1c6eba..d46c69b55aaa 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c | |||
@@ -17,10 +17,10 @@ | |||
17 | #include <linux/mutex.h> | 17 | #include <linux/mutex.h> |
18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
19 | 19 | ||
20 | #include <asm/arch/hardware.h> | 20 | #include <mach/hardware.h> |
21 | #include <asm/io.h> | 21 | #include <asm/io.h> |
22 | 22 | ||
23 | #include <asm/arch/psc.h> | 23 | #include <mach/psc.h> |
24 | #include "clock.h" | 24 | #include "clock.h" |
25 | 25 | ||
26 | /* PLL/Reset register offsets */ | 26 | /* PLL/Reset register offsets */ |
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 9c67886e7189..c9cb4f09b18f 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c | |||
@@ -20,9 +20,9 @@ | |||
20 | #include <linux/irq.h> | 20 | #include <linux/irq.h> |
21 | #include <linux/bitops.h> | 21 | #include <linux/bitops.h> |
22 | 22 | ||
23 | #include <asm/arch/irqs.h> | 23 | #include <mach/irqs.h> |
24 | #include <asm/arch/hardware.h> | 24 | #include <mach/hardware.h> |
25 | #include <asm/arch/gpio.h> | 25 | #include <mach/gpio.h> |
26 | 26 | ||
27 | #include <asm/mach/irq.h> | 27 | #include <asm/mach/irq.h> |
28 | 28 | ||
diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h new file mode 100644 index 000000000000..38bdd49bc181 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/clock.h | |||
@@ -0,0 +1,22 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-davinci/include/mach/clock.h | ||
3 | * | ||
4 | * Clock control driver for DaVinci - header file | ||
5 | * | ||
6 | * Authors: Vladimir Barinov <source@mvista.com> | ||
7 | * | ||
8 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
9 | * the terms of the GNU General Public License version 2. This program | ||
10 | * is licensed "as is" without any warranty of any kind, whether express | ||
11 | * or implied. | ||
12 | */ | ||
13 | #ifndef __ASM_ARCH_DAVINCI_CLOCK_H | ||
14 | #define __ASM_ARCH_DAVINCI_CLOCK_H | ||
15 | |||
16 | struct clk; | ||
17 | |||
18 | extern int clk_register(struct clk *clk); | ||
19 | extern void clk_unregister(struct clk *clk); | ||
20 | extern int davinci_clk_init(void); | ||
21 | |||
22 | #endif | ||
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h new file mode 100644 index 000000000000..a97dfbb15e57 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/common.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * Header for code common to all DaVinci machines. | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | |||
12 | #ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H | ||
13 | #define __ARCH_ARM_MACH_DAVINCI_COMMON_H | ||
14 | |||
15 | struct sys_timer; | ||
16 | |||
17 | extern struct sys_timer davinci_timer; | ||
18 | |||
19 | #endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S new file mode 100644 index 000000000000..e6c0f0d5d062 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/debug-macro.S | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * Debugging macro for DaVinci | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | |||
12 | .macro addruart, rx | ||
13 | mrc p15, 0, \rx, c1, c0 | ||
14 | tst \rx, #1 @ MMU enabled? | ||
15 | moveq \rx, #0x01000000 @ physical base address | ||
16 | movne \rx, #0xfe000000 @ virtual base | ||
17 | orr \rx, \rx, #0x00c20000 @ UART 0 | ||
18 | .endm | ||
19 | |||
20 | #define UART_SHIFT 2 | ||
21 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/arch/arm/mach-davinci/include/mach/dma.h b/arch/arm/mach-davinci/include/mach/dma.h new file mode 100644 index 000000000000..8e2f2d0ba667 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/dma.h | |||
@@ -0,0 +1,16 @@ | |||
1 | /* | ||
2 | * DaVinci DMA definitions | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_DMA_H | ||
12 | #define __ASM_ARCH_DMA_H | ||
13 | |||
14 | #define MAX_DMA_ADDRESS 0xffffffff | ||
15 | |||
16 | #endif /* __ASM_ARCH_DMA_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S new file mode 100644 index 000000000000..039b84f933b3 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/entry-macro.S | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * Low-level IRQ helper macros for TI DaVinci-based platforms | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #include <mach/io.h> | ||
12 | #include <mach/irqs.h> | ||
13 | |||
14 | .macro disable_fiq | ||
15 | .endm | ||
16 | |||
17 | .macro get_irqnr_preamble, base, tmp | ||
18 | ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE) | ||
19 | .endm | ||
20 | |||
21 | .macro arch_ret_to_user, tmp1, tmp2 | ||
22 | .endm | ||
23 | |||
24 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
25 | ldr \tmp, [\base, #0x14] | ||
26 | mov \tmp, \tmp, lsr #2 | ||
27 | sub \irqnr, \tmp, #1 | ||
28 | cmp \tmp, #0 | ||
29 | .endm | ||
30 | |||
31 | .macro irq_prio_table | ||
32 | .endm | ||
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h new file mode 100644 index 000000000000..ec151ccf1e8f --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/gpio.h | |||
@@ -0,0 +1,159 @@ | |||
1 | /* | ||
2 | * TI DaVinci GPIO Support | ||
3 | * | ||
4 | * Copyright (c) 2006 David Brownell | ||
5 | * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | */ | ||
12 | |||
13 | #ifndef __DAVINCI_GPIO_H | ||
14 | #define __DAVINCI_GPIO_H | ||
15 | |||
16 | #include <linux/io.h> | ||
17 | #include <mach/hardware.h> | ||
18 | |||
19 | /* | ||
20 | * basic gpio routines | ||
21 | * | ||
22 | * board-specific init should be done by arch/.../.../board-XXX.c (maybe | ||
23 | * initializing banks together) rather than boot loaders; kexec() won't | ||
24 | * go through boot loaders. | ||
25 | * | ||
26 | * the gpio clock will be turned on when gpios are used, and you may also | ||
27 | * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are | ||
28 | * used as gpios, not with other peripherals. | ||
29 | * | ||
30 | * GPIOs are numbered 0..(DAVINCI_N_GPIO-1). For documentation, and maybe | ||
31 | * for later updates, code should write GPIO(N) or: | ||
32 | * - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53) | ||
33 | * - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70) | ||
34 | * | ||
35 | * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc | ||
36 | * for now, that's != GPIO(N) | ||
37 | */ | ||
38 | #define GPIO(X) (X) /* 0 <= X <= 70 */ | ||
39 | #define GPIOV18(X) (X) /* 1.8V i/o; 0 <= X <= 53 */ | ||
40 | #define GPIOV33(X) ((X)+54) /* 3.3V i/o; 0 <= X <= 17 */ | ||
41 | |||
42 | struct gpio_controller { | ||
43 | u32 dir; | ||
44 | u32 out_data; | ||
45 | u32 set_data; | ||
46 | u32 clr_data; | ||
47 | u32 in_data; | ||
48 | u32 set_rising; | ||
49 | u32 clr_rising; | ||
50 | u32 set_falling; | ||
51 | u32 clr_falling; | ||
52 | u32 intstat; | ||
53 | }; | ||
54 | |||
55 | /* The __gpio_to_controller() and __gpio_mask() functions inline to constants | ||
56 | * with constant parameters; or in outlined code they execute at runtime. | ||
57 | * | ||
58 | * You'd access the controller directly when reading or writing more than | ||
59 | * one gpio value at a time, and to support wired logic where the value | ||
60 | * being driven by the cpu need not match the value read back. | ||
61 | * | ||
62 | * These are NOT part of the cross-platform GPIO interface | ||
63 | */ | ||
64 | static inline struct gpio_controller *__iomem | ||
65 | __gpio_to_controller(unsigned gpio) | ||
66 | { | ||
67 | void *__iomem ptr; | ||
68 | |||
69 | if (gpio < 32) | ||
70 | ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10); | ||
71 | else if (gpio < 64) | ||
72 | ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38); | ||
73 | else if (gpio < DAVINCI_N_GPIO) | ||
74 | ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60); | ||
75 | else | ||
76 | ptr = NULL; | ||
77 | return ptr; | ||
78 | } | ||
79 | |||
80 | static inline u32 __gpio_mask(unsigned gpio) | ||
81 | { | ||
82 | return 1 << (gpio % 32); | ||
83 | } | ||
84 | |||
85 | /* The get/set/clear functions will inline when called with constant | ||
86 | * parameters, for low-overhead bitbanging. Illegal constant parameters | ||
87 | * cause link-time errors. | ||
88 | * | ||
89 | * Otherwise, calls with variable parameters use outlined functions. | ||
90 | */ | ||
91 | extern int __error_inval_gpio(void); | ||
92 | |||
93 | extern void __gpio_set(unsigned gpio, int value); | ||
94 | extern int __gpio_get(unsigned gpio); | ||
95 | |||
96 | static inline void gpio_set_value(unsigned gpio, int value) | ||
97 | { | ||
98 | if (__builtin_constant_p(value)) { | ||
99 | struct gpio_controller *__iomem g; | ||
100 | u32 mask; | ||
101 | |||
102 | if (gpio >= DAVINCI_N_GPIO) | ||
103 | __error_inval_gpio(); | ||
104 | |||
105 | g = __gpio_to_controller(gpio); | ||
106 | mask = __gpio_mask(gpio); | ||
107 | if (value) | ||
108 | __raw_writel(mask, &g->set_data); | ||
109 | else | ||
110 | __raw_writel(mask, &g->clr_data); | ||
111 | return; | ||
112 | } | ||
113 | |||
114 | __gpio_set(gpio, value); | ||
115 | } | ||
116 | |||
117 | /* Returns zero or nonzero; works for gpios configured as inputs OR | ||
118 | * as outputs. | ||
119 | * | ||
120 | * NOTE: changes in reported values are synchronized to the GPIO clock. | ||
121 | * This is most easily seen after calling gpio_set_value() and then immediatly | ||
122 | * gpio_get_value(), where the gpio_get_value() would return the old value | ||
123 | * until the GPIO clock ticks and the new value gets latched. | ||
124 | */ | ||
125 | |||
126 | static inline int gpio_get_value(unsigned gpio) | ||
127 | { | ||
128 | struct gpio_controller *__iomem g; | ||
129 | |||
130 | if (!__builtin_constant_p(gpio)) | ||
131 | return __gpio_get(gpio); | ||
132 | |||
133 | if (gpio >= DAVINCI_N_GPIO) | ||
134 | return __error_inval_gpio(); | ||
135 | |||
136 | g = __gpio_to_controller(gpio); | ||
137 | return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data)); | ||
138 | } | ||
139 | |||
140 | /* powerup default direction is IN */ | ||
141 | extern int gpio_direction_input(unsigned gpio); | ||
142 | extern int gpio_direction_output(unsigned gpio, int value); | ||
143 | |||
144 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | ||
145 | |||
146 | extern int gpio_request(unsigned gpio, const char *tag); | ||
147 | extern void gpio_free(unsigned gpio); | ||
148 | |||
149 | static inline int gpio_to_irq(unsigned gpio) | ||
150 | { | ||
151 | return DAVINCI_N_AINTC_IRQ + gpio; | ||
152 | } | ||
153 | |||
154 | static inline int irq_to_gpio(unsigned irq) | ||
155 | { | ||
156 | return irq - DAVINCI_N_AINTC_IRQ; | ||
157 | } | ||
158 | |||
159 | #endif /* __DAVINCI_GPIO_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h new file mode 100644 index 000000000000..a2e8969afaca --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/hardware.h | |||
@@ -0,0 +1,52 @@ | |||
1 | /* | ||
2 | * Common hardware definitions | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_HARDWARE_H | ||
12 | #define __ASM_ARCH_HARDWARE_H | ||
13 | |||
14 | /* | ||
15 | * Base register addresses | ||
16 | */ | ||
17 | #define DAVINCI_DMA_3PCC_BASE (0x01C00000) | ||
18 | #define DAVINCI_DMA_3PTC0_BASE (0x01C10000) | ||
19 | #define DAVINCI_DMA_3PTC1_BASE (0x01C10400) | ||
20 | #define DAVINCI_I2C_BASE (0x01C21000) | ||
21 | #define DAVINCI_PWM0_BASE (0x01C22000) | ||
22 | #define DAVINCI_PWM1_BASE (0x01C22400) | ||
23 | #define DAVINCI_PWM2_BASE (0x01C22800) | ||
24 | #define DAVINCI_SYSTEM_MODULE_BASE (0x01C40000) | ||
25 | #define DAVINCI_PLL_CNTRL0_BASE (0x01C40800) | ||
26 | #define DAVINCI_PLL_CNTRL1_BASE (0x01C40C00) | ||
27 | #define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01C41000) | ||
28 | #define DAVINCI_SYSTEM_DFT_BASE (0x01C42000) | ||
29 | #define DAVINCI_IEEE1394_BASE (0x01C60000) | ||
30 | #define DAVINCI_USB_OTG_BASE (0x01C64000) | ||
31 | #define DAVINCI_CFC_ATA_BASE (0x01C66000) | ||
32 | #define DAVINCI_SPI_BASE (0x01C66800) | ||
33 | #define DAVINCI_GPIO_BASE (0x01C67000) | ||
34 | #define DAVINCI_UHPI_BASE (0x01C67800) | ||
35 | #define DAVINCI_VPSS_REGS_BASE (0x01C70000) | ||
36 | #define DAVINCI_EMAC_CNTRL_REGS_BASE (0x01C80000) | ||
37 | #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE (0x01C81000) | ||
38 | #define DAVINCI_EMAC_WRAPPER_RAM_BASE (0x01C82000) | ||
39 | #define DAVINCI_MDIO_CNTRL_REGS_BASE (0x01C84000) | ||
40 | #define DAVINCI_IMCOP_BASE (0x01CC0000) | ||
41 | #define DAVINCI_ASYNC_EMIF_CNTRL_BASE (0x01E00000) | ||
42 | #define DAVINCI_VLYNQ_BASE (0x01E01000) | ||
43 | #define DAVINCI_MCBSP_BASE (0x01E02000) | ||
44 | #define DAVINCI_MMC_SD_BASE (0x01E10000) | ||
45 | #define DAVINCI_MS_BASE (0x01E20000) | ||
46 | #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) | ||
47 | #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) | ||
48 | #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) | ||
49 | #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) | ||
50 | #define DAVINCI_VLYNQ_REMOTE_BASE (0x0C000000) | ||
51 | |||
52 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/i2c.h b/arch/arm/mach-davinci/include/mach/i2c.h new file mode 100644 index 000000000000..e2f54168abd1 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/i2c.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * DaVinci I2C controller platfrom_device info | ||
3 | * | ||
4 | * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | |||
12 | #ifndef __ASM_ARCH_I2C_H | ||
13 | #define __ASM_ARCH_I2C_H | ||
14 | |||
15 | /* All frequencies are expressed in kHz */ | ||
16 | struct davinci_i2c_platform_data { | ||
17 | unsigned int bus_freq; /* standard bus frequency */ | ||
18 | unsigned int bus_delay; /* transaction delay */ | ||
19 | }; | ||
20 | |||
21 | #endif /* __ASM_ARCH_I2C_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h new file mode 100644 index 000000000000..e7accb910864 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/io.h | |||
@@ -0,0 +1,79 @@ | |||
1 | /* | ||
2 | * DaVinci IO address definitions | ||
3 | * | ||
4 | * Copied from include/asm/arm/arch-omap/io.h | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_IO_H | ||
12 | #define __ASM_ARCH_IO_H | ||
13 | |||
14 | #define IO_SPACE_LIMIT 0xffffffff | ||
15 | |||
16 | /* | ||
17 | * ---------------------------------------------------------------------------- | ||
18 | * I/O mapping | ||
19 | * ---------------------------------------------------------------------------- | ||
20 | */ | ||
21 | #define IO_PHYS 0x01c00000 | ||
22 | #define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ | ||
23 | #define IO_SIZE 0x00400000 | ||
24 | #define IO_VIRT (IO_PHYS + IO_OFFSET) | ||
25 | #define io_p2v(pa) ((pa) + IO_OFFSET) | ||
26 | #define io_v2p(va) ((va) - IO_OFFSET) | ||
27 | #define IO_ADDRESS(x) io_p2v(x) | ||
28 | |||
29 | /* | ||
30 | * We don't actually have real ISA nor PCI buses, but there is so many | ||
31 | * drivers out there that might just work if we fake them... | ||
32 | */ | ||
33 | #define PCIO_BASE 0 | ||
34 | #define __io(a) ((void __iomem *)(PCIO_BASE + (a))) | ||
35 | #define __mem_pci(a) (a) | ||
36 | #define __mem_isa(a) (a) | ||
37 | |||
38 | #ifndef __ASSEMBLER__ | ||
39 | |||
40 | /* | ||
41 | * Functions to access the DaVinci IO region | ||
42 | * | ||
43 | * NOTE: - Use davinci_read/write[bwl] for physical register addresses | ||
44 | * - Use __raw_read/write[bwl]() for virtual register addresses | ||
45 | * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses | ||
46 | * - DO NOT use hardcoded virtual addresses to allow changing the | ||
47 | * IO address space again if needed | ||
48 | */ | ||
49 | #define davinci_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) | ||
50 | #define davinci_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) | ||
51 | #define davinci_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) | ||
52 | |||
53 | #define davinci_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) | ||
54 | #define davinci_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) | ||
55 | #define davinci_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) | ||
56 | |||
57 | /* 16 bit uses LDRH/STRH, base +/- offset_8 */ | ||
58 | typedef struct { volatile u16 offset[256]; } __regbase16; | ||
59 | #define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \ | ||
60 | ->offset[((vaddr)&0xff)>>1] | ||
61 | #define __REG16(paddr) __REGV16(io_p2v(paddr)) | ||
62 | |||
63 | /* 8/32 bit uses LDR/STR, base +/- offset_12 */ | ||
64 | typedef struct { volatile u8 offset[4096]; } __regbase8; | ||
65 | #define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \ | ||
66 | ->offset[((vaddr)&4095)>>0] | ||
67 | #define __REG8(paddr) __REGV8(io_p2v(paddr)) | ||
68 | |||
69 | typedef struct { volatile u32 offset[4096]; } __regbase32; | ||
70 | #define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \ | ||
71 | ->offset[((vaddr)&4095)>>2] | ||
72 | |||
73 | #define __REG(paddr) __REGV32(io_p2v(paddr)) | ||
74 | #else | ||
75 | |||
76 | #define __REG(x) (*((volatile unsigned long *)io_p2v(x))) | ||
77 | |||
78 | #endif /* __ASSEMBLER__ */ | ||
79 | #endif /* __ASM_ARCH_IO_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h new file mode 100644 index 000000000000..f4c5ca6da9f4 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/irqs.h | |||
@@ -0,0 +1,105 @@ | |||
1 | /* | ||
2 | * DaVinci interrupt controller definitions | ||
3 | * | ||
4 | * Copyright (C) 2006 Texas Instruments. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | * | ||
11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
14 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
15 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
16 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
17 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
18 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
19 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
20 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
21 | * | ||
22 | * You should have received a copy of the GNU General Public License along | ||
23 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
24 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
25 | * | ||
26 | */ | ||
27 | #ifndef __ASM_ARCH_IRQS_H | ||
28 | #define __ASM_ARCH_IRQS_H | ||
29 | |||
30 | /* Base address */ | ||
31 | #define DAVINCI_ARM_INTC_BASE 0x01C48000 | ||
32 | |||
33 | /* Interrupt lines */ | ||
34 | #define IRQ_VDINT0 0 | ||
35 | #define IRQ_VDINT1 1 | ||
36 | #define IRQ_VDINT2 2 | ||
37 | #define IRQ_HISTINT 3 | ||
38 | #define IRQ_H3AINT 4 | ||
39 | #define IRQ_PRVUINT 5 | ||
40 | #define IRQ_RSZINT 6 | ||
41 | #define IRQ_VFOCINT 7 | ||
42 | #define IRQ_VENCINT 8 | ||
43 | #define IRQ_ASQINT 9 | ||
44 | #define IRQ_IMXINT 10 | ||
45 | #define IRQ_VLCDINT 11 | ||
46 | #define IRQ_USBINT 12 | ||
47 | #define IRQ_EMACINT 13 | ||
48 | |||
49 | #define IRQ_CCINT0 16 | ||
50 | #define IRQ_CCERRINT 17 | ||
51 | #define IRQ_TCERRINT0 18 | ||
52 | #define IRQ_TCERRINT 19 | ||
53 | #define IRQ_PSCIN 20 | ||
54 | |||
55 | #define IRQ_IDE 22 | ||
56 | #define IRQ_HPIINT 23 | ||
57 | #define IRQ_MBXINT 24 | ||
58 | #define IRQ_MBRINT 25 | ||
59 | #define IRQ_MMCINT 26 | ||
60 | #define IRQ_SDIOINT 27 | ||
61 | #define IRQ_MSINT 28 | ||
62 | #define IRQ_DDRINT 29 | ||
63 | #define IRQ_AEMIFINT 30 | ||
64 | #define IRQ_VLQINT 31 | ||
65 | #define IRQ_TINT0_TINT12 32 | ||
66 | #define IRQ_TINT0_TINT34 33 | ||
67 | #define IRQ_TINT1_TINT12 34 | ||
68 | #define IRQ_TINT1_TINT34 35 | ||
69 | #define IRQ_PWMINT0 36 | ||
70 | #define IRQ_PWMINT1 37 | ||
71 | #define IRQ_PWMINT2 38 | ||
72 | #define IRQ_I2C 39 | ||
73 | #define IRQ_UARTINT0 40 | ||
74 | #define IRQ_UARTINT1 41 | ||
75 | #define IRQ_UARTINT2 42 | ||
76 | #define IRQ_SPINT0 43 | ||
77 | #define IRQ_SPINT1 44 | ||
78 | |||
79 | #define IRQ_DSP2ARM0 46 | ||
80 | #define IRQ_DSP2ARM1 47 | ||
81 | #define IRQ_GPIO0 48 | ||
82 | #define IRQ_GPIO1 49 | ||
83 | #define IRQ_GPIO2 50 | ||
84 | #define IRQ_GPIO3 51 | ||
85 | #define IRQ_GPIO4 52 | ||
86 | #define IRQ_GPIO5 53 | ||
87 | #define IRQ_GPIO6 54 | ||
88 | #define IRQ_GPIO7 55 | ||
89 | #define IRQ_GPIOBNK0 56 | ||
90 | #define IRQ_GPIOBNK1 57 | ||
91 | #define IRQ_GPIOBNK2 58 | ||
92 | #define IRQ_GPIOBNK3 59 | ||
93 | #define IRQ_GPIOBNK4 60 | ||
94 | #define IRQ_COMMTX 61 | ||
95 | #define IRQ_COMMRX 62 | ||
96 | #define IRQ_EMUINT 63 | ||
97 | |||
98 | #define DAVINCI_N_AINTC_IRQ 64 | ||
99 | #define DAVINCI_N_GPIO 71 | ||
100 | |||
101 | #define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) | ||
102 | |||
103 | #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 | ||
104 | |||
105 | #endif /* __ASM_ARCH_IRQS_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h new file mode 100644 index 000000000000..dd1625c23cf4 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/memory.h | |||
@@ -0,0 +1,64 @@ | |||
1 | /* | ||
2 | * DaVinci memory space definitions | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_MEMORY_H | ||
12 | #define __ASM_ARCH_MEMORY_H | ||
13 | |||
14 | /************************************************************************** | ||
15 | * Included Files | ||
16 | **************************************************************************/ | ||
17 | #include <asm/page.h> | ||
18 | #include <asm/sizes.h> | ||
19 | |||
20 | /************************************************************************** | ||
21 | * Definitions | ||
22 | **************************************************************************/ | ||
23 | #define DAVINCI_DDR_BASE 0x80000000 | ||
24 | #define DAVINCI_IRAM_BASE 0x00008000 /* ARM Internal RAM */ | ||
25 | |||
26 | #define PHYS_OFFSET DAVINCI_DDR_BASE | ||
27 | |||
28 | /* | ||
29 | * Increase size of DMA-consistent memory region | ||
30 | */ | ||
31 | #define CONSISTENT_DMA_SIZE (14<<20) | ||
32 | |||
33 | #ifndef __ASSEMBLY__ | ||
34 | /* | ||
35 | * Restrict DMA-able region to workaround silicon bug. The bug | ||
36 | * restricts buffers available for DMA to video hardware to be | ||
37 | * below 128M | ||
38 | */ | ||
39 | static inline void | ||
40 | __arch_adjust_zones(int node, unsigned long *size, unsigned long *holes) | ||
41 | { | ||
42 | unsigned int sz = (128<<20) >> PAGE_SHIFT; | ||
43 | |||
44 | if (node != 0) | ||
45 | sz = 0; | ||
46 | |||
47 | size[1] = size[0] - sz; | ||
48 | size[0] = sz; | ||
49 | } | ||
50 | |||
51 | #define arch_adjust_zones(node, zone_size, holes) \ | ||
52 | if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes) | ||
53 | |||
54 | #define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1) | ||
55 | |||
56 | #endif | ||
57 | |||
58 | /* | ||
59 | * Bus address is physical address | ||
60 | */ | ||
61 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
62 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
63 | |||
64 | #endif /* __ASM_ARCH_MEMORY_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h new file mode 100644 index 000000000000..c24b6782804d --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/mux.h | |||
@@ -0,0 +1,55 @@ | |||
1 | /* | ||
2 | * DaVinci pin multiplexing defines | ||
3 | * | ||
4 | * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_MUX_H | ||
12 | #define __ASM_ARCH_MUX_H | ||
13 | |||
14 | #define DAVINCI_MUX_AEAW0 0 | ||
15 | #define DAVINCI_MUX_AEAW1 1 | ||
16 | #define DAVINCI_MUX_AEAW2 2 | ||
17 | #define DAVINCI_MUX_AEAW3 3 | ||
18 | #define DAVINCI_MUX_AEAW4 4 | ||
19 | #define DAVINCI_MUX_AECS4 10 | ||
20 | #define DAVINCI_MUX_AECS5 11 | ||
21 | #define DAVINCI_MUX_VLYNQWD0 12 | ||
22 | #define DAVINCI_MUX_VLYNQWD1 13 | ||
23 | #define DAVINCI_MUX_VLSCREN 14 | ||
24 | #define DAVINCI_MUX_VLYNQEN 15 | ||
25 | #define DAVINCI_MUX_HDIREN 16 | ||
26 | #define DAVINCI_MUX_ATAEN 17 | ||
27 | #define DAVINCI_MUX_RGB666 22 | ||
28 | #define DAVINCI_MUX_RGB888 23 | ||
29 | #define DAVINCI_MUX_LOEEN 24 | ||
30 | #define DAVINCI_MUX_LFLDEN 25 | ||
31 | #define DAVINCI_MUX_CWEN 26 | ||
32 | #define DAVINCI_MUX_CFLDEN 27 | ||
33 | #define DAVINCI_MUX_HPIEN 29 | ||
34 | #define DAVINCI_MUX_1394EN 30 | ||
35 | #define DAVINCI_MUX_EMACEN 31 | ||
36 | |||
37 | #define DAVINCI_MUX_LEVEL2 32 | ||
38 | #define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0) | ||
39 | #define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1) | ||
40 | #define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2) | ||
41 | #define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3) | ||
42 | #define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4) | ||
43 | #define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5) | ||
44 | #define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6) | ||
45 | #define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7) | ||
46 | #define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8) | ||
47 | #define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9) | ||
48 | #define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10) | ||
49 | #define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16) | ||
50 | #define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17) | ||
51 | #define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18) | ||
52 | |||
53 | extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable); | ||
54 | |||
55 | #endif /* __ASM_ARCH_MUX_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h new file mode 100644 index 000000000000..4977aa071e1e --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/psc.h | |||
@@ -0,0 +1,76 @@ | |||
1 | /* | ||
2 | * DaVinci Power & Sleep Controller (PSC) defines | ||
3 | * | ||
4 | * Copyright (C) 2006 Texas Instruments. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | * | ||
11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
14 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
15 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
16 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
17 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
18 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
19 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
20 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
21 | * | ||
22 | * You should have received a copy of the GNU General Public License along | ||
23 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
24 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
25 | * | ||
26 | */ | ||
27 | #ifndef __ASM_ARCH_PSC_H | ||
28 | #define __ASM_ARCH_PSC_H | ||
29 | |||
30 | /* Power and Sleep Controller (PSC) Domains */ | ||
31 | #define DAVINCI_GPSC_ARMDOMAIN 0 | ||
32 | #define DAVINCI_GPSC_DSPDOMAIN 1 | ||
33 | |||
34 | #define DAVINCI_LPSC_VPSSMSTR 0 | ||
35 | #define DAVINCI_LPSC_VPSSSLV 1 | ||
36 | #define DAVINCI_LPSC_TPCC 2 | ||
37 | #define DAVINCI_LPSC_TPTC0 3 | ||
38 | #define DAVINCI_LPSC_TPTC1 4 | ||
39 | #define DAVINCI_LPSC_EMAC 5 | ||
40 | #define DAVINCI_LPSC_EMAC_WRAPPER 6 | ||
41 | #define DAVINCI_LPSC_MDIO 7 | ||
42 | #define DAVINCI_LPSC_IEEE1394 8 | ||
43 | #define DAVINCI_LPSC_USB 9 | ||
44 | #define DAVINCI_LPSC_ATA 10 | ||
45 | #define DAVINCI_LPSC_VLYNQ 11 | ||
46 | #define DAVINCI_LPSC_UHPI 12 | ||
47 | #define DAVINCI_LPSC_DDR_EMIF 13 | ||
48 | #define DAVINCI_LPSC_AEMIF 14 | ||
49 | #define DAVINCI_LPSC_MMC_SD 15 | ||
50 | #define DAVINCI_LPSC_MEMSTICK 16 | ||
51 | #define DAVINCI_LPSC_McBSP 17 | ||
52 | #define DAVINCI_LPSC_I2C 18 | ||
53 | #define DAVINCI_LPSC_UART0 19 | ||
54 | #define DAVINCI_LPSC_UART1 20 | ||
55 | #define DAVINCI_LPSC_UART2 21 | ||
56 | #define DAVINCI_LPSC_SPI 22 | ||
57 | #define DAVINCI_LPSC_PWM0 23 | ||
58 | #define DAVINCI_LPSC_PWM1 24 | ||
59 | #define DAVINCI_LPSC_PWM2 25 | ||
60 | #define DAVINCI_LPSC_GPIO 26 | ||
61 | #define DAVINCI_LPSC_TIMER0 27 | ||
62 | #define DAVINCI_LPSC_TIMER1 28 | ||
63 | #define DAVINCI_LPSC_TIMER2 29 | ||
64 | #define DAVINCI_LPSC_SYSTEM_SUBSYS 30 | ||
65 | #define DAVINCI_LPSC_ARM 31 | ||
66 | #define DAVINCI_LPSC_SCR2 32 | ||
67 | #define DAVINCI_LPSC_SCR3 33 | ||
68 | #define DAVINCI_LPSC_SCR4 34 | ||
69 | #define DAVINCI_LPSC_CROSSBAR 35 | ||
70 | #define DAVINCI_LPSC_CFG27 36 | ||
71 | #define DAVINCI_LPSC_CFG3 37 | ||
72 | #define DAVINCI_LPSC_CFG5 38 | ||
73 | #define DAVINCI_LPSC_GEM 39 | ||
74 | #define DAVINCI_LPSC_IMCOP 40 | ||
75 | |||
76 | #endif /* __ASM_ARCH_PSC_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h new file mode 100644 index 000000000000..fb8cb229bfd2 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/serial.h | |||
@@ -0,0 +1,20 @@ | |||
1 | /* | ||
2 | * DaVinci serial device definitions | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_SERIAL_H | ||
12 | #define __ASM_ARCH_SERIAL_H | ||
13 | |||
14 | #include <mach/io.h> | ||
15 | |||
16 | #define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) | ||
17 | #define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) | ||
18 | #define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) | ||
19 | |||
20 | #endif /* __ASM_ARCH_SERIAL_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h new file mode 100644 index 000000000000..84ff77aeb738 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/system.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * DaVinci system defines | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_SYSTEM_H | ||
12 | #define __ASM_ARCH_SYSTEM_H | ||
13 | |||
14 | #include <asm/io.h> | ||
15 | #include <mach/hardware.h> | ||
16 | |||
17 | extern void davinci_watchdog_reset(void); | ||
18 | |||
19 | static void arch_idle(void) | ||
20 | { | ||
21 | cpu_do_idle(); | ||
22 | } | ||
23 | |||
24 | static void arch_reset(char mode) | ||
25 | { | ||
26 | davinci_watchdog_reset(); | ||
27 | } | ||
28 | |||
29 | #endif /* __ASM_ARCH_SYSTEM_H */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/timex.h b/arch/arm/mach-davinci/include/mach/timex.h new file mode 100644 index 000000000000..52827567841d --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/timex.h | |||
@@ -0,0 +1,17 @@ | |||
1 | /* | ||
2 | * DaVinci timer defines | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #ifndef __ASM_ARCH_TIMEX_H | ||
12 | #define __ASM_ARCH_TIMEX_H | ||
13 | |||
14 | /* The source frequency for the timers is the 27MHz clock */ | ||
15 | #define CLOCK_TICK_RATE 27000000 | ||
16 | |||
17 | #endif /* __ASM_ARCH_TIMEX_H__ */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h new file mode 100644 index 000000000000..8c165def37b6 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/uncompress.h | |||
@@ -0,0 +1,35 @@ | |||
1 | /* | ||
2 | * Serial port stubs for kernel decompress status messages | ||
3 | * | ||
4 | * Author: Anant Gole | ||
5 | * (C) Copyright (C) 2006, Texas Instruments, Inc | ||
6 | * | ||
7 | * This file is licensed under the terms of the GNU General Public License | ||
8 | * version 2. This program is licensed "as is" without any warranty of any | ||
9 | * kind, whether express or implied. | ||
10 | */ | ||
11 | |||
12 | #include <linux/types.h> | ||
13 | #include <linux/serial_reg.h> | ||
14 | #include <mach/serial.h> | ||
15 | |||
16 | /* PORT_16C550A, in polled non-fifo mode */ | ||
17 | |||
18 | static void putc(char c) | ||
19 | { | ||
20 | volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; | ||
21 | |||
22 | while (!(uart[UART_LSR] & UART_LSR_THRE)) | ||
23 | barrier(); | ||
24 | uart[UART_TX] = c; | ||
25 | } | ||
26 | |||
27 | static inline void flush(void) | ||
28 | { | ||
29 | volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; | ||
30 | while (!(uart[UART_LSR] & UART_LSR_THRE)) | ||
31 | barrier(); | ||
32 | } | ||
33 | |||
34 | #define arch_decomp_setup() | ||
35 | #define arch_decomp_wdog() | ||
diff --git a/arch/arm/mach-davinci/include/mach/vmalloc.h b/arch/arm/mach-davinci/include/mach/vmalloc.h new file mode 100644 index 000000000000..b98bd9e92fd6 --- /dev/null +++ b/arch/arm/mach-davinci/include/mach/vmalloc.h | |||
@@ -0,0 +1,15 @@ | |||
1 | /* | ||
2 | * DaVinci vmalloc definitions | ||
3 | * | ||
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | ||
5 | * | ||
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | ||
7 | * the terms of the GNU General Public License version 2. This program | ||
8 | * is licensed "as is" without any warranty of any kind, whether express | ||
9 | * or implied. | ||
10 | */ | ||
11 | #include <asm/memory.h> | ||
12 | #include <mach/io.h> | ||
13 | |||
14 | /* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ | ||
15 | #define VMALLOC_END (IO_VIRT - (2<<20)) | ||
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c index 47787ff84a6a..5bb66b61c1a3 100644 --- a/arch/arm/mach-davinci/io.c +++ b/arch/arm/mach-davinci/io.c | |||
@@ -17,7 +17,7 @@ | |||
17 | #include <asm/memory.h> | 17 | #include <asm/memory.h> |
18 | 18 | ||
19 | #include <asm/mach/map.h> | 19 | #include <asm/mach/map.h> |
20 | #include <asm/arch/clock.h> | 20 | #include <mach/clock.h> |
21 | 21 | ||
22 | extern void davinci_check_revision(void); | 22 | extern void davinci_check_revision(void); |
23 | 23 | ||
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c index 090580ed88ef..12ca9f29f847 100644 --- a/arch/arm/mach-davinci/irq.c +++ b/arch/arm/mach-davinci/irq.c | |||
@@ -23,7 +23,7 @@ | |||
23 | #include <linux/interrupt.h> | 23 | #include <linux/interrupt.h> |
24 | #include <linux/irq.h> | 24 | #include <linux/irq.h> |
25 | 25 | ||
26 | #include <asm/arch/hardware.h> | 26 | #include <mach/hardware.h> |
27 | #include <asm/io.h> | 27 | #include <asm/io.h> |
28 | #include <asm/mach/irq.h> | 28 | #include <asm/mach/irq.h> |
29 | 29 | ||
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c index 439bf94bdc4e..8ff9d8aca60b 100644 --- a/arch/arm/mach-davinci/mux.c +++ b/arch/arm/mach-davinci/mux.c | |||
@@ -11,9 +11,9 @@ | |||
11 | #include <linux/io.h> | 11 | #include <linux/io.h> |
12 | #include <linux/spinlock.h> | 12 | #include <linux/spinlock.h> |
13 | 13 | ||
14 | #include <asm/arch/hardware.h> | 14 | #include <mach/hardware.h> |
15 | 15 | ||
16 | #include <asm/arch/mux.h> | 16 | #include <mach/mux.h> |
17 | 17 | ||
18 | /* System control register offsets */ | 18 | /* System control register offsets */ |
19 | #define PINMUX0 0x00 | 19 | #define PINMUX0 0x00 |
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index 753f0ba81a44..720c48b9ee04 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c | |||
@@ -23,9 +23,9 @@ | |||
23 | #include <linux/init.h> | 23 | #include <linux/init.h> |
24 | 24 | ||
25 | #include <asm/io.h> | 25 | #include <asm/io.h> |
26 | #include <asm/arch/hardware.h> | 26 | #include <mach/hardware.h> |
27 | #include <asm/arch/psc.h> | 27 | #include <mach/psc.h> |
28 | #include <asm/arch/mux.h> | 28 | #include <mach/mux.h> |
29 | 29 | ||
30 | /* PSC register offsets */ | 30 | /* PSC register offsets */ |
31 | #define EPCPR 0x070 | 31 | #define EPCPR 0x070 |
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c index c2b812f3391c..caf101e2cc62 100644 --- a/arch/arm/mach-davinci/serial.c +++ b/arch/arm/mach-davinci/serial.c | |||
@@ -29,9 +29,9 @@ | |||
29 | 29 | ||
30 | #include <asm/io.h> | 30 | #include <asm/io.h> |
31 | #include <asm/irq.h> | 31 | #include <asm/irq.h> |
32 | #include <asm/arch/hardware.h> | 32 | #include <mach/hardware.h> |
33 | #include <asm/arch/serial.h> | 33 | #include <mach/serial.h> |
34 | #include <asm/arch/irqs.h> | 34 | #include <mach/irqs.h> |
35 | 35 | ||
36 | #define UART_DAVINCI_PWREMU 0x0c | 36 | #define UART_DAVINCI_PWREMU 0x0c |
37 | 37 | ||
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c index 50c3b54c4ccd..206e80d41717 100644 --- a/arch/arm/mach-davinci/time.c +++ b/arch/arm/mach-davinci/time.c | |||
@@ -17,13 +17,13 @@ | |||
17 | #include <linux/spinlock.h> | 17 | #include <linux/spinlock.h> |
18 | 18 | ||
19 | #include <asm/io.h> | 19 | #include <asm/io.h> |
20 | #include <asm/arch/hardware.h> | 20 | #include <mach/hardware.h> |
21 | #include <asm/system.h> | 21 | #include <asm/system.h> |
22 | #include <asm/irq.h> | 22 | #include <asm/irq.h> |
23 | #include <asm/mach/irq.h> | 23 | #include <asm/mach/irq.h> |
24 | #include <asm/mach/time.h> | 24 | #include <asm/mach/time.h> |
25 | #include <asm/errno.h> | 25 | #include <asm/errno.h> |
26 | #include <asm/arch/io.h> | 26 | #include <mach/io.h> |
27 | 27 | ||
28 | static struct clock_event_device clockevent_davinci; | 28 | static struct clock_event_device clockevent_davinci; |
29 | 29 | ||