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authorSekhar Nori <nsekhar@ti.com>2010-05-04 04:41:35 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2010-05-06 18:55:38 -0400
commit3f68b98a75381f785f4e13085296c52c75ea29ac (patch)
tree98afc8fde032542324594e175bc2523c40700a1e /arch/arm/mach-davinci
parente2800007f3b9aab51c1fe866034db576d3a9fd83 (diff)
davinci: edma: use a more intuitive name for edma_info
'edma_info' structure inside the edma driver represents a single instance of edma channel controller. Call it 'edma_cc' instead. This also avoids readers confusing it with an instance of edma_soc_info structre which carries the platform data for a single channel controller instance. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci')
-rw-r--r--arch/arm/mach-davinci/dma.c158
1 files changed, 77 insertions, 81 deletions
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 0bf290befa23..b705089e2bef 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -243,7 +243,7 @@ struct edma {
243 } intr_data[EDMA_MAX_DMACH]; 243 } intr_data[EDMA_MAX_DMACH];
244}; 244};
245 245
246static struct edma *edma_info[EDMA_MAX_CC]; 246static struct edma *edma_cc[EDMA_MAX_CC];
247static int arch_num_cc; 247static int arch_num_cc;
248 248
249/* dummy param set used to (re)initialize parameter RAM slots */ 249/* dummy param set used to (re)initialize parameter RAM slots */
@@ -261,7 +261,7 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
261 261
262 /* default to low priority queue */ 262 /* default to low priority queue */
263 if (queue_no == EVENTQ_DEFAULT) 263 if (queue_no == EVENTQ_DEFAULT)
264 queue_no = edma_info[ctlr]->default_queue; 264 queue_no = edma_cc[ctlr]->default_queue;
265 265
266 queue_no &= 7; 266 queue_no &= 7;
267 edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), 267 edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
@@ -315,8 +315,8 @@ setup_dma_interrupt(unsigned lch,
315 (1 << (lch & 0x1f))); 315 (1 << (lch & 0x1f)));
316 } 316 }
317 317
318 edma_info[ctlr]->intr_data[lch].callback = callback; 318 edma_cc[ctlr]->intr_data[lch].callback = callback;
319 edma_info[ctlr]->intr_data[lch].data = data; 319 edma_cc[ctlr]->intr_data[lch].data = data;
320 320
321 if (callback) { 321 if (callback) {
322 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, 322 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
@@ -328,11 +328,10 @@ setup_dma_interrupt(unsigned lch,
328 328
329static int irq2ctlr(int irq) 329static int irq2ctlr(int irq)
330{ 330{
331 if (irq >= edma_info[0]->irq_res_start && 331 if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
332 irq <= edma_info[0]->irq_res_end)
333 return 0; 332 return 0;
334 else if (irq >= edma_info[1]->irq_res_start && 333 else if (irq >= edma_cc[1]->irq_res_start &&
335 irq <= edma_info[1]->irq_res_end) 334 irq <= edma_cc[1]->irq_res_end)
336 return 1; 335 return 1;
337 336
338 return -1; 337 return -1;
@@ -377,10 +376,10 @@ static irqreturn_t dma_irq_handler(int irq, void *data)
377 /* Clear the corresponding IPR bits */ 376 /* Clear the corresponding IPR bits */
378 edma_shadow0_write_array(ctlr, SH_ICR, j, 377 edma_shadow0_write_array(ctlr, SH_ICR, j,
379 (1 << i)); 378 (1 << i));
380 if (edma_info[ctlr]->intr_data[k].callback) { 379 if (edma_cc[ctlr]->intr_data[k].callback) {
381 edma_info[ctlr]->intr_data[k].callback( 380 edma_cc[ctlr]->intr_data[k].callback(
382 k, DMA_COMPLETE, 381 k, DMA_COMPLETE,
383 edma_info[ctlr]->intr_data[k]. 382 edma_cc[ctlr]->intr_data[k].
384 data); 383 data);
385 } 384 }
386 } 385 }
@@ -433,12 +432,12 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
433 /* Clear any SER */ 432 /* Clear any SER */
434 edma_shadow0_write_array(ctlr, SH_SECR, 433 edma_shadow0_write_array(ctlr, SH_SECR,
435 j, (1 << i)); 434 j, (1 << i));
436 if (edma_info[ctlr]->intr_data[k]. 435 if (edma_cc[ctlr]->intr_data[k].
437 callback) { 436 callback) {
438 edma_info[ctlr]->intr_data[k]. 437 edma_cc[ctlr]->intr_data[k].
439 callback(k, 438 callback(k,
440 DMA_CC_ERROR, 439 DMA_CC_ERROR,
441 edma_info[ctlr]->intr_data 440 edma_cc[ctlr]->intr_data
442 [k].data); 441 [k].data);
443 } 442 }
444 } 443 }
@@ -514,9 +513,9 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
514 int stop_slot = start_slot; 513 int stop_slot = start_slot;
515 DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); 514 DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
516 515
517 for (i = start_slot; i < edma_info[ctlr]->num_slots; ++i) { 516 for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
518 j = EDMA_CHAN_SLOT(i); 517 j = EDMA_CHAN_SLOT(i);
519 if (!test_and_set_bit(j, edma_info[ctlr]->edma_inuse)) { 518 if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
520 /* Record our current beginning slot */ 519 /* Record our current beginning slot */
521 if (count == num_slots) 520 if (count == num_slots)
522 stop_slot = i; 521 stop_slot = i;
@@ -543,12 +542,12 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
543 * of contiguous parameter RAM slots but do not find the exact number 542 * of contiguous parameter RAM slots but do not find the exact number
544 * requested as we may reach the total number of parameter RAM slots 543 * requested as we may reach the total number of parameter RAM slots
545 */ 544 */
546 if (i == edma_info[ctlr]->num_slots) 545 if (i == edma_cc[ctlr]->num_slots)
547 stop_slot = i; 546 stop_slot = i;
548 547
549 for (j = start_slot; j < stop_slot; j++) 548 for (j = start_slot; j < stop_slot; j++)
550 if (test_bit(j, tmp_inuse)) 549 if (test_bit(j, tmp_inuse))
551 clear_bit(j, edma_info[ctlr]->edma_inuse); 550 clear_bit(j, edma_cc[ctlr]->edma_inuse);
552 551
553 if (count) 552 if (count)
554 return -EBUSY; 553 return -EBUSY;
@@ -570,7 +569,7 @@ static int prepare_unused_channel_list(struct device *dev, void *data)
570 (int)pdev->resource[i].start >= 0) { 569 (int)pdev->resource[i].start >= 0) {
571 ctlr = EDMA_CTLR(pdev->resource[i].start); 570 ctlr = EDMA_CTLR(pdev->resource[i].start);
572 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), 571 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
573 edma_info[ctlr]->edma_unused); 572 edma_cc[ctlr]->edma_unused);
574 } 573 }
575 } 574 }
576 575
@@ -644,14 +643,13 @@ int edma_alloc_channel(int channel,
644 for (i = 0; i < arch_num_cc; i++) { 643 for (i = 0; i < arch_num_cc; i++) {
645 channel = 0; 644 channel = 0;
646 for (;;) { 645 for (;;) {
647 channel = find_next_bit(edma_info[i]-> 646 channel = find_next_bit(edma_cc[i]->edma_unused,
648 edma_unused, 647 edma_cc[i]->num_channels,
649 edma_info[i]->num_channels,
650 channel); 648 channel);
651 if (channel == edma_info[i]->num_channels) 649 if (channel == edma_cc[i]->num_channels)
652 break; 650 break;
653 if (!test_and_set_bit(channel, 651 if (!test_and_set_bit(channel,
654 edma_info[i]->edma_inuse)) { 652 edma_cc[i]->edma_inuse)) {
655 done = 1; 653 done = 1;
656 ctlr = i; 654 ctlr = i;
657 break; 655 break;
@@ -663,9 +661,9 @@ int edma_alloc_channel(int channel,
663 } 661 }
664 if (!done) 662 if (!done)
665 return -ENOMEM; 663 return -ENOMEM;
666 } else if (channel >= edma_info[ctlr]->num_channels) { 664 } else if (channel >= edma_cc[ctlr]->num_channels) {
667 return -EINVAL; 665 return -EINVAL;
668 } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) { 666 } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
669 return -EBUSY; 667 return -EBUSY;
670 } 668 }
671 669
@@ -706,7 +704,7 @@ void edma_free_channel(unsigned channel)
706 ctlr = EDMA_CTLR(channel); 704 ctlr = EDMA_CTLR(channel);
707 channel = EDMA_CHAN_SLOT(channel); 705 channel = EDMA_CHAN_SLOT(channel);
708 706
709 if (channel >= edma_info[ctlr]->num_channels) 707 if (channel >= edma_cc[ctlr]->num_channels)
710 return; 708 return;
711 709
712 setup_dma_interrupt(channel, NULL, NULL); 710 setup_dma_interrupt(channel, NULL, NULL);
@@ -714,7 +712,7 @@ void edma_free_channel(unsigned channel)
714 712
715 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), 713 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
716 &dummy_paramset, PARM_SIZE); 714 &dummy_paramset, PARM_SIZE);
717 clear_bit(channel, edma_info[ctlr]->edma_inuse); 715 clear_bit(channel, edma_cc[ctlr]->edma_inuse);
718} 716}
719EXPORT_SYMBOL(edma_free_channel); 717EXPORT_SYMBOL(edma_free_channel);
720 718
@@ -738,20 +736,19 @@ int edma_alloc_slot(unsigned ctlr, int slot)
738 slot = EDMA_CHAN_SLOT(slot); 736 slot = EDMA_CHAN_SLOT(slot);
739 737
740 if (slot < 0) { 738 if (slot < 0) {
741 slot = edma_info[ctlr]->num_channels; 739 slot = edma_cc[ctlr]->num_channels;
742 for (;;) { 740 for (;;) {
743 slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse, 741 slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
744 edma_info[ctlr]->num_slots, slot); 742 edma_cc[ctlr]->num_slots, slot);
745 if (slot == edma_info[ctlr]->num_slots) 743 if (slot == edma_cc[ctlr]->num_slots)
746 return -ENOMEM; 744 return -ENOMEM;
747 if (!test_and_set_bit(slot, 745 if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
748 edma_info[ctlr]->edma_inuse))
749 break; 746 break;
750 } 747 }
751 } else if (slot < edma_info[ctlr]->num_channels || 748 } else if (slot < edma_cc[ctlr]->num_channels ||
752 slot >= edma_info[ctlr]->num_slots) { 749 slot >= edma_cc[ctlr]->num_slots) {
753 return -EINVAL; 750 return -EINVAL;
754 } else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) { 751 } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
755 return -EBUSY; 752 return -EBUSY;
756 } 753 }
757 754
@@ -777,13 +774,13 @@ void edma_free_slot(unsigned slot)
777 ctlr = EDMA_CTLR(slot); 774 ctlr = EDMA_CTLR(slot);
778 slot = EDMA_CHAN_SLOT(slot); 775 slot = EDMA_CHAN_SLOT(slot);
779 776
780 if (slot < edma_info[ctlr]->num_channels || 777 if (slot < edma_cc[ctlr]->num_channels ||
781 slot >= edma_info[ctlr]->num_slots) 778 slot >= edma_cc[ctlr]->num_slots)
782 return; 779 return;
783 780
784 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), 781 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
785 &dummy_paramset, PARM_SIZE); 782 &dummy_paramset, PARM_SIZE);
786 clear_bit(slot, edma_info[ctlr]->edma_inuse); 783 clear_bit(slot, edma_cc[ctlr]->edma_inuse);
787} 784}
788EXPORT_SYMBOL(edma_free_slot); 785EXPORT_SYMBOL(edma_free_slot);
789 786
@@ -821,8 +818,8 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
821 * of slots 818 * of slots
822 */ 819 */
823 if ((id != EDMA_CONT_PARAMS_ANY) && 820 if ((id != EDMA_CONT_PARAMS_ANY) &&
824 (slot < edma_info[ctlr]->num_channels || 821 (slot < edma_cc[ctlr]->num_channels ||
825 slot >= edma_info[ctlr]->num_slots)) 822 slot >= edma_cc[ctlr]->num_slots))
826 return -EINVAL; 823 return -EINVAL;
827 824
828 /* 825 /*
@@ -831,13 +828,13 @@ int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
831 * channels 828 * channels
832 */ 829 */
833 if (count < 1 || count > 830 if (count < 1 || count >
834 (edma_info[ctlr]->num_slots - edma_info[ctlr]->num_channels)) 831 (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
835 return -EINVAL; 832 return -EINVAL;
836 833
837 switch (id) { 834 switch (id) {
838 case EDMA_CONT_PARAMS_ANY: 835 case EDMA_CONT_PARAMS_ANY:
839 return reserve_contiguous_slots(ctlr, id, count, 836 return reserve_contiguous_slots(ctlr, id, count,
840 edma_info[ctlr]->num_channels); 837 edma_cc[ctlr]->num_channels);
841 case EDMA_CONT_PARAMS_FIXED_EXACT: 838 case EDMA_CONT_PARAMS_FIXED_EXACT:
842 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: 839 case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
843 return reserve_contiguous_slots(ctlr, id, count, slot); 840 return reserve_contiguous_slots(ctlr, id, count, slot);
@@ -869,8 +866,8 @@ int edma_free_cont_slots(unsigned slot, int count)
869 ctlr = EDMA_CTLR(slot); 866 ctlr = EDMA_CTLR(slot);
870 slot = EDMA_CHAN_SLOT(slot); 867 slot = EDMA_CHAN_SLOT(slot);
871 868
872 if (slot < edma_info[ctlr]->num_channels || 869 if (slot < edma_cc[ctlr]->num_channels ||
873 slot >= edma_info[ctlr]->num_slots || 870 slot >= edma_cc[ctlr]->num_slots ||
874 count < 1) 871 count < 1)
875 return -EINVAL; 872 return -EINVAL;
876 873
@@ -880,7 +877,7 @@ int edma_free_cont_slots(unsigned slot, int count)
880 877
881 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free), 878 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
882 &dummy_paramset, PARM_SIZE); 879 &dummy_paramset, PARM_SIZE);
883 clear_bit(slot_to_free, edma_info[ctlr]->edma_inuse); 880 clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
884 } 881 }
885 882
886 return 0; 883 return 0;
@@ -910,7 +907,7 @@ void edma_set_src(unsigned slot, dma_addr_t src_port,
910 ctlr = EDMA_CTLR(slot); 907 ctlr = EDMA_CTLR(slot);
911 slot = EDMA_CHAN_SLOT(slot); 908 slot = EDMA_CHAN_SLOT(slot);
912 909
913 if (slot < edma_info[ctlr]->num_slots) { 910 if (slot < edma_cc[ctlr]->num_slots) {
914 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); 911 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
915 912
916 if (mode) { 913 if (mode) {
@@ -948,7 +945,7 @@ void edma_set_dest(unsigned slot, dma_addr_t dest_port,
948 ctlr = EDMA_CTLR(slot); 945 ctlr = EDMA_CTLR(slot);
949 slot = EDMA_CHAN_SLOT(slot); 946 slot = EDMA_CHAN_SLOT(slot);
950 947
951 if (slot < edma_info[ctlr]->num_slots) { 948 if (slot < edma_cc[ctlr]->num_slots) {
952 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); 949 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
953 950
954 if (mode) { 951 if (mode) {
@@ -1008,7 +1005,7 @@ void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
1008 ctlr = EDMA_CTLR(slot); 1005 ctlr = EDMA_CTLR(slot);
1009 slot = EDMA_CHAN_SLOT(slot); 1006 slot = EDMA_CHAN_SLOT(slot);
1010 1007
1011 if (slot < edma_info[ctlr]->num_slots) { 1008 if (slot < edma_cc[ctlr]->num_slots) {
1012 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, 1009 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1013 0xffff0000, src_bidx); 1010 0xffff0000, src_bidx);
1014 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, 1011 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
@@ -1034,7 +1031,7 @@ void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
1034 ctlr = EDMA_CTLR(slot); 1031 ctlr = EDMA_CTLR(slot);
1035 slot = EDMA_CHAN_SLOT(slot); 1032 slot = EDMA_CHAN_SLOT(slot);
1036 1033
1037 if (slot < edma_info[ctlr]->num_slots) { 1034 if (slot < edma_cc[ctlr]->num_slots) {
1038 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, 1035 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
1039 0x0000ffff, dest_bidx << 16); 1036 0x0000ffff, dest_bidx << 16);
1040 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, 1037 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
@@ -1081,7 +1078,7 @@ void edma_set_transfer_params(unsigned slot,
1081 ctlr = EDMA_CTLR(slot); 1078 ctlr = EDMA_CTLR(slot);
1082 slot = EDMA_CHAN_SLOT(slot); 1079 slot = EDMA_CHAN_SLOT(slot);
1083 1080
1084 if (slot < edma_info[ctlr]->num_slots) { 1081 if (slot < edma_cc[ctlr]->num_slots) {
1085 edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, 1082 edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
1086 0x0000ffff, bcnt_rld << 16); 1083 0x0000ffff, bcnt_rld << 16);
1087 if (sync_mode == ASYNC) 1084 if (sync_mode == ASYNC)
@@ -1111,9 +1108,9 @@ void edma_link(unsigned from, unsigned to)
1111 ctlr_to = EDMA_CTLR(to); 1108 ctlr_to = EDMA_CTLR(to);
1112 to = EDMA_CHAN_SLOT(to); 1109 to = EDMA_CHAN_SLOT(to);
1113 1110
1114 if (from >= edma_info[ctlr_from]->num_slots) 1111 if (from >= edma_cc[ctlr_from]->num_slots)
1115 return; 1112 return;
1116 if (to >= edma_info[ctlr_to]->num_slots) 1113 if (to >= edma_cc[ctlr_to]->num_slots)
1117 return; 1114 return;
1118 edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, 1115 edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
1119 PARM_OFFSET(to)); 1116 PARM_OFFSET(to));
@@ -1134,7 +1131,7 @@ void edma_unlink(unsigned from)
1134 ctlr = EDMA_CTLR(from); 1131 ctlr = EDMA_CTLR(from);
1135 from = EDMA_CHAN_SLOT(from); 1132 from = EDMA_CHAN_SLOT(from);
1136 1133
1137 if (from >= edma_info[ctlr]->num_slots) 1134 if (from >= edma_cc[ctlr]->num_slots)
1138 return; 1135 return;
1139 edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); 1136 edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
1140} 1137}
@@ -1161,7 +1158,7 @@ void edma_write_slot(unsigned slot, const struct edmacc_param *param)
1161 ctlr = EDMA_CTLR(slot); 1158 ctlr = EDMA_CTLR(slot);
1162 slot = EDMA_CHAN_SLOT(slot); 1159 slot = EDMA_CHAN_SLOT(slot);
1163 1160
1164 if (slot >= edma_info[ctlr]->num_slots) 1161 if (slot >= edma_cc[ctlr]->num_slots)
1165 return; 1162 return;
1166 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param, 1163 memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
1167 PARM_SIZE); 1164 PARM_SIZE);
@@ -1183,7 +1180,7 @@ void edma_read_slot(unsigned slot, struct edmacc_param *param)
1183 ctlr = EDMA_CTLR(slot); 1180 ctlr = EDMA_CTLR(slot);
1184 slot = EDMA_CHAN_SLOT(slot); 1181 slot = EDMA_CHAN_SLOT(slot);
1185 1182
1186 if (slot >= edma_info[ctlr]->num_slots) 1183 if (slot >= edma_cc[ctlr]->num_slots)
1187 return; 1184 return;
1188 memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot), 1185 memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
1189 PARM_SIZE); 1186 PARM_SIZE);
@@ -1208,7 +1205,7 @@ void edma_pause(unsigned channel)
1208 ctlr = EDMA_CTLR(channel); 1205 ctlr = EDMA_CTLR(channel);
1209 channel = EDMA_CHAN_SLOT(channel); 1206 channel = EDMA_CHAN_SLOT(channel);
1210 1207
1211 if (channel < edma_info[ctlr]->num_channels) { 1208 if (channel < edma_cc[ctlr]->num_channels) {
1212 unsigned int mask = (1 << (channel & 0x1f)); 1209 unsigned int mask = (1 << (channel & 0x1f));
1213 1210
1214 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); 1211 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
@@ -1229,7 +1226,7 @@ void edma_resume(unsigned channel)
1229 ctlr = EDMA_CTLR(channel); 1226 ctlr = EDMA_CTLR(channel);
1230 channel = EDMA_CHAN_SLOT(channel); 1227 channel = EDMA_CHAN_SLOT(channel);
1231 1228
1232 if (channel < edma_info[ctlr]->num_channels) { 1229 if (channel < edma_cc[ctlr]->num_channels) {
1233 unsigned int mask = (1 << (channel & 0x1f)); 1230 unsigned int mask = (1 << (channel & 0x1f));
1234 1231
1235 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); 1232 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
@@ -1255,12 +1252,12 @@ int edma_start(unsigned channel)
1255 ctlr = EDMA_CTLR(channel); 1252 ctlr = EDMA_CTLR(channel);
1256 channel = EDMA_CHAN_SLOT(channel); 1253 channel = EDMA_CHAN_SLOT(channel);
1257 1254
1258 if (channel < edma_info[ctlr]->num_channels) { 1255 if (channel < edma_cc[ctlr]->num_channels) {
1259 int j = channel >> 5; 1256 int j = channel >> 5;
1260 unsigned int mask = (1 << (channel & 0x1f)); 1257 unsigned int mask = (1 << (channel & 0x1f));
1261 1258
1262 /* EDMA channels without event association */ 1259 /* EDMA channels without event association */
1263 if (test_bit(channel, edma_info[ctlr]->edma_unused)) { 1260 if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
1264 pr_debug("EDMA: ESR%d %08x\n", j, 1261 pr_debug("EDMA: ESR%d %08x\n", j,
1265 edma_shadow0_read_array(ctlr, SH_ESR, j)); 1262 edma_shadow0_read_array(ctlr, SH_ESR, j));
1266 edma_shadow0_write_array(ctlr, SH_ESR, j, mask); 1263 edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
@@ -1301,7 +1298,7 @@ void edma_stop(unsigned channel)
1301 ctlr = EDMA_CTLR(channel); 1298 ctlr = EDMA_CTLR(channel);
1302 channel = EDMA_CHAN_SLOT(channel); 1299 channel = EDMA_CHAN_SLOT(channel);
1303 1300
1304 if (channel < edma_info[ctlr]->num_channels) { 1301 if (channel < edma_cc[ctlr]->num_channels) {
1305 int j = channel >> 5; 1302 int j = channel >> 5;
1306 unsigned int mask = (1 << (channel & 0x1f)); 1303 unsigned int mask = (1 << (channel & 0x1f));
1307 1304
@@ -1340,7 +1337,7 @@ void edma_clean_channel(unsigned channel)
1340 ctlr = EDMA_CTLR(channel); 1337 ctlr = EDMA_CTLR(channel);
1341 channel = EDMA_CHAN_SLOT(channel); 1338 channel = EDMA_CHAN_SLOT(channel);
1342 1339
1343 if (channel < edma_info[ctlr]->num_channels) { 1340 if (channel < edma_cc[ctlr]->num_channels) {
1344 int j = (channel >> 5); 1341 int j = (channel >> 5);
1345 unsigned int mask = 1 << (channel & 0x1f); 1342 unsigned int mask = 1 << (channel & 0x1f);
1346 1343
@@ -1368,7 +1365,7 @@ void edma_clear_event(unsigned channel)
1368 ctlr = EDMA_CTLR(channel); 1365 ctlr = EDMA_CTLR(channel);
1369 channel = EDMA_CHAN_SLOT(channel); 1366 channel = EDMA_CHAN_SLOT(channel);
1370 1367
1371 if (channel >= edma_info[ctlr]->num_channels) 1368 if (channel >= edma_cc[ctlr]->num_channels)
1372 return; 1369 return;
1373 if (channel < 32) 1370 if (channel < 32)
1374 edma_write(ctlr, EDMA_ECR, 1 << channel); 1371 edma_write(ctlr, EDMA_ECR, 1 << channel);
@@ -1423,38 +1420,37 @@ static int __init edma_probe(struct platform_device *pdev)
1423 goto fail1; 1420 goto fail1;
1424 } 1421 }
1425 1422
1426 edma_info[j] = kmalloc(sizeof(struct edma), GFP_KERNEL); 1423 edma_cc[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
1427 if (!edma_info[j]) { 1424 if (!edma_cc[j]) {
1428 status = -ENOMEM; 1425 status = -ENOMEM;
1429 goto fail1; 1426 goto fail1;
1430 } 1427 }
1431 memset(edma_info[j], 0, sizeof(struct edma)); 1428 memset(edma_cc[j], 0, sizeof(struct edma));
1432 1429
1433 edma_info[j]->num_channels = min_t(unsigned, info[j].n_channel, 1430 edma_cc[j]->num_channels = min_t(unsigned, info[j].n_channel,
1434 EDMA_MAX_DMACH); 1431 EDMA_MAX_DMACH);
1435 edma_info[j]->num_slots = min_t(unsigned, info[j].n_slot, 1432 edma_cc[j]->num_slots = min_t(unsigned, info[j].n_slot,
1436 EDMA_MAX_PARAMENTRY); 1433 EDMA_MAX_PARAMENTRY);
1437 edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc, 1434 edma_cc[j]->num_cc = min_t(unsigned, info[j].n_cc, EDMA_MAX_CC);
1438 EDMA_MAX_CC);
1439 1435
1440 edma_info[j]->default_queue = info[j].default_queue; 1436 edma_cc[j]->default_queue = info[j].default_queue;
1441 if (!edma_info[j]->default_queue) 1437 if (!edma_cc[j]->default_queue)
1442 edma_info[j]->default_queue = EVENTQ_1; 1438 edma_cc[j]->default_queue = EVENTQ_1;
1443 1439
1444 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", 1440 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
1445 edmacc_regs_base[j]); 1441 edmacc_regs_base[j]);
1446 1442
1447 for (i = 0; i < edma_info[j]->num_slots; i++) 1443 for (i = 0; i < edma_cc[j]->num_slots; i++)
1448 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), 1444 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1449 &dummy_paramset, PARM_SIZE); 1445 &dummy_paramset, PARM_SIZE);
1450 1446
1451 /* Mark all channels as unused */ 1447 /* Mark all channels as unused */
1452 memset(edma_info[j]->edma_unused, 0xff, 1448 memset(edma_cc[j]->edma_unused, 0xff,
1453 sizeof(edma_info[j]->edma_unused)); 1449 sizeof(edma_cc[j]->edma_unused));
1454 1450
1455 sprintf(irq_name, "edma%d", j); 1451 sprintf(irq_name, "edma%d", j);
1456 irq[j] = platform_get_irq_byname(pdev, irq_name); 1452 irq[j] = platform_get_irq_byname(pdev, irq_name);
1457 edma_info[j]->irq_res_start = irq[j]; 1453 edma_cc[j]->irq_res_start = irq[j];
1458 status = request_irq(irq[j], dma_irq_handler, 0, "edma", 1454 status = request_irq(irq[j], dma_irq_handler, 0, "edma",
1459 &pdev->dev); 1455 &pdev->dev);
1460 if (status < 0) { 1456 if (status < 0) {
@@ -1465,7 +1461,7 @@ static int __init edma_probe(struct platform_device *pdev)
1465 1461
1466 sprintf(irq_name, "edma%d_err", j); 1462 sprintf(irq_name, "edma%d_err", j);
1467 err_irq[j] = platform_get_irq_byname(pdev, irq_name); 1463 err_irq[j] = platform_get_irq_byname(pdev, irq_name);
1468 edma_info[j]->irq_res_end = err_irq[j]; 1464 edma_cc[j]->irq_res_end = err_irq[j];
1469 status = request_irq(err_irq[j], dma_ccerr_handler, 0, 1465 status = request_irq(err_irq[j], dma_ccerr_handler, 0,
1470 "edma_error", &pdev->dev); 1466 "edma_error", &pdev->dev);
1471 if (status < 0) { 1467 if (status < 0) {
@@ -1478,7 +1474,7 @@ static int __init edma_probe(struct platform_device *pdev)
1478 * specified. This way, long transfers on the low priority queue 1474 * specified. This way, long transfers on the low priority queue
1479 * started by the codec engine will not cause audio defects. 1475 * started by the codec engine will not cause audio defects.
1480 */ 1476 */
1481 for (i = 0; i < edma_info[j]->num_channels; i++) 1477 for (i = 0; i < edma_cc[j]->num_channels; i++)
1482 map_dmach_queue(j, i, EVENTQ_1); 1478 map_dmach_queue(j, i, EVENTQ_1);
1483 1479
1484 queue_tc_mapping = info[j].queue_tc_mapping; 1480 queue_tc_mapping = info[j].queue_tc_mapping;
@@ -1541,7 +1537,7 @@ fail1:
1541 release_mem_region(r[i]->start, len[i]); 1537 release_mem_region(r[i]->start, len[i]);
1542 if (edmacc_regs_base[i]) 1538 if (edmacc_regs_base[i])
1543 iounmap(edmacc_regs_base[i]); 1539 iounmap(edmacc_regs_base[i]);
1544 kfree(edma_info[i]); 1540 kfree(edma_cc[i]);
1545 } 1541 }
1546 return status; 1542 return status;
1547} 1543}