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authorLinus Walleij <linus.walleij@linaro.org>2011-08-22 03:39:28 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-08-22 04:12:55 -0400
commit8338d87fea2c001b4f5a07f9217df89956d1fddd (patch)
treeefc6a257dacf3dd87c90282fdaaa626939c3e47e /arch/arm/mach-davinci
parent386ab6400a4d2331f60695cb355dcc3790ccfbcc (diff)
ARM: 7038/1: mach-davinci: move GPIO driver to GPIO subsystem
As per example from the other ARM boards, push the DaVinci GPIO driver down to the GPIO subsystem so it can be consolidated. Cc: Sekhar Nori <nsekhar@ti.com> Cc: Kevin Hilman <khilman@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-davinci')
-rw-r--r--arch/arm/mach-davinci/Makefile2
-rw-r--r--arch/arm/mach-davinci/gpio.c458
2 files changed, 1 insertions, 459 deletions
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 0b87a1ca2bb3..8f3c8ee43ffa 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,7 +5,7 @@
5 5
6# Common objects 6# Common objects
7obj-y := time.o clock.o serial.o io.o psc.o \ 7obj-y := time.o clock.o serial.o io.o psc.o \
8 gpio.o dma.o usb.o common.o sram.o aemif.o 8 dma.o usb.o common.o sram.o aemif.o
9 9
10obj-$(CONFIG_DAVINCI_MUX) += mux.o 10obj-$(CONFIG_DAVINCI_MUX) += mux.o
11 11
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
deleted file mode 100644
index a8066e8edade..000000000000
--- a/arch/arm/mach-davinci/gpio.c
+++ /dev/null
@@ -1,458 +0,0 @@
1/*
2 * TI DaVinci GPIO Support
3 *
4 * Copyright (c) 2006-2007 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#include <linux/gpio.h>
13#include <linux/errno.h>
14#include <linux/kernel.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
18
19#include <asm/mach/irq.h>
20
21struct davinci_gpio_regs {
22 u32 dir;
23 u32 out_data;
24 u32 set_data;
25 u32 clr_data;
26 u32 in_data;
27 u32 set_rising;
28 u32 clr_rising;
29 u32 set_falling;
30 u32 clr_falling;
31 u32 intstat;
32};
33
34#define chip2controller(chip) \
35 container_of(chip, struct davinci_gpio_controller, chip)
36
37static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
38static void __iomem *gpio_base;
39
40static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
41{
42 void __iomem *ptr;
43
44 if (gpio < 32 * 1)
45 ptr = gpio_base + 0x10;
46 else if (gpio < 32 * 2)
47 ptr = gpio_base + 0x38;
48 else if (gpio < 32 * 3)
49 ptr = gpio_base + 0x60;
50 else if (gpio < 32 * 4)
51 ptr = gpio_base + 0x88;
52 else if (gpio < 32 * 5)
53 ptr = gpio_base + 0xb0;
54 else
55 ptr = NULL;
56 return ptr;
57}
58
59static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
60{
61 struct davinci_gpio_regs __iomem *g;
62
63 g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
64
65 return g;
66}
67
68static int __init davinci_gpio_irq_setup(void);
69
70/*--------------------------------------------------------------------------*/
71
72/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
73static inline int __davinci_direction(struct gpio_chip *chip,
74 unsigned offset, bool out, int value)
75{
76 struct davinci_gpio_controller *d = chip2controller(chip);
77 struct davinci_gpio_regs __iomem *g = d->regs;
78 unsigned long flags;
79 u32 temp;
80 u32 mask = 1 << offset;
81
82 spin_lock_irqsave(&d->lock, flags);
83 temp = __raw_readl(&g->dir);
84 if (out) {
85 temp &= ~mask;
86 __raw_writel(mask, value ? &g->set_data : &g->clr_data);
87 } else {
88 temp |= mask;
89 }
90 __raw_writel(temp, &g->dir);
91 spin_unlock_irqrestore(&d->lock, flags);
92
93 return 0;
94}
95
96static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
97{
98 return __davinci_direction(chip, offset, false, 0);
99}
100
101static int
102davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
103{
104 return __davinci_direction(chip, offset, true, value);
105}
106
107/*
108 * Read the pin's value (works even if it's set up as output);
109 * returns zero/nonzero.
110 *
111 * Note that changes are synched to the GPIO clock, so reading values back
112 * right after you've set them may give old values.
113 */
114static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
115{
116 struct davinci_gpio_controller *d = chip2controller(chip);
117 struct davinci_gpio_regs __iomem *g = d->regs;
118
119 return (1 << offset) & __raw_readl(&g->in_data);
120}
121
122/*
123 * Assuming the pin is muxed as a gpio output, set its output value.
124 */
125static void
126davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
127{
128 struct davinci_gpio_controller *d = chip2controller(chip);
129 struct davinci_gpio_regs __iomem *g = d->regs;
130
131 __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
132}
133
134static int __init davinci_gpio_setup(void)
135{
136 int i, base;
137 unsigned ngpio;
138 struct davinci_soc_info *soc_info = &davinci_soc_info;
139 struct davinci_gpio_regs *regs;
140
141 if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
142 return 0;
143
144 /*
145 * The gpio banks conceptually expose a segmented bitmap,
146 * and "ngpio" is one more than the largest zero-based
147 * bit index that's valid.
148 */
149 ngpio = soc_info->gpio_num;
150 if (ngpio == 0) {
151 pr_err("GPIO setup: how many GPIOs?\n");
152 return -EINVAL;
153 }
154
155 if (WARN_ON(DAVINCI_N_GPIO < ngpio))
156 ngpio = DAVINCI_N_GPIO;
157
158 gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
159 if (WARN_ON(!gpio_base))
160 return -ENOMEM;
161
162 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
163 chips[i].chip.label = "DaVinci";
164
165 chips[i].chip.direction_input = davinci_direction_in;
166 chips[i].chip.get = davinci_gpio_get;
167 chips[i].chip.direction_output = davinci_direction_out;
168 chips[i].chip.set = davinci_gpio_set;
169
170 chips[i].chip.base = base;
171 chips[i].chip.ngpio = ngpio - base;
172 if (chips[i].chip.ngpio > 32)
173 chips[i].chip.ngpio = 32;
174
175 spin_lock_init(&chips[i].lock);
176
177 regs = gpio2regs(base);
178 chips[i].regs = regs;
179 chips[i].set_data = &regs->set_data;
180 chips[i].clr_data = &regs->clr_data;
181 chips[i].in_data = &regs->in_data;
182
183 gpiochip_add(&chips[i].chip);
184 }
185
186 soc_info->gpio_ctlrs = chips;
187 soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
188
189 davinci_gpio_irq_setup();
190 return 0;
191}
192pure_initcall(davinci_gpio_setup);
193
194/*--------------------------------------------------------------------------*/
195/*
196 * We expect irqs will normally be set up as input pins, but they can also be
197 * used as output pins ... which is convenient for testing.
198 *
199 * NOTE: The first few GPIOs also have direct INTC hookups in addition
200 * to their GPIOBNK0 irq, with a bit less overhead.
201 *
202 * All those INTC hookups (direct, plus several IRQ banks) can also
203 * serve as EDMA event triggers.
204 */
205
206static void gpio_irq_disable(struct irq_data *d)
207{
208 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
209 u32 mask = (u32) irq_data_get_irq_handler_data(d);
210
211 __raw_writel(mask, &g->clr_falling);
212 __raw_writel(mask, &g->clr_rising);
213}
214
215static void gpio_irq_enable(struct irq_data *d)
216{
217 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
218 u32 mask = (u32) irq_data_get_irq_handler_data(d);
219 unsigned status = irqd_get_trigger_type(d);
220
221 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
222 if (!status)
223 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
224
225 if (status & IRQ_TYPE_EDGE_FALLING)
226 __raw_writel(mask, &g->set_falling);
227 if (status & IRQ_TYPE_EDGE_RISING)
228 __raw_writel(mask, &g->set_rising);
229}
230
231static int gpio_irq_type(struct irq_data *d, unsigned trigger)
232{
233 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
234 u32 mask = (u32) irq_data_get_irq_handler_data(d);
235
236 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
237 return -EINVAL;
238
239 return 0;
240}
241
242static struct irq_chip gpio_irqchip = {
243 .name = "GPIO",
244 .irq_enable = gpio_irq_enable,
245 .irq_disable = gpio_irq_disable,
246 .irq_set_type = gpio_irq_type,
247 .flags = IRQCHIP_SET_TYPE_MASKED,
248};
249
250static void
251gpio_irq_handler(unsigned irq, struct irq_desc *desc)
252{
253 struct davinci_gpio_regs __iomem *g;
254 u32 mask = 0xffff;
255 struct davinci_gpio_controller *d;
256
257 d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
258 g = (struct davinci_gpio_regs __iomem *)d->regs;
259
260 /* we only care about one bank */
261 if (irq & 1)
262 mask <<= 16;
263
264 /* temporarily mask (level sensitive) parent IRQ */
265 desc->irq_data.chip->irq_mask(&desc->irq_data);
266 desc->irq_data.chip->irq_ack(&desc->irq_data);
267 while (1) {
268 u32 status;
269 int n;
270 int res;
271
272 /* ack any irqs */
273 status = __raw_readl(&g->intstat) & mask;
274 if (!status)
275 break;
276 __raw_writel(status, &g->intstat);
277
278 /* now demux them to the right lowlevel handler */
279 n = d->irq_base;
280 if (irq & 1) {
281 n += 16;
282 status >>= 16;
283 }
284
285 while (status) {
286 res = ffs(status);
287 n += res;
288 generic_handle_irq(n - 1);
289 status >>= res;
290 }
291 }
292 desc->irq_data.chip->irq_unmask(&desc->irq_data);
293 /* now it may re-trigger */
294}
295
296static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
297{
298 struct davinci_gpio_controller *d = chip2controller(chip);
299
300 if (d->irq_base >= 0)
301 return d->irq_base + offset;
302 else
303 return -ENODEV;
304}
305
306static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
307{
308 struct davinci_soc_info *soc_info = &davinci_soc_info;
309
310 /* NOTE: we assume for now that only irqs in the first gpio_chip
311 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
312 */
313 if (offset < soc_info->gpio_unbanked)
314 return soc_info->gpio_irq + offset;
315 else
316 return -ENODEV;
317}
318
319static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
320{
321 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
322 u32 mask = (u32) irq_data_get_irq_handler_data(d);
323
324 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
325 return -EINVAL;
326
327 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
328 ? &g->set_falling : &g->clr_falling);
329 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
330 ? &g->set_rising : &g->clr_rising);
331
332 return 0;
333}
334
335/*
336 * NOTE: for suspend/resume, probably best to make a platform_device with
337 * suspend_late/resume_resume calls hooking into results of the set_wake()
338 * calls ... so if no gpios are wakeup events the clock can be disabled,
339 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
340 * (dm6446) can be set appropriately for GPIOV33 pins.
341 */
342
343static int __init davinci_gpio_irq_setup(void)
344{
345 unsigned gpio, irq, bank;
346 struct clk *clk;
347 u32 binten = 0;
348 unsigned ngpio, bank_irq;
349 struct davinci_soc_info *soc_info = &davinci_soc_info;
350 struct davinci_gpio_regs __iomem *g;
351
352 ngpio = soc_info->gpio_num;
353
354 bank_irq = soc_info->gpio_irq;
355 if (bank_irq == 0) {
356 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
357 return -EINVAL;
358 }
359
360 clk = clk_get(NULL, "gpio");
361 if (IS_ERR(clk)) {
362 printk(KERN_ERR "Error %ld getting gpio clock?\n",
363 PTR_ERR(clk));
364 return PTR_ERR(clk);
365 }
366 clk_enable(clk);
367
368 /* Arrange gpio_to_irq() support, handling either direct IRQs or
369 * banked IRQs. Having GPIOs in the first GPIO bank use direct
370 * IRQs, while the others use banked IRQs, would need some setup
371 * tweaks to recognize hardware which can do that.
372 */
373 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
374 chips[bank].chip.to_irq = gpio_to_irq_banked;
375 chips[bank].irq_base = soc_info->gpio_unbanked
376 ? -EINVAL
377 : (soc_info->intc_irq_num + gpio);
378 }
379
380 /*
381 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
382 * controller only handling trigger modes. We currently assume no
383 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
384 */
385 if (soc_info->gpio_unbanked) {
386 static struct irq_chip gpio_irqchip_unbanked;
387
388 /* pass "bank 0" GPIO IRQs to AINTC */
389 chips[0].chip.to_irq = gpio_to_irq_unbanked;
390 binten = BIT(0);
391
392 /* AINTC handles mask/unmask; GPIO handles triggering */
393 irq = bank_irq;
394 gpio_irqchip_unbanked = *irq_get_chip(irq);
395 gpio_irqchip_unbanked.name = "GPIO-AINTC";
396 gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
397
398 /* default trigger: both edges */
399 g = gpio2regs(0);
400 __raw_writel(~0, &g->set_falling);
401 __raw_writel(~0, &g->set_rising);
402
403 /* set the direct IRQs up to use that irqchip */
404 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
405 irq_set_chip(irq, &gpio_irqchip_unbanked);
406 irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
407 irq_set_chip_data(irq, (__force void *)g);
408 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
409 }
410
411 goto done;
412 }
413
414 /*
415 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
416 * then chain through our own handler.
417 */
418 for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
419 gpio < ngpio;
420 bank++, bank_irq++) {
421 unsigned i;
422
423 /* disabled by default, enabled only as needed */
424 g = gpio2regs(gpio);
425 __raw_writel(~0, &g->clr_falling);
426 __raw_writel(~0, &g->clr_rising);
427
428 /* set up all irqs in this bank */
429 irq_set_chained_handler(bank_irq, gpio_irq_handler);
430
431 /*
432 * Each chip handles 32 gpios, and each irq bank consists of 16
433 * gpio irqs. Pass the irq bank's corresponding controller to
434 * the chained irq handler.
435 */
436 irq_set_handler_data(bank_irq, &chips[gpio / 32]);
437
438 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
439 irq_set_chip(irq, &gpio_irqchip);
440 irq_set_chip_data(irq, (__force void *)g);
441 irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
442 irq_set_handler(irq, handle_simple_irq);
443 set_irq_flags(irq, IRQF_VALID);
444 }
445
446 binten |= BIT(bank);
447 }
448
449done:
450 /* BINTEN -- per-bank interrupt enable. genirq would also let these
451 * bits be set/cleared dynamically.
452 */
453 __raw_writel(binten, gpio_base + 0x08);
454
455 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
456
457 return 0;
458}
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