diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-07-25 15:38:42 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-07-25 15:38:42 -0400 |
commit | ae4c42e4e4d76d003f8ca551fe1aef93ff9a4b21 (patch) | |
tree | 2bff2e4f4456077e7d7c589c8c28824f12dfa21c /arch/arm/mach-davinci | |
parent | dd58ecba48edf14be1a5f70120fcd3002277a74a (diff) | |
parent | ab2a0e0d135490729e384c1826d118f92e88cae8 (diff) |
Merge branch 'next/cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc
* 'next/cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (133 commits)
ARM: EXYNOS4: Change devname for FIMD clkdev
ARM: S3C64XX: Cleanup mach/regs-fb.h from mach-s3c64xx
ARM: S5PV210: Cleanup mach/regs-fb.h from mach-s5pv210
ARM: S5PC100: Cleanup mach/regs-fb.h from mach-s5pc100
ARM: S3C24XX: Use generic s3c_set_platdata for devices
ARM: S3C64XX: Use generic s3c_set_platdata for OneNAND
ARM: SAMSUNG: Use generic s3c_set_platdata for NAND
ARM: SAMSUNG: Use generic s3c_set_platdata for USB OHCI
ARM: SAMSUNG: Use generic s3c_set_platdata for HWMON
ARM: SAMSUNG: Use generic s3c_set_platdata for FB
ARM: SAMSUNG: Use generic s3c_set_platdata for TS
ARM: S3C64XX: Add PWM backlight support on SMDK6410
ARM: S5P64X0: Add PWM backlight support on SMDK6450
ARM: S5P64X0: Add PWM backlight support on SMDK6440
ARM: S5PC100: Add PWM backlight support on SMDKC100
ARM: S5PV210: Add PWM backlight support on SMDKV210
ARM: EXYNOS4: Add PWM backlight support on SMDKC210
ARM: EXYNOS4: Add PWM backlight support on SMDKV310
ARM: SAMSUNG: Create a common infrastructure for PWM backlight support
clocksource: convert 32-bit down counting clocksource on S5PV210/S5P64X0
...
Fix up trivial conflict in arch/arm/mach-imx/mach-scb9328.c
Diffstat (limited to 'arch/arm/mach-davinci')
-rw-r--r-- | arch/arm/mach-davinci/board-dm646x-evm.c | 17 | ||||
-rw-r--r-- | arch/arm/mach-davinci/clock.c | 38 | ||||
-rw-r--r-- | arch/arm/mach-davinci/clock.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-davinci/dm646x.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/dm646x.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-davinci/include/mach/psc.h | 148 |
6 files changed, 123 insertions, 88 deletions
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c index 6d03643b9bd1..993a3146fd35 100644 --- a/arch/arm/mach-davinci/board-dm646x-evm.c +++ b/arch/arm/mach-davinci/board-dm646x-evm.c | |||
@@ -719,9 +719,15 @@ static void __init cdce_clk_init(void) | |||
719 | } | 719 | } |
720 | } | 720 | } |
721 | 721 | ||
722 | #define DM6467T_EVM_REF_FREQ 33000000 | ||
723 | |||
722 | static void __init davinci_map_io(void) | 724 | static void __init davinci_map_io(void) |
723 | { | 725 | { |
724 | dm646x_init(); | 726 | dm646x_init(); |
727 | |||
728 | if (machine_is_davinci_dm6467tevm()) | ||
729 | davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ); | ||
730 | |||
725 | cdce_clk_init(); | 731 | cdce_clk_init(); |
726 | } | 732 | } |
727 | 733 | ||
@@ -785,17 +791,6 @@ static __init void evm_init(void) | |||
785 | soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID; | 791 | soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID; |
786 | } | 792 | } |
787 | 793 | ||
788 | #define DM646X_EVM_REF_FREQ 27000000 | ||
789 | #define DM6467T_EVM_REF_FREQ 33000000 | ||
790 | |||
791 | void __init dm646x_board_setup_refclk(struct clk *clk) | ||
792 | { | ||
793 | if (machine_is_davinci_dm6467tevm()) | ||
794 | clk->rate = DM6467T_EVM_REF_FREQ; | ||
795 | else | ||
796 | clk->rate = DM646X_EVM_REF_FREQ; | ||
797 | } | ||
798 | |||
799 | MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") | 794 | MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") |
800 | .boot_params = (0x80000100), | 795 | .boot_params = (0x80000100), |
801 | .map_io = davinci_map_io, | 796 | .map_io = davinci_map_io, |
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c index e4e3af179f02..ae653194b645 100644 --- a/arch/arm/mach-davinci/clock.c +++ b/arch/arm/mach-davinci/clock.c | |||
@@ -368,6 +368,12 @@ static unsigned long clk_leafclk_recalc(struct clk *clk) | |||
368 | return clk->parent->rate; | 368 | return clk->parent->rate; |
369 | } | 369 | } |
370 | 370 | ||
371 | int davinci_simple_set_rate(struct clk *clk, unsigned long rate) | ||
372 | { | ||
373 | clk->rate = rate; | ||
374 | return 0; | ||
375 | } | ||
376 | |||
371 | static unsigned long clk_pllclk_recalc(struct clk *clk) | 377 | static unsigned long clk_pllclk_recalc(struct clk *clk) |
372 | { | 378 | { |
373 | u32 ctrl, mult = 1, prediv = 1, postdiv = 1; | 379 | u32 ctrl, mult = 1, prediv = 1, postdiv = 1; |
@@ -506,6 +512,38 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, | |||
506 | } | 512 | } |
507 | EXPORT_SYMBOL(davinci_set_pllrate); | 513 | EXPORT_SYMBOL(davinci_set_pllrate); |
508 | 514 | ||
515 | /** | ||
516 | * davinci_set_refclk_rate() - Set the reference clock rate | ||
517 | * @rate: The new rate. | ||
518 | * | ||
519 | * Sets the reference clock rate to a given value. This will most likely | ||
520 | * result in the entire clock tree getting updated. | ||
521 | * | ||
522 | * This is used to support boards which use a reference clock different | ||
523 | * than that used by default in <soc>.c file. The reference clock rate | ||
524 | * should be updated early in the boot process; ideally soon after the | ||
525 | * clock tree has been initialized once with the default reference clock | ||
526 | * rate (davinci_common_init()). | ||
527 | * | ||
528 | * Returns 0 on success, error otherwise. | ||
529 | */ | ||
530 | int davinci_set_refclk_rate(unsigned long rate) | ||
531 | { | ||
532 | struct clk *refclk; | ||
533 | |||
534 | refclk = clk_get(NULL, "ref"); | ||
535 | if (IS_ERR(refclk)) { | ||
536 | pr_err("%s: failed to get reference clock.\n", __func__); | ||
537 | return PTR_ERR(refclk); | ||
538 | } | ||
539 | |||
540 | clk_set_rate(refclk, rate); | ||
541 | |||
542 | clk_put(refclk); | ||
543 | |||
544 | return 0; | ||
545 | } | ||
546 | |||
509 | int __init davinci_clk_init(struct clk_lookup *clocks) | 547 | int __init davinci_clk_init(struct clk_lookup *clocks) |
510 | { | 548 | { |
511 | struct clk_lookup *c; | 549 | struct clk_lookup *c; |
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 0dd22031ec62..50b2482e0ba2 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h | |||
@@ -123,6 +123,8 @@ int davinci_clk_init(struct clk_lookup *clocks); | |||
123 | int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, | 123 | int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, |
124 | unsigned int mult, unsigned int postdiv); | 124 | unsigned int mult, unsigned int postdiv); |
125 | int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); | 125 | int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); |
126 | int davinci_set_refclk_rate(unsigned long rate); | ||
127 | int davinci_simple_set_rate(struct clk *clk, unsigned long rate); | ||
126 | 128 | ||
127 | extern struct platform_device davinci_wdt_device; | 129 | extern struct platform_device davinci_wdt_device; |
128 | extern void davinci_watchdog_reset(struct platform_device *); | 130 | extern void davinci_watchdog_reset(struct platform_device *); |
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index e00d61e2efbe..1802e711a2b8 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c | |||
@@ -43,6 +43,7 @@ | |||
43 | /* | 43 | /* |
44 | * Device specific clocks | 44 | * Device specific clocks |
45 | */ | 45 | */ |
46 | #define DM646X_REF_FREQ 27000000 | ||
46 | #define DM646X_AUX_FREQ 24000000 | 47 | #define DM646X_AUX_FREQ 24000000 |
47 | 48 | ||
48 | static struct pll_data pll1_data = { | 49 | static struct pll_data pll1_data = { |
@@ -57,6 +58,8 @@ static struct pll_data pll2_data = { | |||
57 | 58 | ||
58 | static struct clk ref_clk = { | 59 | static struct clk ref_clk = { |
59 | .name = "ref_clk", | 60 | .name = "ref_clk", |
61 | .rate = DM646X_REF_FREQ, | ||
62 | .set_rate = davinci_simple_set_rate, | ||
60 | }; | 63 | }; |
61 | 64 | ||
62 | static struct clk aux_clkin = { | 65 | static struct clk aux_clkin = { |
@@ -902,7 +905,6 @@ int __init dm646x_init_edma(struct edma_rsv_info *rsv) | |||
902 | 905 | ||
903 | void __init dm646x_init(void) | 906 | void __init dm646x_init(void) |
904 | { | 907 | { |
905 | dm646x_board_setup_refclk(&ref_clk); | ||
906 | davinci_common_init(&davinci_soc_info_dm646x); | 908 | davinci_common_init(&davinci_soc_info_dm646x); |
907 | } | 909 | } |
908 | 910 | ||
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h index 7a27f3f13913..2a00fe5ac253 100644 --- a/arch/arm/mach-davinci/include/mach/dm646x.h +++ b/arch/arm/mach-davinci/include/mach/dm646x.h | |||
@@ -15,7 +15,6 @@ | |||
15 | #include <mach/asp.h> | 15 | #include <mach/asp.h> |
16 | #include <linux/i2c.h> | 16 | #include <linux/i2c.h> |
17 | #include <linux/videodev2.h> | 17 | #include <linux/videodev2.h> |
18 | #include <linux/clk.h> | ||
19 | #include <linux/davinci_emac.h> | 18 | #include <linux/davinci_emac.h> |
20 | 19 | ||
21 | #define DM646X_EMAC_BASE (0x01C80000) | 20 | #define DM646X_EMAC_BASE (0x01C80000) |
@@ -31,7 +30,6 @@ | |||
31 | void __init dm646x_init(void); | 30 | void __init dm646x_init(void); |
32 | void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); | 31 | void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); |
33 | void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); | 32 | void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); |
34 | void __init dm646x_board_setup_refclk(struct clk *clk); | ||
35 | int __init dm646x_init_edma(struct edma_rsv_info *rsv); | 33 | int __init dm646x_init_edma(struct edma_rsv_info *rsv); |
36 | 34 | ||
37 | void dm646x_video_init(void); | 35 | void dm646x_video_init(void); |
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h index a47e6f29206e..1110fdd77ba4 100644 --- a/arch/arm/mach-davinci/include/mach/psc.h +++ b/arch/arm/mach-davinci/include/mach/psc.h | |||
@@ -30,47 +30,47 @@ | |||
30 | #define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000 | 30 | #define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000 |
31 | 31 | ||
32 | /* Power and Sleep Controller (PSC) Domains */ | 32 | /* Power and Sleep Controller (PSC) Domains */ |
33 | #define DAVINCI_GPSC_ARMDOMAIN 0 | 33 | #define DAVINCI_GPSC_ARMDOMAIN 0 |
34 | #define DAVINCI_GPSC_DSPDOMAIN 1 | 34 | #define DAVINCI_GPSC_DSPDOMAIN 1 |
35 | 35 | ||
36 | #define DAVINCI_LPSC_VPSSMSTR 0 | 36 | #define DAVINCI_LPSC_VPSSMSTR 0 |
37 | #define DAVINCI_LPSC_VPSSSLV 1 | 37 | #define DAVINCI_LPSC_VPSSSLV 1 |
38 | #define DAVINCI_LPSC_TPCC 2 | 38 | #define DAVINCI_LPSC_TPCC 2 |
39 | #define DAVINCI_LPSC_TPTC0 3 | 39 | #define DAVINCI_LPSC_TPTC0 3 |
40 | #define DAVINCI_LPSC_TPTC1 4 | 40 | #define DAVINCI_LPSC_TPTC1 4 |
41 | #define DAVINCI_LPSC_EMAC 5 | 41 | #define DAVINCI_LPSC_EMAC 5 |
42 | #define DAVINCI_LPSC_EMAC_WRAPPER 6 | 42 | #define DAVINCI_LPSC_EMAC_WRAPPER 6 |
43 | #define DAVINCI_LPSC_USB 9 | 43 | #define DAVINCI_LPSC_USB 9 |
44 | #define DAVINCI_LPSC_ATA 10 | 44 | #define DAVINCI_LPSC_ATA 10 |
45 | #define DAVINCI_LPSC_VLYNQ 11 | 45 | #define DAVINCI_LPSC_VLYNQ 11 |
46 | #define DAVINCI_LPSC_UHPI 12 | 46 | #define DAVINCI_LPSC_UHPI 12 |
47 | #define DAVINCI_LPSC_DDR_EMIF 13 | 47 | #define DAVINCI_LPSC_DDR_EMIF 13 |
48 | #define DAVINCI_LPSC_AEMIF 14 | 48 | #define DAVINCI_LPSC_AEMIF 14 |
49 | #define DAVINCI_LPSC_MMC_SD 15 | 49 | #define DAVINCI_LPSC_MMC_SD 15 |
50 | #define DAVINCI_LPSC_McBSP 17 | 50 | #define DAVINCI_LPSC_McBSP 17 |
51 | #define DAVINCI_LPSC_I2C 18 | 51 | #define DAVINCI_LPSC_I2C 18 |
52 | #define DAVINCI_LPSC_UART0 19 | 52 | #define DAVINCI_LPSC_UART0 19 |
53 | #define DAVINCI_LPSC_UART1 20 | 53 | #define DAVINCI_LPSC_UART1 20 |
54 | #define DAVINCI_LPSC_UART2 21 | 54 | #define DAVINCI_LPSC_UART2 21 |
55 | #define DAVINCI_LPSC_SPI 22 | 55 | #define DAVINCI_LPSC_SPI 22 |
56 | #define DAVINCI_LPSC_PWM0 23 | 56 | #define DAVINCI_LPSC_PWM0 23 |
57 | #define DAVINCI_LPSC_PWM1 24 | 57 | #define DAVINCI_LPSC_PWM1 24 |
58 | #define DAVINCI_LPSC_PWM2 25 | 58 | #define DAVINCI_LPSC_PWM2 25 |
59 | #define DAVINCI_LPSC_GPIO 26 | 59 | #define DAVINCI_LPSC_GPIO 26 |
60 | #define DAVINCI_LPSC_TIMER0 27 | 60 | #define DAVINCI_LPSC_TIMER0 27 |
61 | #define DAVINCI_LPSC_TIMER1 28 | 61 | #define DAVINCI_LPSC_TIMER1 28 |
62 | #define DAVINCI_LPSC_TIMER2 29 | 62 | #define DAVINCI_LPSC_TIMER2 29 |
63 | #define DAVINCI_LPSC_SYSTEM_SUBSYS 30 | 63 | #define DAVINCI_LPSC_SYSTEM_SUBSYS 30 |
64 | #define DAVINCI_LPSC_ARM 31 | 64 | #define DAVINCI_LPSC_ARM 31 |
65 | #define DAVINCI_LPSC_SCR2 32 | 65 | #define DAVINCI_LPSC_SCR2 32 |
66 | #define DAVINCI_LPSC_SCR3 33 | 66 | #define DAVINCI_LPSC_SCR3 33 |
67 | #define DAVINCI_LPSC_SCR4 34 | 67 | #define DAVINCI_LPSC_SCR4 34 |
68 | #define DAVINCI_LPSC_CROSSBAR 35 | 68 | #define DAVINCI_LPSC_CROSSBAR 35 |
69 | #define DAVINCI_LPSC_CFG27 36 | 69 | #define DAVINCI_LPSC_CFG27 36 |
70 | #define DAVINCI_LPSC_CFG3 37 | 70 | #define DAVINCI_LPSC_CFG3 37 |
71 | #define DAVINCI_LPSC_CFG5 38 | 71 | #define DAVINCI_LPSC_CFG5 38 |
72 | #define DAVINCI_LPSC_GEM 39 | 72 | #define DAVINCI_LPSC_GEM 39 |
73 | #define DAVINCI_LPSC_IMCOP 40 | 73 | #define DAVINCI_LPSC_IMCOP 40 |
74 | 74 | ||
75 | #define DM355_LPSC_TIMER3 5 | 75 | #define DM355_LPSC_TIMER3 5 |
76 | #define DM355_LPSC_SPI1 6 | 76 | #define DM355_LPSC_SPI1 6 |
@@ -102,39 +102,39 @@ | |||
102 | /* | 102 | /* |
103 | * LPSC Assignments | 103 | * LPSC Assignments |
104 | */ | 104 | */ |
105 | #define DM646X_LPSC_ARM 0 | 105 | #define DM646X_LPSC_ARM 0 |
106 | #define DM646X_LPSC_C64X_CPU 1 | 106 | #define DM646X_LPSC_C64X_CPU 1 |
107 | #define DM646X_LPSC_HDVICP0 2 | 107 | #define DM646X_LPSC_HDVICP0 2 |
108 | #define DM646X_LPSC_HDVICP1 3 | 108 | #define DM646X_LPSC_HDVICP1 3 |
109 | #define DM646X_LPSC_TPCC 4 | 109 | #define DM646X_LPSC_TPCC 4 |
110 | #define DM646X_LPSC_TPTC0 5 | 110 | #define DM646X_LPSC_TPTC0 5 |
111 | #define DM646X_LPSC_TPTC1 6 | 111 | #define DM646X_LPSC_TPTC1 6 |
112 | #define DM646X_LPSC_TPTC2 7 | 112 | #define DM646X_LPSC_TPTC2 7 |
113 | #define DM646X_LPSC_TPTC3 8 | 113 | #define DM646X_LPSC_TPTC3 8 |
114 | #define DM646X_LPSC_PCI 13 | 114 | #define DM646X_LPSC_PCI 13 |
115 | #define DM646X_LPSC_EMAC 14 | 115 | #define DM646X_LPSC_EMAC 14 |
116 | #define DM646X_LPSC_VDCE 15 | 116 | #define DM646X_LPSC_VDCE 15 |
117 | #define DM646X_LPSC_VPSSMSTR 16 | 117 | #define DM646X_LPSC_VPSSMSTR 16 |
118 | #define DM646X_LPSC_VPSSSLV 17 | 118 | #define DM646X_LPSC_VPSSSLV 17 |
119 | #define DM646X_LPSC_TSIF0 18 | 119 | #define DM646X_LPSC_TSIF0 18 |
120 | #define DM646X_LPSC_TSIF1 19 | 120 | #define DM646X_LPSC_TSIF1 19 |
121 | #define DM646X_LPSC_DDR_EMIF 20 | 121 | #define DM646X_LPSC_DDR_EMIF 20 |
122 | #define DM646X_LPSC_AEMIF 21 | 122 | #define DM646X_LPSC_AEMIF 21 |
123 | #define DM646X_LPSC_McASP0 22 | 123 | #define DM646X_LPSC_McASP0 22 |
124 | #define DM646X_LPSC_McASP1 23 | 124 | #define DM646X_LPSC_McASP1 23 |
125 | #define DM646X_LPSC_CRGEN0 24 | 125 | #define DM646X_LPSC_CRGEN0 24 |
126 | #define DM646X_LPSC_CRGEN1 25 | 126 | #define DM646X_LPSC_CRGEN1 25 |
127 | #define DM646X_LPSC_UART0 26 | 127 | #define DM646X_LPSC_UART0 26 |
128 | #define DM646X_LPSC_UART1 27 | 128 | #define DM646X_LPSC_UART1 27 |
129 | #define DM646X_LPSC_UART2 28 | 129 | #define DM646X_LPSC_UART2 28 |
130 | #define DM646X_LPSC_PWM0 29 | 130 | #define DM646X_LPSC_PWM0 29 |
131 | #define DM646X_LPSC_PWM1 30 | 131 | #define DM646X_LPSC_PWM1 30 |
132 | #define DM646X_LPSC_I2C 31 | 132 | #define DM646X_LPSC_I2C 31 |
133 | #define DM646X_LPSC_SPI 32 | 133 | #define DM646X_LPSC_SPI 32 |
134 | #define DM646X_LPSC_GPIO 33 | 134 | #define DM646X_LPSC_GPIO 33 |
135 | #define DM646X_LPSC_TIMER0 34 | 135 | #define DM646X_LPSC_TIMER0 34 |
136 | #define DM646X_LPSC_TIMER1 35 | 136 | #define DM646X_LPSC_TIMER1 35 |
137 | #define DM646X_LPSC_ARM_INTC 45 | 137 | #define DM646X_LPSC_ARM_INTC 45 |
138 | 138 | ||
139 | /* PSC0 defines */ | 139 | /* PSC0 defines */ |
140 | #define DA8XX_LPSC0_TPCC 0 | 140 | #define DA8XX_LPSC0_TPCC 0 |
@@ -243,7 +243,7 @@ | |||
243 | #define PSC_STATE_DISABLE 2 | 243 | #define PSC_STATE_DISABLE 2 |
244 | #define PSC_STATE_ENABLE 3 | 244 | #define PSC_STATE_ENABLE 3 |
245 | 245 | ||
246 | #define MDSTAT_STATE_MASK 0x1f | 246 | #define MDSTAT_STATE_MASK 0x1f |
247 | 247 | ||
248 | #ifndef __ASSEMBLER__ | 248 | #ifndef __ASSEMBLER__ |
249 | 249 | ||