Merge branch 'next/cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc

* 'next/cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc: (133 commits)
  ARM: EXYNOS4: Change devname for FIMD clkdev
  ARM: S3C64XX: Cleanup mach/regs-fb.h from mach-s3c64xx
  ARM: S5PV210: Cleanup mach/regs-fb.h from mach-s5pv210
  ARM: S5PC100: Cleanup mach/regs-fb.h from mach-s5pc100
  ARM: S3C24XX: Use generic s3c_set_platdata for devices
  ARM: S3C64XX: Use generic s3c_set_platdata for OneNAND
  ARM: SAMSUNG: Use generic s3c_set_platdata for NAND
  ARM: SAMSUNG: Use generic s3c_set_platdata for USB OHCI
  ARM: SAMSUNG: Use generic s3c_set_platdata for HWMON
  ARM: SAMSUNG: Use generic s3c_set_platdata for FB
  ARM: SAMSUNG: Use generic s3c_set_platdata for TS
  ARM: S3C64XX: Add PWM backlight support on SMDK6410
  ARM: S5P64X0: Add PWM backlight support on SMDK6450
  ARM: S5P64X0: Add PWM backlight support on SMDK6440
  ARM: S5PC100: Add PWM backlight support on SMDKC100
  ARM: S5PV210: Add PWM backlight support on SMDKV210
  ARM: EXYNOS4: Add PWM backlight support on SMDKC210
  ARM: EXYNOS4: Add PWM backlight support on SMDKV310
  ARM: SAMSUNG: Create a common infrastructure for PWM backlight support
  clocksource: convert 32-bit down counting clocksource on S5PV210/S5P64X0
  ...

Fix up trivial conflict in arch/arm/mach-imx/mach-scb9328.c

6 files changed, 123 insertions, 88 deletions

diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 6d03643b9bd1..993a3146fd35 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -719,9 +719,15 @@ static void __init cdce_clk_init(void)
         }
 }
 
+#define DM6467T_EVM_REF_FREQ            33000000
+
 static void __init davinci_map_io(void)
 {
         dm646x_init();
+
+        if (machine_is_davinci_dm6467tevm())
+                davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);
+
         cdce_clk_init();
 }
 
@@ -785,17 +791,6 @@ static __init void evm_init(void)
         soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID;
 }
 
-#define DM646X_EVM_REF_FREQ             27000000
-#define DM6467T_EVM_REF_FREQ            33000000
-
-void __init dm646x_board_setup_refclk(struct clk *clk)
-{
-        if (machine_is_davinci_dm6467tevm())
-                clk->rate = DM6467T_EVM_REF_FREQ;
-        else
-                clk->rate = DM646X_EVM_REF_FREQ;
-}
-
 MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
         .boot_params  = (0x80000100),
         .map_io       = davinci_map_io,
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index e4e3af179f02..ae653194b645 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -368,6 +368,12 @@ static unsigned long clk_leafclk_recalc(struct clk *clk)
         return clk->parent->rate;
 }
 
+int davinci_simple_set_rate(struct clk *clk, unsigned long rate)
+{
+        clk->rate = rate;
+        return 0;
+}
+
 static unsigned long clk_pllclk_recalc(struct clk *clk)
 {
         u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
@@ -506,6 +512,38 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
 }
 EXPORT_SYMBOL(davinci_set_pllrate);
 
+/**
+ * davinci_set_refclk_rate() - Set the reference clock rate
+ * @rate:       The new rate.
+ *
+ * Sets the reference clock rate to a given value. This will most likely
+ * result in the entire clock tree getting updated.
+ *
+ * This is used to support boards which use a reference clock different
+ * than that used by default in <soc>.c file. The reference clock rate
+ * should be updated early in the boot process; ideally soon after the
+ * clock tree has been initialized once with the default reference clock
+ * rate (davinci_common_init()).
+ *
+ * Returns 0 on success, error otherwise.
+ */
+int davinci_set_refclk_rate(unsigned long rate)
+{
+        struct clk *refclk;
+
+        refclk = clk_get(NULL, "ref");
+        if (IS_ERR(refclk)) {
+                pr_err("%s: failed to get reference clock.\n", __func__);
+                return PTR_ERR(refclk);
+        }
+
+        clk_set_rate(refclk, rate);
+
+        clk_put(refclk);
+
+        return 0;
+}
+
 int __init davinci_clk_init(struct clk_lookup *clocks)
   {
         struct clk_lookup *c;
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 0dd22031ec62..50b2482e0ba2 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -123,6 +123,8 @@ int davinci_clk_init(struct clk_lookup *clocks);
 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
                                 unsigned int mult, unsigned int postdiv);
 int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
+int davinci_set_refclk_rate(unsigned long rate);
+int davinci_simple_set_rate(struct clk *clk, unsigned long rate);
 
 extern struct platform_device davinci_wdt_device;
 extern void davinci_watchdog_reset(struct platform_device *);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index e00d61e2efbe..1802e711a2b8 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -43,6 +43,7 @@
 /*
  * Device specific clocks
  */
+#define DM646X_REF_FREQ         27000000
 #define DM646X_AUX_FREQ         24000000
 
 static struct pll_data pll1_data = {
@@ -57,6 +58,8 @@ static struct pll_data pll2_data = {
 
 static struct clk ref_clk = {
         .name = "ref_clk",
+        .rate = DM646X_REF_FREQ,
+        .set_rate = davinci_simple_set_rate,
 };
 
 static struct clk aux_clkin = {
@@ -902,7 +905,6 @@ int __init dm646x_init_edma(struct edma_rsv_info *rsv)
 
 void __init dm646x_init(void)
 {
-        dm646x_board_setup_refclk(&ref_clk);
         davinci_common_init(&davinci_soc_info_dm646x);
 }
 
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 7a27f3f13913..2a00fe5ac253 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -15,7 +15,6 @@
 #include <mach/asp.h>
 #include <linux/i2c.h>
 #include <linux/videodev2.h>
-#include <linux/clk.h>
 #include <linux/davinci_emac.h>
 
 #define DM646X_EMAC_BASE                (0x01C80000)
@@ -31,7 +30,6 @@
 void __init dm646x_init(void);
 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
-void __init dm646x_board_setup_refclk(struct clk *clk);
 int __init dm646x_init_edma(struct edma_rsv_info *rsv);
 
 void dm646x_video_init(void);
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index a47e6f29206e..1110fdd77ba4 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -30,47 +30,47 @@
 #define DAVINCI_PWR_SLEEP_CNTRL_BASE    0x01C41000
 
 /* Power and Sleep Controller (PSC) Domains */
-#define DAVINCI_GPSC_ARMDOMAIN      0
-#define DAVINCI_GPSC_DSPDOMAIN      1
+#define DAVINCI_GPSC_ARMDOMAIN          0
+#define DAVINCI_GPSC_DSPDOMAIN          1
 
-#define DAVINCI_LPSC_VPSSMSTR       0
-#define DAVINCI_LPSC_VPSSSLV        1
-#define DAVINCI_LPSC_TPCC           2
-#define DAVINCI_LPSC_TPTC0          3
-#define DAVINCI_LPSC_TPTC1          4
-#define DAVINCI_LPSC_EMAC           5
-#define DAVINCI_LPSC_EMAC_WRAPPER   6
-#define DAVINCI_LPSC_USB            9
-#define DAVINCI_LPSC_ATA            10
-#define DAVINCI_LPSC_VLYNQ          11
-#define DAVINCI_LPSC_UHPI           12
-#define DAVINCI_LPSC_DDR_EMIF       13
-#define DAVINCI_LPSC_AEMIF          14
-#define DAVINCI_LPSC_MMC_SD         15
-#define DAVINCI_LPSC_McBSP          17
-#define DAVINCI_LPSC_I2C            18
-#define DAVINCI_LPSC_UART0          19
-#define DAVINCI_LPSC_UART1          20
-#define DAVINCI_LPSC_UART2          21
-#define DAVINCI_LPSC_SPI            22
-#define DAVINCI_LPSC_PWM0           23
-#define DAVINCI_LPSC_PWM1           24
-#define DAVINCI_LPSC_PWM2           25
-#define DAVINCI_LPSC_GPIO           26
-#define DAVINCI_LPSC_TIMER0         27
-#define DAVINCI_LPSC_TIMER1         28
-#define DAVINCI_LPSC_TIMER2         29
-#define DAVINCI_LPSC_SYSTEM_SUBSYS  30
-#define DAVINCI_LPSC_ARM            31
-#define DAVINCI_LPSC_SCR2           32
-#define DAVINCI_LPSC_SCR3           33
-#define DAVINCI_LPSC_SCR4           34
-#define DAVINCI_LPSC_CROSSBAR       35
-#define DAVINCI_LPSC_CFG27          36
-#define DAVINCI_LPSC_CFG3           37
-#define DAVINCI_LPSC_CFG5           38
-#define DAVINCI_LPSC_GEM            39
-#define DAVINCI_LPSC_IMCOP          40
+#define DAVINCI_LPSC_VPSSMSTR           0
+#define DAVINCI_LPSC_VPSSSLV            1
+#define DAVINCI_LPSC_TPCC               2
+#define DAVINCI_LPSC_TPTC0              3
+#define DAVINCI_LPSC_TPTC1              4
+#define DAVINCI_LPSC_EMAC               5
+#define DAVINCI_LPSC_EMAC_WRAPPER       6
+#define DAVINCI_LPSC_USB                9
+#define DAVINCI_LPSC_ATA                10
+#define DAVINCI_LPSC_VLYNQ              11
+#define DAVINCI_LPSC_UHPI               12
+#define DAVINCI_LPSC_DDR_EMIF           13
+#define DAVINCI_LPSC_AEMIF              14
+#define DAVINCI_LPSC_MMC_SD             15
+#define DAVINCI_LPSC_McBSP              17
+#define DAVINCI_LPSC_I2C                18
+#define DAVINCI_LPSC_UART0              19
+#define DAVINCI_LPSC_UART1              20
+#define DAVINCI_LPSC_UART2              21
+#define DAVINCI_LPSC_SPI                22
+#define DAVINCI_LPSC_PWM0               23
+#define DAVINCI_LPSC_PWM1               24
+#define DAVINCI_LPSC_PWM2               25
+#define DAVINCI_LPSC_GPIO               26
+#define DAVINCI_LPSC_TIMER0             27
+#define DAVINCI_LPSC_TIMER1             28
+#define DAVINCI_LPSC_TIMER2             29
+#define DAVINCI_LPSC_SYSTEM_SUBSYS      30
+#define DAVINCI_LPSC_ARM                31
+#define DAVINCI_LPSC_SCR2               32
+#define DAVINCI_LPSC_SCR3               33
+#define DAVINCI_LPSC_SCR4               34
+#define DAVINCI_LPSC_CROSSBAR           35
+#define DAVINCI_LPSC_CFG27              36
+#define DAVINCI_LPSC_CFG3               37
+#define DAVINCI_LPSC_CFG5               38
+#define DAVINCI_LPSC_GEM                39
+#define DAVINCI_LPSC_IMCOP              40
 
 #define DM355_LPSC_TIMER3               5
 #define DM355_LPSC_SPI1                 6
@@ -102,39 +102,39 @@
 /*
  * LPSC Assignments
  */
-#define DM646X_LPSC_ARM            0
-#define DM646X_LPSC_C64X_CPU       1
-#define DM646X_LPSC_HDVICP0        2
-#define DM646X_LPSC_HDVICP1        3
-#define DM646X_LPSC_TPCC           4
-#define DM646X_LPSC_TPTC0          5
-#define DM646X_LPSC_TPTC1          6
-#define DM646X_LPSC_TPTC2          7
-#define DM646X_LPSC_TPTC3          8
-#define DM646X_LPSC_PCI            13
-#define DM646X_LPSC_EMAC           14
-#define DM646X_LPSC_VDCE           15
-#define DM646X_LPSC_VPSSMSTR       16
-#define DM646X_LPSC_VPSSSLV        17
-#define DM646X_LPSC_TSIF0          18
-#define DM646X_LPSC_TSIF1          19
-#define DM646X_LPSC_DDR_EMIF       20
-#define DM646X_LPSC_AEMIF          21
-#define DM646X_LPSC_McASP0         22
-#define DM646X_LPSC_McASP1         23
-#define DM646X_LPSC_CRGEN0         24
-#define DM646X_LPSC_CRGEN1         25
-#define DM646X_LPSC_UART0          26
-#define DM646X_LPSC_UART1          27
-#define DM646X_LPSC_UART2          28
-#define DM646X_LPSC_PWM0           29
-#define DM646X_LPSC_PWM1           30
-#define DM646X_LPSC_I2C            31
-#define DM646X_LPSC_SPI            32
-#define DM646X_LPSC_GPIO           33
-#define DM646X_LPSC_TIMER0         34
-#define DM646X_LPSC_TIMER1         35
-#define DM646X_LPSC_ARM_INTC       45
+#define DM646X_LPSC_ARM         0
+#define DM646X_LPSC_C64X_CPU    1
+#define DM646X_LPSC_HDVICP0     2
+#define DM646X_LPSC_HDVICP1     3
+#define DM646X_LPSC_TPCC        4
+#define DM646X_LPSC_TPTC0       5
+#define DM646X_LPSC_TPTC1       6
+#define DM646X_LPSC_TPTC2       7
+#define DM646X_LPSC_TPTC3       8
+#define DM646X_LPSC_PCI         13
+#define DM646X_LPSC_EMAC        14
+#define DM646X_LPSC_VDCE        15
+#define DM646X_LPSC_VPSSMSTR    16
+#define DM646X_LPSC_VPSSSLV     17
+#define DM646X_LPSC_TSIF0       18
+#define DM646X_LPSC_TSIF1       19
+#define DM646X_LPSC_DDR_EMIF    20
+#define DM646X_LPSC_AEMIF       21
+#define DM646X_LPSC_McASP0      22
+#define DM646X_LPSC_McASP1      23
+#define DM646X_LPSC_CRGEN0      24
+#define DM646X_LPSC_CRGEN1      25
+#define DM646X_LPSC_UART0       26
+#define DM646X_LPSC_UART1       27
+#define DM646X_LPSC_UART2       28
+#define DM646X_LPSC_PWM0        29
+#define DM646X_LPSC_PWM1        30
+#define DM646X_LPSC_I2C         31
+#define DM646X_LPSC_SPI         32
+#define DM646X_LPSC_GPIO        33
+#define DM646X_LPSC_TIMER0      34
+#define DM646X_LPSC_TIMER1      35
+#define DM646X_LPSC_ARM_INTC    45
 
 /* PSC0 defines */
 #define DA8XX_LPSC0_TPCC                0
@@ -243,7 +243,7 @@
 #define PSC_STATE_DISABLE       2
 #define PSC_STATE_ENABLE        3
 
-#define MDSTAT_STATE_MASK 0x1f
+#define MDSTAT_STATE_MASK       0x1f
 
 #ifndef __ASSEMBLER__