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authorSandeep Paulraj <s-paulraj@ti.com>2009-06-11 09:41:05 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2009-08-26 03:56:57 -0400
commitfb8fcb891390639d6258c816abb537663495da0c (patch)
tree41172c12bc61a3b14d7d613d7f3f133215680a13 /arch/arm/mach-davinci
parent5fcd294df26e6160f32ea551ef074630b4df728d (diff)
davinci: Adding DM365 SOC Support
The patch adds base support for new TI SOC DM365, which s similar to the dm355. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci')
-rw-r--r--arch/arm/mach-davinci/clock.c5
-rw-r--r--arch/arm/mach-davinci/dm365.c699
-rw-r--r--arch/arm/mach-davinci/include/mach/cputype.h8
-rw-r--r--arch/arm/mach-davinci/include/mach/dm365.h29
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h36
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h81
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h18
7 files changed, 875 insertions, 1 deletions
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 39bf321d70a2..83d54d50b5ea 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -227,7 +227,10 @@ static void __init clk_pll_init(struct clk *clk)
227 if (ctrl & PLLCTL_PLLEN) { 227 if (ctrl & PLLCTL_PLLEN) {
228 bypass = 0; 228 bypass = 0;
229 mult = __raw_readl(pll->base + PLLM); 229 mult = __raw_readl(pll->base + PLLM);
230 mult = (mult & PLLM_PLLM_MASK) + 1; 230 if (cpu_is_davinci_dm365())
231 mult = 2 * (mult & PLLM_PLLM_MASK);
232 else
233 mult = (mult & PLLM_PLLM_MASK) + 1;
231 } else 234 } else
232 bypass = 1; 235 bypass = 1;
233 236
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
new file mode 100644
index 000000000000..69d35d947767
--- /dev/null
+++ b/arch/arm/mach-davinci/dm365.c
@@ -0,0 +1,699 @@
1/*
2 * TI DaVinci DM365 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/clk.h>
18#include <linux/serial_8250.h>
19#include <linux/platform_device.h>
20#include <linux/dma-mapping.h>
21#include <linux/gpio.h>
22
23#include <asm/mach/map.h>
24
25#include <mach/dm365.h>
26#include <mach/clock.h>
27#include <mach/cputype.h>
28#include <mach/edma.h>
29#include <mach/psc.h>
30#include <mach/mux.h>
31#include <mach/irqs.h>
32#include <mach/time.h>
33#include <mach/serial.h>
34#include <mach/common.h>
35
36#include "clock.h"
37#include "mux.h"
38
39#define DM365_REF_FREQ 24000000 /* 24 MHz on the DM365 EVM */
40
41static struct pll_data pll1_data = {
42 .num = 1,
43 .phys_base = DAVINCI_PLL1_BASE,
44 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
45};
46
47static struct pll_data pll2_data = {
48 .num = 2,
49 .phys_base = DAVINCI_PLL2_BASE,
50 .flags = PLL_HAS_POSTDIV | PLL_HAS_PREDIV,
51};
52
53static struct clk ref_clk = {
54 .name = "ref_clk",
55 .rate = DM365_REF_FREQ,
56};
57
58static struct clk pll1_clk = {
59 .name = "pll1",
60 .parent = &ref_clk,
61 .flags = CLK_PLL,
62 .pll_data = &pll1_data,
63};
64
65static struct clk pll1_aux_clk = {
66 .name = "pll1_aux_clk",
67 .parent = &pll1_clk,
68 .flags = CLK_PLL | PRE_PLL,
69};
70
71static struct clk pll1_sysclkbp = {
72 .name = "pll1_sysclkbp",
73 .parent = &pll1_clk,
74 .flags = CLK_PLL | PRE_PLL,
75 .div_reg = BPDIV
76};
77
78static struct clk clkout0_clk = {
79 .name = "clkout0",
80 .parent = &pll1_clk,
81 .flags = CLK_PLL | PRE_PLL,
82};
83
84static struct clk pll1_sysclk1 = {
85 .name = "pll1_sysclk1",
86 .parent = &pll1_clk,
87 .flags = CLK_PLL,
88 .div_reg = PLLDIV1,
89};
90
91static struct clk pll1_sysclk2 = {
92 .name = "pll1_sysclk2",
93 .parent = &pll1_clk,
94 .flags = CLK_PLL,
95 .div_reg = PLLDIV2,
96};
97
98static struct clk pll1_sysclk3 = {
99 .name = "pll1_sysclk3",
100 .parent = &pll1_clk,
101 .flags = CLK_PLL,
102 .div_reg = PLLDIV3,
103};
104
105static struct clk pll1_sysclk4 = {
106 .name = "pll1_sysclk4",
107 .parent = &pll1_clk,
108 .flags = CLK_PLL,
109 .div_reg = PLLDIV4,
110};
111
112static struct clk pll1_sysclk5 = {
113 .name = "pll1_sysclk5",
114 .parent = &pll1_clk,
115 .flags = CLK_PLL,
116 .div_reg = PLLDIV5,
117};
118
119static struct clk pll1_sysclk6 = {
120 .name = "pll1_sysclk6",
121 .parent = &pll1_clk,
122 .flags = CLK_PLL,
123 .div_reg = PLLDIV6,
124};
125
126static struct clk pll1_sysclk7 = {
127 .name = "pll1_sysclk7",
128 .parent = &pll1_clk,
129 .flags = CLK_PLL,
130 .div_reg = PLLDIV7,
131};
132
133static struct clk pll1_sysclk8 = {
134 .name = "pll1_sysclk8",
135 .parent = &pll1_clk,
136 .flags = CLK_PLL,
137 .div_reg = PLLDIV8,
138};
139
140static struct clk pll1_sysclk9 = {
141 .name = "pll1_sysclk9",
142 .parent = &pll1_clk,
143 .flags = CLK_PLL,
144 .div_reg = PLLDIV9,
145};
146
147static struct clk pll2_clk = {
148 .name = "pll2",
149 .parent = &ref_clk,
150 .flags = CLK_PLL,
151 .pll_data = &pll2_data,
152};
153
154static struct clk pll2_aux_clk = {
155 .name = "pll2_aux_clk",
156 .parent = &pll2_clk,
157 .flags = CLK_PLL | PRE_PLL,
158};
159
160static struct clk clkout1_clk = {
161 .name = "clkout1",
162 .parent = &pll2_clk,
163 .flags = CLK_PLL | PRE_PLL,
164};
165
166static struct clk pll2_sysclk1 = {
167 .name = "pll2_sysclk1",
168 .parent = &pll2_clk,
169 .flags = CLK_PLL,
170 .div_reg = PLLDIV1,
171};
172
173static struct clk pll2_sysclk2 = {
174 .name = "pll2_sysclk2",
175 .parent = &pll2_clk,
176 .flags = CLK_PLL,
177 .div_reg = PLLDIV2,
178};
179
180static struct clk pll2_sysclk3 = {
181 .name = "pll2_sysclk3",
182 .parent = &pll2_clk,
183 .flags = CLK_PLL,
184 .div_reg = PLLDIV3,
185};
186
187static struct clk pll2_sysclk4 = {
188 .name = "pll2_sysclk4",
189 .parent = &pll2_clk,
190 .flags = CLK_PLL,
191 .div_reg = PLLDIV4,
192};
193
194static struct clk pll2_sysclk5 = {
195 .name = "pll2_sysclk5",
196 .parent = &pll2_clk,
197 .flags = CLK_PLL,
198 .div_reg = PLLDIV5,
199};
200
201static struct clk pll2_sysclk6 = {
202 .name = "pll2_sysclk6",
203 .parent = &pll2_clk,
204 .flags = CLK_PLL,
205 .div_reg = PLLDIV6,
206};
207
208static struct clk pll2_sysclk7 = {
209 .name = "pll2_sysclk7",
210 .parent = &pll2_clk,
211 .flags = CLK_PLL,
212 .div_reg = PLLDIV7,
213};
214
215static struct clk pll2_sysclk8 = {
216 .name = "pll2_sysclk8",
217 .parent = &pll2_clk,
218 .flags = CLK_PLL,
219 .div_reg = PLLDIV8,
220};
221
222static struct clk pll2_sysclk9 = {
223 .name = "pll2_sysclk9",
224 .parent = &pll2_clk,
225 .flags = CLK_PLL,
226 .div_reg = PLLDIV9,
227};
228
229static struct clk vpss_dac_clk = {
230 .name = "vpss_dac",
231 .parent = &pll1_sysclk3,
232 .lpsc = DM365_LPSC_DAC_CLK,
233};
234
235static struct clk vpss_master_clk = {
236 .name = "vpss_master",
237 .parent = &pll1_sysclk5,
238 .lpsc = DM365_LPSC_VPSSMSTR,
239 .flags = CLK_PSC,
240};
241
242static struct clk arm_clk = {
243 .name = "arm_clk",
244 .parent = &pll2_sysclk2,
245 .lpsc = DAVINCI_LPSC_ARM,
246 .flags = ALWAYS_ENABLED,
247};
248
249static struct clk uart0_clk = {
250 .name = "uart0",
251 .parent = &pll1_aux_clk,
252 .lpsc = DAVINCI_LPSC_UART0,
253};
254
255static struct clk uart1_clk = {
256 .name = "uart1",
257 .parent = &pll1_sysclk4,
258 .lpsc = DAVINCI_LPSC_UART1,
259};
260
261static struct clk i2c_clk = {
262 .name = "i2c",
263 .parent = &pll1_aux_clk,
264 .lpsc = DAVINCI_LPSC_I2C,
265};
266
267static struct clk mmcsd0_clk = {
268 .name = "mmcsd0",
269 .parent = &pll1_sysclk8,
270 .lpsc = DAVINCI_LPSC_MMC_SD,
271};
272
273static struct clk mmcsd1_clk = {
274 .name = "mmcsd1",
275 .parent = &pll1_sysclk4,
276 .lpsc = DM365_LPSC_MMC_SD1,
277};
278
279static struct clk spi0_clk = {
280 .name = "spi0",
281 .parent = &pll1_sysclk4,
282 .lpsc = DAVINCI_LPSC_SPI,
283};
284
285static struct clk spi1_clk = {
286 .name = "spi1",
287 .parent = &pll1_sysclk4,
288 .lpsc = DM365_LPSC_SPI1,
289};
290
291static struct clk spi2_clk = {
292 .name = "spi2",
293 .parent = &pll1_sysclk4,
294 .lpsc = DM365_LPSC_SPI2,
295};
296
297static struct clk spi3_clk = {
298 .name = "spi3",
299 .parent = &pll1_sysclk4,
300 .lpsc = DM365_LPSC_SPI3,
301};
302
303static struct clk spi4_clk = {
304 .name = "spi4",
305 .parent = &pll1_aux_clk,
306 .lpsc = DM365_LPSC_SPI4,
307};
308
309static struct clk gpio_clk = {
310 .name = "gpio",
311 .parent = &pll1_sysclk4,
312 .lpsc = DAVINCI_LPSC_GPIO,
313};
314
315static struct clk aemif_clk = {
316 .name = "aemif",
317 .parent = &pll1_sysclk4,
318 .lpsc = DAVINCI_LPSC_AEMIF,
319};
320
321static struct clk pwm0_clk = {
322 .name = "pwm0",
323 .parent = &pll1_aux_clk,
324 .lpsc = DAVINCI_LPSC_PWM0,
325};
326
327static struct clk pwm1_clk = {
328 .name = "pwm1",
329 .parent = &pll1_aux_clk,
330 .lpsc = DAVINCI_LPSC_PWM1,
331};
332
333static struct clk pwm2_clk = {
334 .name = "pwm2",
335 .parent = &pll1_aux_clk,
336 .lpsc = DAVINCI_LPSC_PWM2,
337};
338
339static struct clk pwm3_clk = {
340 .name = "pwm3",
341 .parent = &ref_clk,
342 .lpsc = DM365_LPSC_PWM3,
343};
344
345static struct clk timer0_clk = {
346 .name = "timer0",
347 .parent = &pll1_aux_clk,
348 .lpsc = DAVINCI_LPSC_TIMER0,
349};
350
351static struct clk timer1_clk = {
352 .name = "timer1",
353 .parent = &pll1_aux_clk,
354 .lpsc = DAVINCI_LPSC_TIMER1,
355};
356
357static struct clk timer2_clk = {
358 .name = "timer2",
359 .parent = &pll1_aux_clk,
360 .lpsc = DAVINCI_LPSC_TIMER2,
361 .usecount = 1,
362};
363
364static struct clk timer3_clk = {
365 .name = "timer3",
366 .parent = &pll1_aux_clk,
367 .lpsc = DM365_LPSC_TIMER3,
368};
369
370static struct clk usb_clk = {
371 .name = "usb",
372 .parent = &pll2_sysclk1,
373 .lpsc = DAVINCI_LPSC_USB,
374};
375
376static struct clk emac_clk = {
377 .name = "emac",
378 .parent = &pll1_sysclk4,
379 .lpsc = DM365_LPSC_EMAC,
380};
381
382static struct clk voicecodec_clk = {
383 .name = "voice_codec",
384 .parent = &pll2_sysclk4,
385 .lpsc = DM365_LPSC_VOICE_CODEC,
386};
387
388static struct clk asp0_clk = {
389 .name = "asp0",
390 .parent = &pll1_sysclk4,
391 .lpsc = DM365_LPSC_McBSP1,
392};
393
394static struct clk rto_clk = {
395 .name = "rto",
396 .parent = &pll1_sysclk4,
397 .lpsc = DM365_LPSC_RTO,
398};
399
400static struct clk mjcp_clk = {
401 .name = "mjcp",
402 .parent = &pll1_sysclk3,
403 .lpsc = DM365_LPSC_MJCP,
404};
405
406static struct davinci_clk dm365_clks[] = {
407 CLK(NULL, "ref", &ref_clk),
408 CLK(NULL, "pll1", &pll1_clk),
409 CLK(NULL, "pll1_aux", &pll1_aux_clk),
410 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
411 CLK(NULL, "clkout0", &clkout0_clk),
412 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
413 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
414 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
415 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
416 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
417 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
418 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
419 CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
420 CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
421 CLK(NULL, "pll2", &pll2_clk),
422 CLK(NULL, "pll2_aux", &pll2_aux_clk),
423 CLK(NULL, "clkout1", &clkout1_clk),
424 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
425 CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
426 CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
427 CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
428 CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
429 CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
430 CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
431 CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
432 CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
433 CLK(NULL, "vpss_dac", &vpss_dac_clk),
434 CLK(NULL, "vpss_master", &vpss_master_clk),
435 CLK(NULL, "arm", &arm_clk),
436 CLK(NULL, "uart0", &uart0_clk),
437 CLK(NULL, "uart1", &uart1_clk),
438 CLK("i2c_davinci.1", NULL, &i2c_clk),
439 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
440 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
441 CLK("spi_davinci.0", NULL, &spi0_clk),
442 CLK("spi_davinci.1", NULL, &spi1_clk),
443 CLK("spi_davinci.2", NULL, &spi2_clk),
444 CLK("spi_davinci.3", NULL, &spi3_clk),
445 CLK("spi_davinci.4", NULL, &spi4_clk),
446 CLK(NULL, "gpio", &gpio_clk),
447 CLK(NULL, "aemif", &aemif_clk),
448 CLK(NULL, "pwm0", &pwm0_clk),
449 CLK(NULL, "pwm1", &pwm1_clk),
450 CLK(NULL, "pwm2", &pwm2_clk),
451 CLK(NULL, "pwm3", &pwm3_clk),
452 CLK(NULL, "timer0", &timer0_clk),
453 CLK(NULL, "timer1", &timer1_clk),
454 CLK("watchdog", NULL, &timer2_clk),
455 CLK(NULL, "timer3", &timer3_clk),
456 CLK(NULL, "usb", &usb_clk),
457 CLK("davinci_emac.1", NULL, &emac_clk),
458 CLK("voice_codec", NULL, &voicecodec_clk),
459 CLK("soc-audio.0", NULL, &asp0_clk),
460 CLK(NULL, "rto", &rto_clk),
461 CLK(NULL, "mjcp", &mjcp_clk),
462 CLK(NULL, NULL, NULL),
463};
464
465/*----------------------------------------------------------------------*/
466
467#define PINMUX0 0x00
468#define PINMUX1 0x04
469#define PINMUX2 0x08
470#define PINMUX3 0x0c
471#define PINMUX4 0x10
472#define INTMUX 0x18
473#define EVTMUX 0x1c
474
475
476static const struct mux_config dm365_pins[] = {
477#ifdef CONFIG_DAVINCI_MUX
478MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
479
480MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
481MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
482MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
483MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
484MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
485MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
486
487MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
488MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
489
490MUX_CFG(DM365, AEMIF_AR, 2, 0, 3, 1, false)
491MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
492MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
493MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
494MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
495
496MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
497MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
498MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
499MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
500MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
501MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
502
503MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
504MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
505MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
506MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
507MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
508
509MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
510MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
511MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
512MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
513MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
514MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
515
516MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
517MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
518MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
519MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
520MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
521MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
522MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
523MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
524MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
525MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
526MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
527MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
528MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
529MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
530MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
531MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
532MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
533#endif
534};
535
536
537static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
538 [IRQ_VDINT0] = 2,
539 [IRQ_VDINT1] = 6,
540 [IRQ_VDINT2] = 6,
541 [IRQ_HISTINT] = 6,
542 [IRQ_H3AINT] = 6,
543 [IRQ_PRVUINT] = 6,
544 [IRQ_RSZINT] = 6,
545 [IRQ_DM365_INSFINT] = 7,
546 [IRQ_VENCINT] = 6,
547 [IRQ_ASQINT] = 6,
548 [IRQ_IMXINT] = 6,
549 [IRQ_DM365_IMCOPINT] = 4,
550 [IRQ_USBINT] = 4,
551 [IRQ_DM365_RTOINT] = 7,
552 [IRQ_DM365_TINT5] = 7,
553 [IRQ_DM365_TINT6] = 5,
554 [IRQ_CCINT0] = 5,
555 [IRQ_CCERRINT] = 5,
556 [IRQ_TCERRINT0] = 5,
557 [IRQ_TCERRINT] = 7,
558 [IRQ_PSCIN] = 4,
559 [IRQ_DM365_SPINT2_1] = 7,
560 [IRQ_DM365_TINT7] = 7,
561 [IRQ_DM365_SDIOINT0] = 7,
562 [IRQ_MBXINT] = 7,
563 [IRQ_MBRINT] = 7,
564 [IRQ_MMCINT] = 7,
565 [IRQ_DM365_MMCINT1] = 7,
566 [IRQ_DM365_PWMINT3] = 7,
567 [IRQ_DDRINT] = 4,
568 [IRQ_AEMIFINT] = 2,
569 [IRQ_DM365_SDIOINT1] = 2,
570 [IRQ_TINT0_TINT12] = 7,
571 [IRQ_TINT0_TINT34] = 7,
572 [IRQ_TINT1_TINT12] = 7,
573 [IRQ_TINT1_TINT34] = 7,
574 [IRQ_PWMINT0] = 7,
575 [IRQ_PWMINT1] = 3,
576 [IRQ_PWMINT2] = 3,
577 [IRQ_I2C] = 3,
578 [IRQ_UARTINT0] = 3,
579 [IRQ_UARTINT1] = 3,
580 [IRQ_DM365_SPIINT0_0] = 3,
581 [IRQ_DM365_SPIINT3_0] = 3,
582 [IRQ_DM365_GPIO0] = 3,
583 [IRQ_DM365_GPIO1] = 7,
584 [IRQ_DM365_GPIO2] = 4,
585 [IRQ_DM365_GPIO3] = 4,
586 [IRQ_DM365_GPIO4] = 7,
587 [IRQ_DM365_GPIO5] = 7,
588 [IRQ_DM365_GPIO6] = 7,
589 [IRQ_DM365_GPIO7] = 7,
590 [IRQ_DM365_EMAC_RXTHRESH] = 7,
591 [IRQ_DM365_EMAC_RXPULSE] = 7,
592 [IRQ_DM365_EMAC_TXPULSE] = 7,
593 [IRQ_DM365_EMAC_MISCPULSE] = 7,
594 [IRQ_DM365_GPIO12] = 7,
595 [IRQ_DM365_GPIO13] = 7,
596 [IRQ_DM365_GPIO14] = 7,
597 [IRQ_DM365_GPIO15] = 7,
598 [IRQ_DM365_KEYINT] = 7,
599 [IRQ_DM365_TCERRINT2] = 7,
600 [IRQ_DM365_TCERRINT3] = 7,
601 [IRQ_DM365_EMUINT] = 7,
602};
603
604static struct map_desc dm365_io_desc[] = {
605 {
606 .virtual = IO_VIRT,
607 .pfn = __phys_to_pfn(IO_PHYS),
608 .length = IO_SIZE,
609 .type = MT_DEVICE
610 },
611 {
612 .virtual = SRAM_VIRT,
613 .pfn = __phys_to_pfn(0x00010000),
614 .length = SZ_32K,
615 /* MT_MEMORY_NONCACHED requires supersection alignment */
616 .type = MT_DEVICE,
617 },
618};
619
620/* Contents of JTAG ID register used to identify exact cpu type */
621static struct davinci_id dm365_ids[] = {
622 {
623 .variant = 0x0,
624 .part_no = 0xb83e,
625 .manufacturer = 0x017,
626 .cpu_id = DAVINCI_CPU_ID_DM365,
627 .name = "dm365",
628 },
629};
630
631static void __iomem *dm365_psc_bases[] = {
632 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
633};
634
635struct davinci_timer_info dm365_timer_info = {
636 .timers = davinci_timer_instance,
637 .clockevent_id = T0_BOT,
638 .clocksource_id = T0_TOP,
639};
640
641static struct plat_serial8250_port dm365_serial_platform_data[] = {
642 {
643 .mapbase = DAVINCI_UART0_BASE,
644 .irq = IRQ_UARTINT0,
645 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
646 UPF_IOREMAP,
647 .iotype = UPIO_MEM,
648 .regshift = 2,
649 },
650 {
651 .mapbase = DAVINCI_UART1_BASE,
652 .irq = IRQ_UARTINT1,
653 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
654 UPF_IOREMAP,
655 .iotype = UPIO_MEM,
656 .regshift = 2,
657 },
658 {
659 .flags = 0
660 },
661};
662
663static struct platform_device dm365_serial_device = {
664 .name = "serial8250",
665 .id = PLAT8250_DEV_PLATFORM,
666 .dev = {
667 .platform_data = dm365_serial_platform_data,
668 },
669};
670
671static struct davinci_soc_info davinci_soc_info_dm365 = {
672 .io_desc = dm365_io_desc,
673 .io_desc_num = ARRAY_SIZE(dm365_io_desc),
674 .jtag_id_base = IO_ADDRESS(0x01c40028),
675 .ids = dm365_ids,
676 .ids_num = ARRAY_SIZE(dm365_ids),
677 .cpu_clks = dm365_clks,
678 .psc_bases = dm365_psc_bases,
679 .psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
680 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
681 .pinmux_pins = dm365_pins,
682 .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
683 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
684 .intc_type = DAVINCI_INTC_TYPE_AINTC,
685 .intc_irq_prios = dm365_default_priorities,
686 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
687 .timer_info = &dm365_timer_info,
688 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
689 .gpio_num = 104,
690 .gpio_irq = 44,
691 .serial_dev = &dm365_serial_device,
692 .sram_dma = 0x00010000,
693 .sram_len = SZ_32K,
694};
695
696void __init dm365_init(void)
697{
698 davinci_common_init(&davinci_soc_info_dm365);
699}
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index d12a5ed2959a..56b92d49e293 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -30,6 +30,7 @@ struct davinci_id {
30#define DAVINCI_CPU_ID_DM6446 0x64460000 30#define DAVINCI_CPU_ID_DM6446 0x64460000
31#define DAVINCI_CPU_ID_DM6467 0x64670000 31#define DAVINCI_CPU_ID_DM6467 0x64670000
32#define DAVINCI_CPU_ID_DM355 0x03550000 32#define DAVINCI_CPU_ID_DM355 0x03550000
33#define DAVINCI_CPU_ID_DM365 0x03650000
33 34
34#define IS_DAVINCI_CPU(type, id) \ 35#define IS_DAVINCI_CPU(type, id) \
35static inline int is_davinci_ ##type(void) \ 36static inline int is_davinci_ ##type(void) \
@@ -40,6 +41,7 @@ static inline int is_davinci_ ##type(void) \
40IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446) 41IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446)
41IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) 42IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467)
42IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) 43IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
44IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
43 45
44#ifdef CONFIG_ARCH_DAVINCI_DM644x 46#ifdef CONFIG_ARCH_DAVINCI_DM644x
45#define cpu_is_davinci_dm644x() is_davinci_dm644x() 47#define cpu_is_davinci_dm644x() is_davinci_dm644x()
@@ -59,4 +61,10 @@ IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
59#define cpu_is_davinci_dm355() 0 61#define cpu_is_davinci_dm355() 0
60#endif 62#endif
61 63
64#ifdef CONFIG_ARCH_DAVINCI_DM365
65#define cpu_is_davinci_dm365() is_davinci_dm365()
66#else
67#define cpu_is_davinci_dm365() 0
68#endif
69
62#endif 70#endif
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
new file mode 100644
index 000000000000..09db4343bb4c
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) 2009 Texas Instruments Incorporated
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#ifndef __ASM_ARCH_DM365_H
14#define __ASM_ARCH_DM665_H
15
16#include <linux/platform_device.h>
17#include <mach/hardware.h>
18#include <mach/emac.h>
19
20#define DM365_EMAC_BASE (0x01D07000)
21#define DM365_EMAC_CNTRL_OFFSET (0x0000)
22#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000)
23#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000)
24#define DM365_EMAC_MDIO_OFFSET (0x4000)
25#define DM365_EMAC_CNTRL_RAM_SIZE (0x2000)
26
27void __init dm365_init(void);
28
29#endif /* __ASM_ARCH_DM365_H */
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index bc5d6aaa69a3..0d34f2fb0993 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -206,4 +206,40 @@
206#define IRQ_DM355_GPIOBNK5 59 206#define IRQ_DM355_GPIOBNK5 59
207#define IRQ_DM355_GPIOBNK6 60 207#define IRQ_DM355_GPIOBNK6 60
208 208
209/* DaVinci DM365-specific Interrupts */
210#define IRQ_DM365_INSFINT 7
211#define IRQ_DM365_IMCOPINT 11
212#define IRQ_DM365_RTOINT 13
213#define IRQ_DM365_TINT5 14
214#define IRQ_DM365_TINT6 15
215#define IRQ_DM365_SPINT2_1 21
216#define IRQ_DM365_TINT7 22
217#define IRQ_DM365_SDIOINT0 23
218#define IRQ_DM365_MMCINT1 27
219#define IRQ_DM365_PWMINT3 28
220#define IRQ_DM365_SDIOINT1 31
221#define IRQ_DM365_SPIINT0_0 42
222#define IRQ_DM365_SPIINT3_0 43
223#define IRQ_DM365_GPIO0 44
224#define IRQ_DM365_GPIO1 45
225#define IRQ_DM365_GPIO2 46
226#define IRQ_DM365_GPIO3 47
227#define IRQ_DM365_GPIO4 48
228#define IRQ_DM365_GPIO5 49
229#define IRQ_DM365_GPIO6 50
230#define IRQ_DM365_GPIO7 51
231#define IRQ_DM365_EMAC_RXTHRESH 52
232#define IRQ_DM365_EMAC_RXPULSE 53
233#define IRQ_DM365_EMAC_TXPULSE 54
234#define IRQ_DM365_EMAC_MISCPULSE 55
235#define IRQ_DM365_GPIO12 56
236#define IRQ_DM365_GPIO13 57
237#define IRQ_DM365_GPIO14 58
238#define IRQ_DM365_GPIO15 59
239#define IRQ_DM365_ADCINT 59
240#define IRQ_DM365_KEYINT 60
241#define IRQ_DM365_TCERRINT2 61
242#define IRQ_DM365_TCERRINT3 62
243#define IRQ_DM365_EMUINT 63
244
209#endif /* __ASM_ARCH_IRQS_H */ 245#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 27378458542f..c182bd458d73 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -156,6 +156,87 @@ enum davinci_dm355_index {
156 DM355_EVT26_MMC0_RX, 156 DM355_EVT26_MMC0_RX,
157}; 157};
158 158
159enum davinci_dm365_index {
160 /* MMC/SD 0 */
161 DM365_MMCSD0,
162
163 /* MMC/SD 1 */
164 DM365_SD1_CLK,
165 DM365_SD1_CMD,
166 DM365_SD1_DATA3,
167 DM365_SD1_DATA2,
168 DM365_SD1_DATA1,
169 DM365_SD1_DATA0,
170
171 /* I2C */
172 DM365_I2C_SDA,
173 DM365_I2C_SCL,
174
175 /* AEMIF */
176 DM365_AEMIF_AR,
177 DM365_AEMIF_A3,
178 DM365_AEMIF_A7,
179 DM365_AEMIF_D15_8,
180 DM365_AEMIF_CE0,
181
182 /* ASP0 function */
183 DM365_MCBSP0_BDX,
184 DM365_MCBSP0_X,
185 DM365_MCBSP0_BFSX,
186 DM365_MCBSP0_BDR,
187 DM365_MCBSP0_R,
188 DM365_MCBSP0_BFSR,
189
190 /* SPI0 */
191 DM365_SPI0_SCLK,
192 DM365_SPI0_SDI,
193 DM365_SPI0_SDO,
194 DM365_SPI0_SDENA0,
195 DM365_SPI0_SDENA1,
196
197 /* UART */
198 DM365_UART0_RXD,
199 DM365_UART0_TXD,
200 DM365_UART1_RXD,
201 DM365_UART1_TXD,
202 DM365_UART1_RTS,
203 DM365_UART1_CTS,
204
205 /* EMAC */
206 DM365_EMAC_TX_EN,
207 DM365_EMAC_TX_CLK,
208 DM365_EMAC_COL,
209 DM365_EMAC_TXD3,
210 DM365_EMAC_TXD2,
211 DM365_EMAC_TXD1,
212 DM365_EMAC_TXD0,
213 DM365_EMAC_RXD3,
214 DM365_EMAC_RXD2,
215 DM365_EMAC_RXD1,
216 DM365_EMAC_RXD0,
217 DM365_EMAC_RX_CLK,
218 DM365_EMAC_RX_DV,
219 DM365_EMAC_RX_ER,
220 DM365_EMAC_CRS,
221 DM365_EMAC_MDIO,
222 DM365_EMAC_MDCLK,
223
224 /* IRQ muxing */
225 DM365_INT_EDMA_CC,
226 DM365_INT_EDMA_TC0_ERR,
227 DM365_INT_EDMA_TC1_ERR,
228 DM365_INT_PRTCSS,
229 DM365_INT_EMAC_RXTHRESH,
230 DM365_INT_EMAC_RXPULSE,
231 DM365_INT_EMAC_TXPULSE,
232 DM365_INT_EMAC_MISCPULSE,
233
234 /* EDMA event muxing */
235 DM365_EVT2_ASP_TX,
236 DM365_EVT3_ASP_RX,
237 DM365_EVT26_MMC0_RX,
238};
239
159#ifdef CONFIG_DAVINCI_MUX 240#ifdef CONFIG_DAVINCI_MUX
160/* setup pin muxing */ 241/* setup pin muxing */
161extern int davinci_cfg_reg(unsigned long reg_cfg); 242extern int davinci_cfg_reg(unsigned long reg_cfg);
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index ab8a2586d1cc..2bb414b14297 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -81,6 +81,24 @@
81#define DM355_LPSC_RTO 12 81#define DM355_LPSC_RTO 12
82#define DM355_LPSC_VPSS_DAC 41 82#define DM355_LPSC_VPSS_DAC 41
83 83
84/* DM365 */
85#define DM365_LPSC_TIMER3 5
86#define DM365_LPSC_SPI1 6
87#define DM365_LPSC_MMC_SD1 7
88#define DM365_LPSC_McBSP1 8
89#define DM365_LPSC_PWM3 10
90#define DM365_LPSC_SPI2 11
91#define DM365_LPSC_RTO 12
92#define DM365_LPSC_TIMER4 17
93#define DM365_LPSC_SPI0 22
94#define DM365_LPSC_SPI3 38
95#define DM365_LPSC_SPI4 39
96#define DM365_LPSC_EMAC 40
97#define DM365_LPSC_VOICE_CODEC 44
98#define DM365_LPSC_DAC_CLK 46
99#define DM365_LPSC_VPSSMSTR 47
100#define DM365_LPSC_MJCP 50
101
84/* 102/*
85 * LPSC Assignments 103 * LPSC Assignments
86 */ 104 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 18:40:24 -0500