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authorCyril Chemparathy <cyril@ti.com>2010-05-18 12:51:19 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2010-06-21 15:48:30 -0400
commit4d1e78480cc5b5937c9384e47a0b2b0cdf117da4 (patch)
tree3773a06c3b3bfe05ea80a10dfdbe3920daa1d1cc /arch/arm/mach-davinci/tnetv107x.c
parent38db050e0bfc8c483e5d7b85feef23d46069ec18 (diff)
Davinci: tnetv107x soc support
TNETV107X is a Texas Instruments SOC that shares a number of common features with the Davinci architecture. Some of the key differences between traditional Davincis and this new SOC are as follow: 1. The SOCs clock architecture includes a new spread-spectrum PLL. Some elements of the clock architecture are reused from Davinci (e.g. LPSC), but the PLL related code is overridden using existing interfaces in "struct clk". 2. The MMR layout on this SOC is substantially different from Davinci. Consequently, the fixed I/O map is a whole lot more convoluted (more so than DA8xx). The net impact here is that IO_ADDRESS() will not work on this SoC, and therefore all mappings have to be through ioremap(). Signed-off-by: Cyril Chemparathy <cyril@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/tnetv107x.c')
-rw-r--r--arch/arm/mach-davinci/tnetv107x.c753
1 files changed, 753 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
new file mode 100644
index 000000000000..864e60482c53
--- /dev/null
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -0,0 +1,753 @@
1/*
2 * Texas Instruments TNETV107X SoC Support
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21
22#include <asm/mach/map.h>
23
24#include <mach/common.h>
25#include <mach/time.h>
26#include <mach/cputype.h>
27#include <mach/psc.h>
28#include <mach/cp_intc.h>
29#include <mach/irqs.h>
30#include <mach/gpio.h>
31#include <mach/hardware.h>
32#include <mach/tnetv107x.h>
33
34#include "clock.h"
35#include "mux.h"
36
37/* Base addresses for on-chip devices */
38#define TNETV107X_INTC_BASE 0x03000000
39#define TNETV107X_TIMER0_BASE 0x08086500
40#define TNETV107X_TIMER1_BASE 0x08086600
41#define TNETV107X_CHIP_CFG_BASE 0x08087000
42#define TNETV107X_GPIO_BASE 0x08088000
43#define TNETV107X_CLOCK_CONTROL_BASE 0x0808a000
44#define TNETV107X_PSC_BASE 0x0808b000
45
46/* Reference clock frequencies */
47#define OSC_FREQ_ONCHIP (24000 * 1000)
48#define OSC_FREQ_OFFCHIP_SYS (25000 * 1000)
49#define OSC_FREQ_OFFCHIP_ETH (25000 * 1000)
50#define OSC_FREQ_OFFCHIP_TDM (19200 * 1000)
51
52#define N_PLLS 3
53
54/* Clock Control Registers */
55struct clk_ctrl_regs {
56 u32 pll_bypass;
57 u32 _reserved0;
58 u32 gem_lrst;
59 u32 _reserved1;
60 u32 pll_unlock_stat;
61 u32 sys_unlock;
62 u32 eth_unlock;
63 u32 tdm_unlock;
64};
65
66/* SSPLL Registers */
67struct sspll_regs {
68 u32 modes;
69 u32 post_div;
70 u32 pre_div;
71 u32 mult_factor;
72 u32 divider_range;
73 u32 bw_divider;
74 u32 spr_amount;
75 u32 spr_rate_div;
76 u32 diag;
77};
78
79/* Watchdog Timer Registers */
80struct wdt_regs {
81 u32 kick_lock;
82 u32 kick;
83 u32 change_lock;
84 u32 change ;
85 u32 disable_lock;
86 u32 disable;
87 u32 prescale_lock;
88 u32 prescale;
89};
90
91static struct clk_ctrl_regs __iomem *clk_ctrl_regs;
92
93static struct sspll_regs __iomem *sspll_regs[N_PLLS];
94static int sspll_regs_base[N_PLLS] = { 0x40, 0x80, 0xc0 };
95
96/* PLL bypass bit shifts in clk_ctrl_regs->pll_bypass register */
97static u32 bypass_mask[N_PLLS] = { BIT(0), BIT(2), BIT(1) };
98
99/* offchip (external) reference clock frequencies */
100static u32 pll_ext_freq[] = {
101 OSC_FREQ_OFFCHIP_SYS,
102 OSC_FREQ_OFFCHIP_TDM,
103 OSC_FREQ_OFFCHIP_ETH
104};
105
106/* PSC control registers */
107static u32 psc_regs[] __initconst = { TNETV107X_PSC_BASE };
108
109/* Host map for interrupt controller */
110static u32 intc_host_map[] = { 0x01010000, 0x01010101, -1 };
111
112static unsigned long clk_sspll_recalc(struct clk *clk);
113
114/* Level 1 - the PLLs */
115#define define_pll_clk(cname, pll, divmask, base) \
116 static struct pll_data pll_##cname##_data = { \
117 .num = pll, \
118 .div_ratio_mask = divmask, \
119 .phys_base = base + \
120 TNETV107X_CLOCK_CONTROL_BASE, \
121 }; \
122 static struct clk pll_##cname##_clk = { \
123 .name = "pll_" #cname "_clk", \
124 .pll_data = &pll_##cname##_data, \
125 .flags = CLK_PLL, \
126 .recalc = clk_sspll_recalc, \
127 }
128
129define_pll_clk(sys, 0, 0x1ff, 0x600);
130define_pll_clk(tdm, 1, 0x0ff, 0x200);
131define_pll_clk(eth, 2, 0x0ff, 0x400);
132
133/* Level 2 - divided outputs from the PLLs */
134#define define_pll_div_clk(pll, cname, div) \
135 static struct clk pll##_##cname##_clk = { \
136 .name = #pll "_" #cname "_clk",\
137 .parent = &pll_##pll##_clk, \
138 .flags = CLK_PLL, \
139 .div_reg = PLLDIV##div, \
140 }
141
142define_pll_div_clk(sys, arm1176, 1);
143define_pll_div_clk(sys, dsp, 2);
144define_pll_div_clk(sys, ddr, 3);
145define_pll_div_clk(sys, full, 4);
146define_pll_div_clk(sys, lcd, 5);
147define_pll_div_clk(sys, vlynq_ref, 6);
148define_pll_div_clk(sys, tsc, 7);
149define_pll_div_clk(sys, half, 8);
150
151define_pll_div_clk(eth, 5mhz, 1);
152define_pll_div_clk(eth, 50mhz, 2);
153define_pll_div_clk(eth, 125mhz, 3);
154define_pll_div_clk(eth, 250mhz, 4);
155define_pll_div_clk(eth, 25mhz, 5);
156
157define_pll_div_clk(tdm, 0, 1);
158define_pll_div_clk(tdm, extra, 2);
159define_pll_div_clk(tdm, 1, 3);
160
161
162/* Level 3 - LPSC gated clocks */
163#define __lpsc_clk(cname, _parent, mod, flg) \
164 static struct clk clk_##cname = { \
165 .name = #cname, \
166 .parent = &_parent, \
167 .lpsc = TNETV107X_LPSC_##mod,\
168 .flags = flg, \
169 }
170
171#define lpsc_clk_enabled(cname, parent, mod) \
172 __lpsc_clk(cname, parent, mod, ALWAYS_ENABLED)
173
174#define lpsc_clk(cname, parent, mod) \
175 __lpsc_clk(cname, parent, mod, 0)
176
177lpsc_clk_enabled(arm, sys_arm1176_clk, ARM);
178lpsc_clk_enabled(gem, sys_dsp_clk, GEM);
179lpsc_clk_enabled(ddr2_phy, sys_ddr_clk, DDR2_PHY);
180lpsc_clk_enabled(tpcc, sys_full_clk, TPCC);
181lpsc_clk_enabled(tptc0, sys_full_clk, TPTC0);
182lpsc_clk_enabled(tptc1, sys_full_clk, TPTC1);
183lpsc_clk_enabled(ram, sys_full_clk, RAM);
184lpsc_clk_enabled(aemif, sys_full_clk, AEMIF);
185lpsc_clk_enabled(chipcfg, sys_half_clk, CHIP_CFG);
186lpsc_clk_enabled(rom, sys_half_clk, ROM);
187lpsc_clk_enabled(secctl, sys_half_clk, SECCTL);
188lpsc_clk_enabled(keymgr, sys_half_clk, KEYMGR);
189lpsc_clk_enabled(gpio, sys_half_clk, GPIO);
190lpsc_clk_enabled(debugss, sys_half_clk, DEBUGSS);
191lpsc_clk_enabled(system, sys_half_clk, SYSTEM);
192lpsc_clk_enabled(ddr2_vrst, sys_ddr_clk, DDR2_EMIF1_VRST);
193lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk, DDR2_EMIF2_VCTL_RST);
194lpsc_clk_enabled(wdt_arm, sys_half_clk, WDT_ARM);
195
196lpsc_clk(mbx_lite, sys_arm1176_clk, MBX_LITE);
197lpsc_clk(ethss, eth_125mhz_clk, ETHSS);
198lpsc_clk(tsc, sys_tsc_clk, TSC);
199lpsc_clk(uart0, sys_half_clk, UART0);
200lpsc_clk(uart1, sys_half_clk, UART1);
201lpsc_clk(uart2, sys_half_clk, UART2);
202lpsc_clk(pktsec, sys_half_clk, PKTSEC);
203lpsc_clk(keypad, sys_half_clk, KEYPAD);
204lpsc_clk(mdio, sys_half_clk, MDIO);
205lpsc_clk(sdio0, sys_half_clk, SDIO0);
206lpsc_clk(sdio1, sys_half_clk, SDIO1);
207lpsc_clk(timer0, sys_half_clk, TIMER0);
208lpsc_clk(timer1, sys_half_clk, TIMER1);
209lpsc_clk(wdt_dsp, sys_half_clk, WDT_DSP);
210lpsc_clk(ssp, sys_half_clk, SSP);
211lpsc_clk(tdm0, tdm_0_clk, TDM0);
212lpsc_clk(tdm1, tdm_1_clk, TDM1);
213lpsc_clk(vlynq, sys_vlynq_ref_clk, VLYNQ);
214lpsc_clk(mcdma, sys_half_clk, MCDMA);
215lpsc_clk(usb0, sys_half_clk, USB0);
216lpsc_clk(usb1, sys_half_clk, USB1);
217lpsc_clk(usbss, sys_half_clk, USBSS);
218lpsc_clk(ethss_rgmii, eth_250mhz_clk, ETHSS_RGMII);
219lpsc_clk(imcop, sys_dsp_clk, IMCOP);
220lpsc_clk(spare, sys_half_clk, SPARE);
221
222/* LCD needs a full power down to clear controller state */
223__lpsc_clk(lcd, sys_lcd_clk, LCD, PSC_SWRSTDISABLE);
224
225
226/* Level 4 - leaf clocks for LPSC modules shared across drivers */
227static struct clk clk_rng = { .name = "rng", .parent = &clk_pktsec };
228static struct clk clk_pka = { .name = "pka", .parent = &clk_pktsec };
229
230static struct clk_lookup clks[] = {
231 CLK(NULL, "pll_sys_clk", &pll_sys_clk),
232 CLK(NULL, "pll_eth_clk", &pll_eth_clk),
233 CLK(NULL, "pll_tdm_clk", &pll_tdm_clk),
234 CLK(NULL, "sys_arm1176_clk", &sys_arm1176_clk),
235 CLK(NULL, "sys_dsp_clk", &sys_dsp_clk),
236 CLK(NULL, "sys_ddr_clk", &sys_ddr_clk),
237 CLK(NULL, "sys_full_clk", &sys_full_clk),
238 CLK(NULL, "sys_lcd_clk", &sys_lcd_clk),
239 CLK(NULL, "sys_vlynq_ref_clk", &sys_vlynq_ref_clk),
240 CLK(NULL, "sys_tsc_clk", &sys_tsc_clk),
241 CLK(NULL, "sys_half_clk", &sys_half_clk),
242 CLK(NULL, "eth_5mhz_clk", &eth_5mhz_clk),
243 CLK(NULL, "eth_50mhz_clk", &eth_50mhz_clk),
244 CLK(NULL, "eth_125mhz_clk", &eth_125mhz_clk),
245 CLK(NULL, "eth_250mhz_clk", &eth_250mhz_clk),
246 CLK(NULL, "eth_25mhz_clk", &eth_25mhz_clk),
247 CLK(NULL, "tdm_0_clk", &tdm_0_clk),
248 CLK(NULL, "tdm_extra_clk", &tdm_extra_clk),
249 CLK(NULL, "tdm_1_clk", &tdm_1_clk),
250 CLK(NULL, "clk_arm", &clk_arm),
251 CLK(NULL, "clk_gem", &clk_gem),
252 CLK(NULL, "clk_ddr2_phy", &clk_ddr2_phy),
253 CLK(NULL, "clk_tpcc", &clk_tpcc),
254 CLK(NULL, "clk_tptc0", &clk_tptc0),
255 CLK(NULL, "clk_tptc1", &clk_tptc1),
256 CLK(NULL, "clk_ram", &clk_ram),
257 CLK(NULL, "clk_mbx_lite", &clk_mbx_lite),
258 CLK("tnetv107x-fb.0", NULL, &clk_lcd),
259 CLK(NULL, "clk_ethss", &clk_ethss),
260 CLK(NULL, "aemif", &clk_aemif),
261 CLK(NULL, "clk_chipcfg", &clk_chipcfg),
262 CLK("tnetv107x-ts.0", NULL, &clk_tsc),
263 CLK(NULL, "clk_rom", &clk_rom),
264 CLK(NULL, "uart2", &clk_uart2),
265 CLK(NULL, "clk_pktsec", &clk_pktsec),
266 CLK("tnetv107x-rng.0", NULL, &clk_rng),
267 CLK("tnetv107x-pka.0", NULL, &clk_pka),
268 CLK(NULL, "clk_secctl", &clk_secctl),
269 CLK(NULL, "clk_keymgr", &clk_keymgr),
270 CLK("tnetv107x-keypad.0", NULL, &clk_keypad),
271 CLK(NULL, "clk_gpio", &clk_gpio),
272 CLK(NULL, "clk_mdio", &clk_mdio),
273 CLK("davinci_mmc.0", NULL, &clk_sdio0),
274 CLK(NULL, "uart0", &clk_uart0),
275 CLK(NULL, "uart1", &clk_uart1),
276 CLK(NULL, "timer0", &clk_timer0),
277 CLK(NULL, "timer1", &clk_timer1),
278 CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm),
279 CLK(NULL, "clk_wdt_dsp", &clk_wdt_dsp),
280 CLK("ti-ssp.0", NULL, &clk_ssp),
281 CLK(NULL, "clk_tdm0", &clk_tdm0),
282 CLK(NULL, "clk_vlynq", &clk_vlynq),
283 CLK(NULL, "clk_mcdma", &clk_mcdma),
284 CLK(NULL, "clk_usb0", &clk_usb0),
285 CLK(NULL, "clk_tdm1", &clk_tdm1),
286 CLK(NULL, "clk_debugss", &clk_debugss),
287 CLK(NULL, "clk_ethss_rgmii", &clk_ethss_rgmii),
288 CLK(NULL, "clk_system", &clk_system),
289 CLK(NULL, "clk_imcop", &clk_imcop),
290 CLK(NULL, "clk_spare", &clk_spare),
291 CLK("davinci_mmc.1", NULL, &clk_sdio1),
292 CLK(NULL, "clk_usb1", &clk_usb1),
293 CLK(NULL, "clk_usbss", &clk_usbss),
294 CLK(NULL, "clk_ddr2_vrst", &clk_ddr2_vrst),
295 CLK(NULL, "clk_ddr2_vctl_rst", &clk_ddr2_vctl_rst),
296 CLK(NULL, NULL, NULL),
297};
298
299static const struct mux_config pins[] = {
300#ifdef CONFIG_DAVINCI_MUX
301 MUX_CFG(TNETV107X, ASR_A00, 0, 0, 0x1f, 0x00, false)
302 MUX_CFG(TNETV107X, GPIO32, 0, 0, 0x1f, 0x04, false)
303 MUX_CFG(TNETV107X, ASR_A01, 0, 5, 0x1f, 0x00, false)
304 MUX_CFG(TNETV107X, GPIO33, 0, 5, 0x1f, 0x04, false)
305 MUX_CFG(TNETV107X, ASR_A02, 0, 10, 0x1f, 0x00, false)
306 MUX_CFG(TNETV107X, GPIO34, 0, 10, 0x1f, 0x04, false)
307 MUX_CFG(TNETV107X, ASR_A03, 0, 15, 0x1f, 0x00, false)
308 MUX_CFG(TNETV107X, GPIO35, 0, 15, 0x1f, 0x04, false)
309 MUX_CFG(TNETV107X, ASR_A04, 0, 20, 0x1f, 0x00, false)
310 MUX_CFG(TNETV107X, GPIO36, 0, 20, 0x1f, 0x04, false)
311 MUX_CFG(TNETV107X, ASR_A05, 0, 25, 0x1f, 0x00, false)
312 MUX_CFG(TNETV107X, GPIO37, 0, 25, 0x1f, 0x04, false)
313 MUX_CFG(TNETV107X, ASR_A06, 1, 0, 0x1f, 0x00, false)
314 MUX_CFG(TNETV107X, GPIO38, 1, 0, 0x1f, 0x04, false)
315 MUX_CFG(TNETV107X, ASR_A07, 1, 5, 0x1f, 0x00, false)
316 MUX_CFG(TNETV107X, GPIO39, 1, 5, 0x1f, 0x04, false)
317 MUX_CFG(TNETV107X, ASR_A08, 1, 10, 0x1f, 0x00, false)
318 MUX_CFG(TNETV107X, GPIO40, 1, 10, 0x1f, 0x04, false)
319 MUX_CFG(TNETV107X, ASR_A09, 1, 15, 0x1f, 0x00, false)
320 MUX_CFG(TNETV107X, GPIO41, 1, 15, 0x1f, 0x04, false)
321 MUX_CFG(TNETV107X, ASR_A10, 1, 20, 0x1f, 0x00, false)
322 MUX_CFG(TNETV107X, GPIO42, 1, 20, 0x1f, 0x04, false)
323 MUX_CFG(TNETV107X, ASR_A11, 1, 25, 0x1f, 0x00, false)
324 MUX_CFG(TNETV107X, BOOT_STRP_0, 1, 25, 0x1f, 0x04, false)
325 MUX_CFG(TNETV107X, ASR_A12, 2, 0, 0x1f, 0x00, false)
326 MUX_CFG(TNETV107X, BOOT_STRP_1, 2, 0, 0x1f, 0x04, false)
327 MUX_CFG(TNETV107X, ASR_A13, 2, 5, 0x1f, 0x00, false)
328 MUX_CFG(TNETV107X, GPIO43, 2, 5, 0x1f, 0x04, false)
329 MUX_CFG(TNETV107X, ASR_A14, 2, 10, 0x1f, 0x00, false)
330 MUX_CFG(TNETV107X, GPIO44, 2, 10, 0x1f, 0x04, false)
331 MUX_CFG(TNETV107X, ASR_A15, 2, 15, 0x1f, 0x00, false)
332 MUX_CFG(TNETV107X, GPIO45, 2, 15, 0x1f, 0x04, false)
333 MUX_CFG(TNETV107X, ASR_A16, 2, 20, 0x1f, 0x00, false)
334 MUX_CFG(TNETV107X, GPIO46, 2, 20, 0x1f, 0x04, false)
335 MUX_CFG(TNETV107X, ASR_A17, 2, 25, 0x1f, 0x00, false)
336 MUX_CFG(TNETV107X, GPIO47, 2, 25, 0x1f, 0x04, false)
337 MUX_CFG(TNETV107X, ASR_A18, 3, 0, 0x1f, 0x00, false)
338 MUX_CFG(TNETV107X, GPIO48, 3, 0, 0x1f, 0x04, false)
339 MUX_CFG(TNETV107X, SDIO1_DATA3_0, 3, 0, 0x1f, 0x1c, false)
340 MUX_CFG(TNETV107X, ASR_A19, 3, 5, 0x1f, 0x00, false)
341 MUX_CFG(TNETV107X, GPIO49, 3, 5, 0x1f, 0x04, false)
342 MUX_CFG(TNETV107X, SDIO1_DATA2_0, 3, 5, 0x1f, 0x1c, false)
343 MUX_CFG(TNETV107X, ASR_A20, 3, 10, 0x1f, 0x00, false)
344 MUX_CFG(TNETV107X, GPIO50, 3, 10, 0x1f, 0x04, false)
345 MUX_CFG(TNETV107X, SDIO1_DATA1_0, 3, 10, 0x1f, 0x1c, false)
346 MUX_CFG(TNETV107X, ASR_A21, 3, 15, 0x1f, 0x00, false)
347 MUX_CFG(TNETV107X, GPIO51, 3, 15, 0x1f, 0x04, false)
348 MUX_CFG(TNETV107X, SDIO1_DATA0_0, 3, 15, 0x1f, 0x1c, false)
349 MUX_CFG(TNETV107X, ASR_A22, 3, 20, 0x1f, 0x00, false)
350 MUX_CFG(TNETV107X, GPIO52, 3, 20, 0x1f, 0x04, false)
351 MUX_CFG(TNETV107X, SDIO1_CMD_0, 3, 20, 0x1f, 0x1c, false)
352 MUX_CFG(TNETV107X, ASR_A23, 3, 25, 0x1f, 0x00, false)
353 MUX_CFG(TNETV107X, GPIO53, 3, 25, 0x1f, 0x04, false)
354 MUX_CFG(TNETV107X, SDIO1_CLK_0, 3, 25, 0x1f, 0x1c, false)
355 MUX_CFG(TNETV107X, ASR_BA_1, 4, 0, 0x1f, 0x00, false)
356 MUX_CFG(TNETV107X, GPIO54, 4, 0, 0x1f, 0x04, false)
357 MUX_CFG(TNETV107X, SYS_PLL_CLK, 4, 0, 0x1f, 0x1c, false)
358 MUX_CFG(TNETV107X, ASR_CS0, 4, 5, 0x1f, 0x00, false)
359 MUX_CFG(TNETV107X, ASR_CS1, 4, 10, 0x1f, 0x00, false)
360 MUX_CFG(TNETV107X, ASR_CS2, 4, 15, 0x1f, 0x00, false)
361 MUX_CFG(TNETV107X, TDM_PLL_CLK, 4, 15, 0x1f, 0x1c, false)
362 MUX_CFG(TNETV107X, ASR_CS3, 4, 20, 0x1f, 0x00, false)
363 MUX_CFG(TNETV107X, ETH_PHY_CLK, 4, 20, 0x1f, 0x0c, false)
364 MUX_CFG(TNETV107X, ASR_D00, 4, 25, 0x1f, 0x00, false)
365 MUX_CFG(TNETV107X, GPIO55, 4, 25, 0x1f, 0x1c, false)
366 MUX_CFG(TNETV107X, ASR_D01, 5, 0, 0x1f, 0x00, false)
367 MUX_CFG(TNETV107X, GPIO56, 5, 0, 0x1f, 0x1c, false)
368 MUX_CFG(TNETV107X, ASR_D02, 5, 5, 0x1f, 0x00, false)
369 MUX_CFG(TNETV107X, GPIO57, 5, 5, 0x1f, 0x1c, false)
370 MUX_CFG(TNETV107X, ASR_D03, 5, 10, 0x1f, 0x00, false)
371 MUX_CFG(TNETV107X, GPIO58, 5, 10, 0x1f, 0x1c, false)
372 MUX_CFG(TNETV107X, ASR_D04, 5, 15, 0x1f, 0x00, false)
373 MUX_CFG(TNETV107X, GPIO59_0, 5, 15, 0x1f, 0x1c, false)
374 MUX_CFG(TNETV107X, ASR_D05, 5, 20, 0x1f, 0x00, false)
375 MUX_CFG(TNETV107X, GPIO60_0, 5, 20, 0x1f, 0x1c, false)
376 MUX_CFG(TNETV107X, ASR_D06, 5, 25, 0x1f, 0x00, false)
377 MUX_CFG(TNETV107X, GPIO61_0, 5, 25, 0x1f, 0x1c, false)
378 MUX_CFG(TNETV107X, ASR_D07, 6, 0, 0x1f, 0x00, false)
379 MUX_CFG(TNETV107X, GPIO62_0, 6, 0, 0x1f, 0x1c, false)
380 MUX_CFG(TNETV107X, ASR_D08, 6, 5, 0x1f, 0x00, false)
381 MUX_CFG(TNETV107X, GPIO63_0, 6, 5, 0x1f, 0x1c, false)
382 MUX_CFG(TNETV107X, ASR_D09, 6, 10, 0x1f, 0x00, false)
383 MUX_CFG(TNETV107X, GPIO64_0, 6, 10, 0x1f, 0x1c, false)
384 MUX_CFG(TNETV107X, ASR_D10, 6, 15, 0x1f, 0x00, false)
385 MUX_CFG(TNETV107X, SDIO1_DATA3_1, 6, 15, 0x1f, 0x1c, false)
386 MUX_CFG(TNETV107X, ASR_D11, 6, 20, 0x1f, 0x00, false)
387 MUX_CFG(TNETV107X, SDIO1_DATA2_1, 6, 20, 0x1f, 0x1c, false)
388 MUX_CFG(TNETV107X, ASR_D12, 6, 25, 0x1f, 0x00, false)
389 MUX_CFG(TNETV107X, SDIO1_DATA1_1, 6, 25, 0x1f, 0x1c, false)
390 MUX_CFG(TNETV107X, ASR_D13, 7, 0, 0x1f, 0x00, false)
391 MUX_CFG(TNETV107X, SDIO1_DATA0_1, 7, 0, 0x1f, 0x1c, false)
392 MUX_CFG(TNETV107X, ASR_D14, 7, 5, 0x1f, 0x00, false)
393 MUX_CFG(TNETV107X, SDIO1_CMD_1, 7, 5, 0x1f, 0x1c, false)
394 MUX_CFG(TNETV107X, ASR_D15, 7, 10, 0x1f, 0x00, false)
395 MUX_CFG(TNETV107X, SDIO1_CLK_1, 7, 10, 0x1f, 0x1c, false)
396 MUX_CFG(TNETV107X, ASR_OE, 7, 15, 0x1f, 0x00, false)
397 MUX_CFG(TNETV107X, BOOT_STRP_2, 7, 15, 0x1f, 0x04, false)
398 MUX_CFG(TNETV107X, ASR_RNW, 7, 20, 0x1f, 0x00, false)
399 MUX_CFG(TNETV107X, GPIO29_0, 7, 20, 0x1f, 0x04, false)
400 MUX_CFG(TNETV107X, ASR_WAIT, 7, 25, 0x1f, 0x00, false)
401 MUX_CFG(TNETV107X, GPIO30_0, 7, 25, 0x1f, 0x04, false)
402 MUX_CFG(TNETV107X, ASR_WE, 8, 0, 0x1f, 0x00, false)
403 MUX_CFG(TNETV107X, BOOT_STRP_3, 8, 0, 0x1f, 0x04, false)
404 MUX_CFG(TNETV107X, ASR_WE_DQM0, 8, 5, 0x1f, 0x00, false)
405 MUX_CFG(TNETV107X, GPIO31, 8, 5, 0x1f, 0x04, false)
406 MUX_CFG(TNETV107X, LCD_PD17_0, 8, 5, 0x1f, 0x1c, false)
407 MUX_CFG(TNETV107X, ASR_WE_DQM1, 8, 10, 0x1f, 0x00, false)
408 MUX_CFG(TNETV107X, ASR_BA0_0, 8, 10, 0x1f, 0x04, false)
409 MUX_CFG(TNETV107X, VLYNQ_CLK, 9, 0, 0x1f, 0x00, false)
410 MUX_CFG(TNETV107X, GPIO14, 9, 0, 0x1f, 0x04, false)
411 MUX_CFG(TNETV107X, LCD_PD19_0, 9, 0, 0x1f, 0x1c, false)
412 MUX_CFG(TNETV107X, VLYNQ_RXD0, 9, 5, 0x1f, 0x00, false)
413 MUX_CFG(TNETV107X, GPIO15, 9, 5, 0x1f, 0x04, false)
414 MUX_CFG(TNETV107X, LCD_PD20_0, 9, 5, 0x1f, 0x1c, false)
415 MUX_CFG(TNETV107X, VLYNQ_RXD1, 9, 10, 0x1f, 0x00, false)
416 MUX_CFG(TNETV107X, GPIO16, 9, 10, 0x1f, 0x04, false)
417 MUX_CFG(TNETV107X, LCD_PD21_0, 9, 10, 0x1f, 0x1c, false)
418 MUX_CFG(TNETV107X, VLYNQ_TXD0, 9, 15, 0x1f, 0x00, false)
419 MUX_CFG(TNETV107X, GPIO17, 9, 15, 0x1f, 0x04, false)
420 MUX_CFG(TNETV107X, LCD_PD22_0, 9, 15, 0x1f, 0x1c, false)
421 MUX_CFG(TNETV107X, VLYNQ_TXD1, 9, 20, 0x1f, 0x00, false)
422 MUX_CFG(TNETV107X, GPIO18, 9, 20, 0x1f, 0x04, false)
423 MUX_CFG(TNETV107X, LCD_PD23_0, 9, 20, 0x1f, 0x1c, false)
424 MUX_CFG(TNETV107X, SDIO0_CLK, 10, 0, 0x1f, 0x00, false)
425 MUX_CFG(TNETV107X, GPIO19, 10, 0, 0x1f, 0x04, false)
426 MUX_CFG(TNETV107X, SDIO0_CMD, 10, 5, 0x1f, 0x00, false)
427 MUX_CFG(TNETV107X, GPIO20, 10, 5, 0x1f, 0x04, false)
428 MUX_CFG(TNETV107X, SDIO0_DATA0, 10, 10, 0x1f, 0x00, false)
429 MUX_CFG(TNETV107X, GPIO21, 10, 10, 0x1f, 0x04, false)
430 MUX_CFG(TNETV107X, SDIO0_DATA1, 10, 15, 0x1f, 0x00, false)
431 MUX_CFG(TNETV107X, GPIO22, 10, 15, 0x1f, 0x04, false)
432 MUX_CFG(TNETV107X, SDIO0_DATA2, 10, 20, 0x1f, 0x00, false)
433 MUX_CFG(TNETV107X, GPIO23, 10, 20, 0x1f, 0x04, false)
434 MUX_CFG(TNETV107X, SDIO0_DATA3, 10, 25, 0x1f, 0x00, false)
435 MUX_CFG(TNETV107X, GPIO24, 10, 25, 0x1f, 0x04, false)
436 MUX_CFG(TNETV107X, EMU0, 11, 0, 0x1f, 0x00, false)
437 MUX_CFG(TNETV107X, EMU1, 11, 5, 0x1f, 0x00, false)
438 MUX_CFG(TNETV107X, RTCK, 12, 0, 0x1f, 0x00, false)
439 MUX_CFG(TNETV107X, TRST_N, 12, 5, 0x1f, 0x00, false)
440 MUX_CFG(TNETV107X, TCK, 12, 10, 0x1f, 0x00, false)
441 MUX_CFG(TNETV107X, TDI, 12, 15, 0x1f, 0x00, false)
442 MUX_CFG(TNETV107X, TDO, 12, 20, 0x1f, 0x00, false)
443 MUX_CFG(TNETV107X, TMS, 12, 25, 0x1f, 0x00, false)
444 MUX_CFG(TNETV107X, TDM1_CLK, 13, 0, 0x1f, 0x00, false)
445 MUX_CFG(TNETV107X, TDM1_RX, 13, 5, 0x1f, 0x00, false)
446 MUX_CFG(TNETV107X, TDM1_TX, 13, 10, 0x1f, 0x00, false)
447 MUX_CFG(TNETV107X, TDM1_FS, 13, 15, 0x1f, 0x00, false)
448 MUX_CFG(TNETV107X, KEYPAD_R0, 14, 0, 0x1f, 0x00, false)
449 MUX_CFG(TNETV107X, KEYPAD_R1, 14, 5, 0x1f, 0x00, false)
450 MUX_CFG(TNETV107X, KEYPAD_R2, 14, 10, 0x1f, 0x00, false)
451 MUX_CFG(TNETV107X, KEYPAD_R3, 14, 15, 0x1f, 0x00, false)
452 MUX_CFG(TNETV107X, KEYPAD_R4, 14, 20, 0x1f, 0x00, false)
453 MUX_CFG(TNETV107X, KEYPAD_R5, 14, 25, 0x1f, 0x00, false)
454 MUX_CFG(TNETV107X, KEYPAD_R6, 15, 0, 0x1f, 0x00, false)
455 MUX_CFG(TNETV107X, GPIO12, 15, 0, 0x1f, 0x04, false)
456 MUX_CFG(TNETV107X, KEYPAD_R7, 15, 5, 0x1f, 0x00, false)
457 MUX_CFG(TNETV107X, GPIO10, 15, 5, 0x1f, 0x04, false)
458 MUX_CFG(TNETV107X, KEYPAD_C0, 15, 10, 0x1f, 0x00, false)
459 MUX_CFG(TNETV107X, KEYPAD_C1, 15, 15, 0x1f, 0x00, false)
460 MUX_CFG(TNETV107X, KEYPAD_C2, 15, 20, 0x1f, 0x00, false)
461 MUX_CFG(TNETV107X, KEYPAD_C3, 15, 25, 0x1f, 0x00, false)
462 MUX_CFG(TNETV107X, KEYPAD_C4, 16, 0, 0x1f, 0x00, false)
463 MUX_CFG(TNETV107X, KEYPAD_C5, 16, 5, 0x1f, 0x00, false)
464 MUX_CFG(TNETV107X, KEYPAD_C6, 16, 10, 0x1f, 0x00, false)
465 MUX_CFG(TNETV107X, GPIO13, 16, 10, 0x1f, 0x04, false)
466 MUX_CFG(TNETV107X, TEST_CLK_IN, 16, 10, 0x1f, 0x0c, false)
467 MUX_CFG(TNETV107X, KEYPAD_C7, 16, 15, 0x1f, 0x00, false)
468 MUX_CFG(TNETV107X, GPIO11, 16, 15, 0x1f, 0x04, false)
469 MUX_CFG(TNETV107X, SSP0_0, 17, 0, 0x1f, 0x00, false)
470 MUX_CFG(TNETV107X, SCC_DCLK, 17, 0, 0x1f, 0x04, false)
471 MUX_CFG(TNETV107X, LCD_PD20_1, 17, 0, 0x1f, 0x0c, false)
472 MUX_CFG(TNETV107X, SSP0_1, 17, 5, 0x1f, 0x00, false)
473 MUX_CFG(TNETV107X, SCC_CS_N, 17, 5, 0x1f, 0x04, false)
474 MUX_CFG(TNETV107X, LCD_PD21_1, 17, 5, 0x1f, 0x0c, false)
475 MUX_CFG(TNETV107X, SSP0_2, 17, 10, 0x1f, 0x00, false)
476 MUX_CFG(TNETV107X, SCC_D, 17, 10, 0x1f, 0x04, false)
477 MUX_CFG(TNETV107X, LCD_PD22_1, 17, 10, 0x1f, 0x0c, false)
478 MUX_CFG(TNETV107X, SSP0_3, 17, 15, 0x1f, 0x00, false)
479 MUX_CFG(TNETV107X, SCC_RESETN, 17, 15, 0x1f, 0x04, false)
480 MUX_CFG(TNETV107X, LCD_PD23_1, 17, 15, 0x1f, 0x0c, false)
481 MUX_CFG(TNETV107X, SSP1_0, 18, 0, 0x1f, 0x00, false)
482 MUX_CFG(TNETV107X, GPIO25, 18, 0, 0x1f, 0x04, false)
483 MUX_CFG(TNETV107X, UART2_CTS, 18, 0, 0x1f, 0x0c, false)
484 MUX_CFG(TNETV107X, SSP1_1, 18, 5, 0x1f, 0x00, false)
485 MUX_CFG(TNETV107X, GPIO26, 18, 5, 0x1f, 0x04, false)
486 MUX_CFG(TNETV107X, UART2_RD, 18, 5, 0x1f, 0x0c, false)
487 MUX_CFG(TNETV107X, SSP1_2, 18, 10, 0x1f, 0x00, false)
488 MUX_CFG(TNETV107X, GPIO27, 18, 10, 0x1f, 0x04, false)
489 MUX_CFG(TNETV107X, UART2_RTS, 18, 10, 0x1f, 0x0c, false)
490 MUX_CFG(TNETV107X, SSP1_3, 18, 15, 0x1f, 0x00, false)
491 MUX_CFG(TNETV107X, GPIO28, 18, 15, 0x1f, 0x04, false)
492 MUX_CFG(TNETV107X, UART2_TD, 18, 15, 0x1f, 0x0c, false)
493 MUX_CFG(TNETV107X, UART0_CTS, 19, 0, 0x1f, 0x00, false)
494 MUX_CFG(TNETV107X, UART0_RD, 19, 5, 0x1f, 0x00, false)
495 MUX_CFG(TNETV107X, UART0_RTS, 19, 10, 0x1f, 0x00, false)
496 MUX_CFG(TNETV107X, UART0_TD, 19, 15, 0x1f, 0x00, false)
497 MUX_CFG(TNETV107X, UART1_RD, 19, 20, 0x1f, 0x00, false)
498 MUX_CFG(TNETV107X, UART1_TD, 19, 25, 0x1f, 0x00, false)
499 MUX_CFG(TNETV107X, LCD_AC_NCS, 20, 0, 0x1f, 0x00, false)
500 MUX_CFG(TNETV107X, LCD_HSYNC_RNW, 20, 5, 0x1f, 0x00, false)
501 MUX_CFG(TNETV107X, LCD_VSYNC_A0, 20, 10, 0x1f, 0x00, false)
502 MUX_CFG(TNETV107X, LCD_MCLK, 20, 15, 0x1f, 0x00, false)
503 MUX_CFG(TNETV107X, LCD_PD16_0, 20, 15, 0x1f, 0x0c, false)
504 MUX_CFG(TNETV107X, LCD_PCLK_E, 20, 20, 0x1f, 0x00, false)
505 MUX_CFG(TNETV107X, LCD_PD00, 20, 25, 0x1f, 0x00, false)
506 MUX_CFG(TNETV107X, LCD_PD01, 21, 0, 0x1f, 0x00, false)
507 MUX_CFG(TNETV107X, LCD_PD02, 21, 5, 0x1f, 0x00, false)
508 MUX_CFG(TNETV107X, LCD_PD03, 21, 10, 0x1f, 0x00, false)
509 MUX_CFG(TNETV107X, LCD_PD04, 21, 15, 0x1f, 0x00, false)
510 MUX_CFG(TNETV107X, LCD_PD05, 21, 20, 0x1f, 0x00, false)
511 MUX_CFG(TNETV107X, LCD_PD06, 21, 25, 0x1f, 0x00, false)
512 MUX_CFG(TNETV107X, LCD_PD07, 22, 0, 0x1f, 0x00, false)
513 MUX_CFG(TNETV107X, LCD_PD08, 22, 5, 0x1f, 0x00, false)
514 MUX_CFG(TNETV107X, GPIO59_1, 22, 5, 0x1f, 0x0c, false)
515 MUX_CFG(TNETV107X, LCD_PD09, 22, 10, 0x1f, 0x00, false)
516 MUX_CFG(TNETV107X, GPIO60_1, 22, 10, 0x1f, 0x0c, false)
517 MUX_CFG(TNETV107X, LCD_PD10, 22, 15, 0x1f, 0x00, false)
518 MUX_CFG(TNETV107X, ASR_BA0_1, 22, 15, 0x1f, 0x04, false)
519 MUX_CFG(TNETV107X, GPIO61_1, 22, 15, 0x1f, 0x0c, false)
520 MUX_CFG(TNETV107X, LCD_PD11, 22, 20, 0x1f, 0x00, false)
521 MUX_CFG(TNETV107X, GPIO62_1, 22, 20, 0x1f, 0x0c, false)
522 MUX_CFG(TNETV107X, LCD_PD12, 22, 25, 0x1f, 0x00, false)
523 MUX_CFG(TNETV107X, GPIO63_1, 22, 25, 0x1f, 0x0c, false)
524 MUX_CFG(TNETV107X, LCD_PD13, 23, 0, 0x1f, 0x00, false)
525 MUX_CFG(TNETV107X, GPIO64_1, 23, 0, 0x1f, 0x0c, false)
526 MUX_CFG(TNETV107X, LCD_PD14, 23, 5, 0x1f, 0x00, false)
527 MUX_CFG(TNETV107X, GPIO29_1, 23, 5, 0x1f, 0x0c, false)
528 MUX_CFG(TNETV107X, LCD_PD15, 23, 10, 0x1f, 0x00, false)
529 MUX_CFG(TNETV107X, GPIO30_1, 23, 10, 0x1f, 0x0c, false)
530 MUX_CFG(TNETV107X, EINT0, 24, 0, 0x1f, 0x00, false)
531 MUX_CFG(TNETV107X, GPIO08, 24, 0, 0x1f, 0x04, false)
532 MUX_CFG(TNETV107X, EINT1, 24, 5, 0x1f, 0x00, false)
533 MUX_CFG(TNETV107X, GPIO09, 24, 5, 0x1f, 0x04, false)
534 MUX_CFG(TNETV107X, GPIO00, 24, 10, 0x1f, 0x00, false)
535 MUX_CFG(TNETV107X, LCD_PD20_2, 24, 10, 0x1f, 0x04, false)
536 MUX_CFG(TNETV107X, TDM_CLK_IN_2, 24, 10, 0x1f, 0x0c, false)
537 MUX_CFG(TNETV107X, GPIO01, 24, 15, 0x1f, 0x00, false)
538 MUX_CFG(TNETV107X, LCD_PD21_2, 24, 15, 0x1f, 0x04, false)
539 MUX_CFG(TNETV107X, 24M_CLK_OUT_1, 24, 15, 0x1f, 0x0c, false)
540 MUX_CFG(TNETV107X, GPIO02, 24, 20, 0x1f, 0x00, false)
541 MUX_CFG(TNETV107X, LCD_PD22_2, 24, 20, 0x1f, 0x04, false)
542 MUX_CFG(TNETV107X, GPIO03, 24, 25, 0x1f, 0x00, false)
543 MUX_CFG(TNETV107X, LCD_PD23_2, 24, 25, 0x1f, 0x04, false)
544 MUX_CFG(TNETV107X, GPIO04, 25, 0, 0x1f, 0x00, false)
545 MUX_CFG(TNETV107X, LCD_PD16_1, 25, 0, 0x1f, 0x04, false)
546 MUX_CFG(TNETV107X, USB0_RXERR, 25, 0, 0x1f, 0x0c, false)
547 MUX_CFG(TNETV107X, GPIO05, 25, 5, 0x1f, 0x00, false)
548 MUX_CFG(TNETV107X, LCD_PD17_1, 25, 5, 0x1f, 0x04, false)
549 MUX_CFG(TNETV107X, TDM_CLK_IN_1, 25, 5, 0x1f, 0x0c, false)
550 MUX_CFG(TNETV107X, GPIO06, 25, 10, 0x1f, 0x00, false)
551 MUX_CFG(TNETV107X, LCD_PD18, 25, 10, 0x1f, 0x04, false)
552 MUX_CFG(TNETV107X, 24M_CLK_OUT_2, 25, 10, 0x1f, 0x0c, false)
553 MUX_CFG(TNETV107X, GPIO07, 25, 15, 0x1f, 0x00, false)
554 MUX_CFG(TNETV107X, LCD_PD19_1, 25, 15, 0x1f, 0x04, false)
555 MUX_CFG(TNETV107X, USB1_RXERR, 25, 15, 0x1f, 0x0c, false)
556 MUX_CFG(TNETV107X, ETH_PLL_CLK, 25, 15, 0x1f, 0x1c, false)
557 MUX_CFG(TNETV107X, MDIO, 26, 0, 0x1f, 0x00, false)
558 MUX_CFG(TNETV107X, MDC, 26, 5, 0x1f, 0x00, false)
559 MUX_CFG(TNETV107X, AIC_MUTE_STAT_N, 26, 10, 0x1f, 0x00, false)
560 MUX_CFG(TNETV107X, TDM0_CLK, 26, 10, 0x1f, 0x04, false)
561 MUX_CFG(TNETV107X, AIC_HNS_EN_N, 26, 15, 0x1f, 0x00, false)
562 MUX_CFG(TNETV107X, TDM0_FS, 26, 15, 0x1f, 0x04, false)
563 MUX_CFG(TNETV107X, AIC_HDS_EN_STAT_N, 26, 20, 0x1f, 0x00, false)
564 MUX_CFG(TNETV107X, TDM0_TX, 26, 20, 0x1f, 0x04, false)
565 MUX_CFG(TNETV107X, AIC_HNF_EN_STAT_N, 26, 25, 0x1f, 0x00, false)
566 MUX_CFG(TNETV107X, TDM0_RX, 26, 25, 0x1f, 0x04, false)
567#endif
568};
569
570/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
571static u8 irq_prios[TNETV107X_N_CP_INTC_IRQ] = {
572 /* fill in default priority 7 */
573 [0 ... (TNETV107X_N_CP_INTC_IRQ - 1)] = 7,
574 /* now override as needed, e.g. [xxx] = 5 */
575};
576
577/* Contents of JTAG ID register used to identify exact cpu type */
578static struct davinci_id ids[] = {
579 {
580 .variant = 0x0,
581 .part_no = 0xb8a1,
582 .manufacturer = 0x017,
583 .cpu_id = DAVINCI_CPU_ID_TNETV107X,
584 .name = "tnetv107x rev1.0",
585 },
586};
587
588static struct davinci_timer_instance timer_instance[2] = {
589 {
590 .base = TNETV107X_TIMER0_BASE,
591 .bottom_irq = IRQ_TNETV107X_TIMER_0_TINT12,
592 .top_irq = IRQ_TNETV107X_TIMER_0_TINT34,
593 },
594 {
595 .base = TNETV107X_TIMER1_BASE,
596 .bottom_irq = IRQ_TNETV107X_TIMER_1_TINT12,
597 .top_irq = IRQ_TNETV107X_TIMER_1_TINT34,
598 },
599};
600
601static struct davinci_timer_info timer_info = {
602 .timers = timer_instance,
603 .clockevent_id = T0_BOT,
604 .clocksource_id = T0_TOP,
605};
606
607/*
608 * TNETV107X platforms do not use the static mappings from Davinci
609 * IO_PHYS/IO_VIRT. This SOC's interesting MMRs are at different addresses,
610 * and changing IO_PHYS would break away from existing Davinci SOCs.
611 *
612 * The primary impact of the current model is that IO_ADDRESS() is not to be
613 * used to map registers on TNETV107X.
614 *
615 * 1. The first chunk is for INTC: This needs to be mapped in via iotable
616 * because ioremap() does not seem to be operational at the time when
617 * irqs are initialized. Without this, consistent dma init bombs.
618 *
619 * 2. The second chunk maps in register areas that need to be populated into
620 * davinci_soc_info. Note that alignment restrictions come into play if
621 * low-level debug is enabled (see note in <mach/tnetv107x.h>).
622 */
623static struct map_desc io_desc[] = {
624 { /* INTC */
625 .virtual = IO_VIRT,
626 .pfn = __phys_to_pfn(TNETV107X_INTC_BASE),
627 .length = SZ_16K,
628 .type = MT_DEVICE
629 },
630 { /* Most of the rest */
631 .virtual = TNETV107X_IO_VIRT,
632 .pfn = __phys_to_pfn(TNETV107X_IO_BASE),
633 .length = IO_SIZE - SZ_1M,
634 .type = MT_DEVICE
635 },
636};
637
638static unsigned long clk_sspll_recalc(struct clk *clk)
639{
640 int pll;
641 unsigned long mult = 0, prediv = 1, postdiv = 1;
642 unsigned long ref = OSC_FREQ_ONCHIP, ret;
643 u32 tmp;
644
645 if (WARN_ON(!clk->pll_data))
646 return clk->rate;
647
648 if (!clk_ctrl_regs) {
649 void __iomem *tmp;
650
651 tmp = ioremap(TNETV107X_CLOCK_CONTROL_BASE, SZ_4K);
652
653 if (WARN(!tmp, "failed ioremap for clock control regs\n"))
654 return clk->parent ? clk->parent->rate : 0;
655
656 for (pll = 0; pll < N_PLLS; pll++)
657 sspll_regs[pll] = tmp + sspll_regs_base[pll];
658
659 clk_ctrl_regs = tmp;
660 }
661
662 pll = clk->pll_data->num;
663
664 tmp = __raw_readl(&clk_ctrl_regs->pll_bypass);
665 if (!(tmp & bypass_mask[pll])) {
666 mult = __raw_readl(&sspll_regs[pll]->mult_factor);
667 prediv = __raw_readl(&sspll_regs[pll]->pre_div) + 1;
668 postdiv = __raw_readl(&sspll_regs[pll]->post_div) + 1;
669 }
670
671 tmp = __raw_readl(clk->pll_data->base + PLLCTL);
672 if (tmp & PLLCTL_CLKMODE)
673 ref = pll_ext_freq[pll];
674
675 clk->pll_data->input_rate = ref;
676
677 tmp = __raw_readl(clk->pll_data->base + PLLCTL);
678 if (!(tmp & PLLCTL_PLLEN))
679 return ref;
680
681 ret = ref;
682 if (mult)
683 ret += ((unsigned long long)ref * mult) / 256;
684
685 ret /= (prediv * postdiv);
686
687 return ret;
688}
689
690static void tnetv107x_watchdog_reset(struct platform_device *pdev)
691{
692 struct wdt_regs __iomem *regs;
693
694 regs = ioremap(pdev->resource[0].start, SZ_4K);
695
696 /* disable watchdog */
697 __raw_writel(0x7777, &regs->disable_lock);
698 __raw_writel(0xcccc, &regs->disable_lock);
699 __raw_writel(0xdddd, &regs->disable_lock);
700 __raw_writel(0, &regs->disable);
701
702 /* program prescale */
703 __raw_writel(0x5a5a, &regs->prescale_lock);
704 __raw_writel(0xa5a5, &regs->prescale_lock);
705 __raw_writel(0, &regs->prescale);
706
707 /* program countdown */
708 __raw_writel(0x6666, &regs->change_lock);
709 __raw_writel(0xbbbb, &regs->change_lock);
710 __raw_writel(1, &regs->change);
711
712 /* enable watchdog */
713 __raw_writel(0x7777, &regs->disable_lock);
714 __raw_writel(0xcccc, &regs->disable_lock);
715 __raw_writel(0xdddd, &regs->disable_lock);
716 __raw_writel(1, &regs->disable);
717
718 /* kick */
719 __raw_writel(0x5555, &regs->kick_lock);
720 __raw_writel(0xaaaa, &regs->kick_lock);
721 __raw_writel(1, &regs->kick);
722}
723
724static struct davinci_soc_info tnetv107x_soc_info = {
725 .io_desc = io_desc,
726 .io_desc_num = ARRAY_SIZE(io_desc),
727 .ids = ids,
728 .ids_num = ARRAY_SIZE(ids),
729 .jtag_id_reg = TNETV107X_CHIP_CFG_BASE + 0x018,
730 .cpu_clks = clks,
731 .psc_bases = psc_regs,
732 .psc_bases_num = ARRAY_SIZE(psc_regs),
733 .pinmux_base = TNETV107X_CHIP_CFG_BASE + 0x150,
734 .pinmux_pins = pins,
735 .pinmux_pins_num = ARRAY_SIZE(pins),
736 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
737 .intc_base = TNETV107X_INTC_BASE,
738 .intc_irq_prios = irq_prios,
739 .intc_irq_num = TNETV107X_N_CP_INTC_IRQ,
740 .intc_host_map = intc_host_map,
741 .gpio_base = TNETV107X_GPIO_BASE,
742 .gpio_type = GPIO_TYPE_TNETV107X,
743 .gpio_num = TNETV107X_N_GPIO,
744 .timer_info = &timer_info,
745 .serial_dev = &tnetv107x_serial_device,
746 .reset = tnetv107x_watchdog_reset,
747 .reset_device = &tnetv107x_wdt_device,
748};
749
750void __init tnetv107x_init(void)
751{
752 davinci_common_init(&tnetv107x_soc_info);
753}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 19:23:22 -0500