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authorMark A. Greer <mgreer@mvista.com>2009-04-15 15:40:00 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2009-05-26 11:18:09 -0400
commit673dd36f0d0cf8893d6b46d524ad80e81076b885 (patch)
tree50bd5c954e1b006c171c9effe72ac70e0a8203b4 /arch/arm/mach-davinci/irq.c
parent0e585952ac6a06b3c77d6b8eadb9c359766a700d (diff)
davinci: Move interrupt ctlr info to SoC infrastructure
Use the SoC infrastructure to hold the interrupt controller information (i.e., base address, default priorities, interrupt controller type, and the number of IRQs). The interrupt controller base, although initially put in the soc_info structure's intc_base field, is eventually put in the global 'davinci_intc_base' so the low-level interrupt code can access it without a dereference. These changes enable the SoC default irq priorities to be put in the SoC-specific files, and the interrupt controller to be at any base address. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/irq.c')
-rw-r--r--arch/arm/mach-davinci/irq.c217
1 files changed, 4 insertions, 213 deletions
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index 5a324c90e291..af92ffee8471 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -26,6 +26,7 @@
26 26
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/cputype.h> 28#include <mach/cputype.h>
29#include <mach/common.h>
29#include <asm/mach/irq.h> 30#include <asm/mach/irq.h>
30 31
31#define IRQ_BIT(irq) ((irq) & 0x1f) 32#define IRQ_BIT(irq) ((irq) & 0x1f)
@@ -41,18 +42,14 @@
41#define IRQ_INTPRI0_REG_OFFSET 0x0030 42#define IRQ_INTPRI0_REG_OFFSET 0x0030
42#define IRQ_INTPRI7_REG_OFFSET 0x004C 43#define IRQ_INTPRI7_REG_OFFSET 0x004C
43 44
44const u8 *davinci_def_priorities;
45
46#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
47
48static inline unsigned int davinci_irq_readl(int offset) 45static inline unsigned int davinci_irq_readl(int offset)
49{ 46{
50 return __raw_readl(INTC_BASE + offset); 47 return __raw_readl(davinci_intc_base + offset);
51} 48}
52 49
53static inline void davinci_irq_writel(unsigned long value, int offset) 50static inline void davinci_irq_writel(unsigned long value, int offset)
54{ 51{
55 __raw_writel(value, INTC_BASE + offset); 52 __raw_writel(value, davinci_intc_base + offset);
56} 53}
57 54
58/* Disable interrupt */ 55/* Disable interrupt */
@@ -113,217 +110,11 @@ static struct irq_chip davinci_irq_chip_0 = {
113 .unmask = davinci_unmask_irq, 110 .unmask = davinci_unmask_irq,
114}; 111};
115 112
116/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
117static const u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
118 [IRQ_VDINT0] = 2,
119 [IRQ_VDINT1] = 6,
120 [IRQ_VDINT2] = 6,
121 [IRQ_HISTINT] = 6,
122 [IRQ_H3AINT] = 6,
123 [IRQ_PRVUINT] = 6,
124 [IRQ_RSZINT] = 6,
125 [7] = 7,
126 [IRQ_VENCINT] = 6,
127 [IRQ_ASQINT] = 6,
128 [IRQ_IMXINT] = 6,
129 [IRQ_VLCDINT] = 6,
130 [IRQ_USBINT] = 4,
131 [IRQ_EMACINT] = 4,
132 [14] = 7,
133 [15] = 7,
134 [IRQ_CCINT0] = 5, /* dma */
135 [IRQ_CCERRINT] = 5, /* dma */
136 [IRQ_TCERRINT0] = 5, /* dma */
137 [IRQ_TCERRINT] = 5, /* dma */
138 [IRQ_PSCIN] = 7,
139 [21] = 7,
140 [IRQ_IDE] = 4,
141 [23] = 7,
142 [IRQ_MBXINT] = 7,
143 [IRQ_MBRINT] = 7,
144 [IRQ_MMCINT] = 7,
145 [IRQ_SDIOINT] = 7,
146 [28] = 7,
147 [IRQ_DDRINT] = 7,
148 [IRQ_AEMIFINT] = 7,
149 [IRQ_VLQINT] = 4,
150 [IRQ_TINT0_TINT12] = 2, /* clockevent */
151 [IRQ_TINT0_TINT34] = 2, /* clocksource */
152 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
153 [IRQ_TINT1_TINT34] = 7, /* system tick */
154 [IRQ_PWMINT0] = 7,
155 [IRQ_PWMINT1] = 7,
156 [IRQ_PWMINT2] = 7,
157 [IRQ_I2C] = 3,
158 [IRQ_UARTINT0] = 3,
159 [IRQ_UARTINT1] = 3,
160 [IRQ_UARTINT2] = 3,
161 [IRQ_SPINT0] = 3,
162 [IRQ_SPINT1] = 3,
163 [45] = 7,
164 [IRQ_DSP2ARM0] = 4,
165 [IRQ_DSP2ARM1] = 4,
166 [IRQ_GPIO0] = 7,
167 [IRQ_GPIO1] = 7,
168 [IRQ_GPIO2] = 7,
169 [IRQ_GPIO3] = 7,
170 [IRQ_GPIO4] = 7,
171 [IRQ_GPIO5] = 7,
172 [IRQ_GPIO6] = 7,
173 [IRQ_GPIO7] = 7,
174 [IRQ_GPIOBNK0] = 7,
175 [IRQ_GPIOBNK1] = 7,
176 [IRQ_GPIOBNK2] = 7,
177 [IRQ_GPIOBNK3] = 7,
178 [IRQ_GPIOBNK4] = 7,
179 [IRQ_COMMTX] = 7,
180 [IRQ_COMMRX] = 7,
181 [IRQ_EMUINT] = 7,
182};
183
184static const u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
185 [IRQ_DM646X_VP_VERTINT0] = 7,
186 [IRQ_DM646X_VP_VERTINT1] = 7,
187 [IRQ_DM646X_VP_VERTINT2] = 7,
188 [IRQ_DM646X_VP_VERTINT3] = 7,
189 [IRQ_DM646X_VP_ERRINT] = 7,
190 [IRQ_DM646X_RESERVED_1] = 7,
191 [IRQ_DM646X_RESERVED_2] = 7,
192 [IRQ_DM646X_WDINT] = 7,
193 [IRQ_DM646X_CRGENINT0] = 7,
194 [IRQ_DM646X_CRGENINT1] = 7,
195 [IRQ_DM646X_TSIFINT0] = 7,
196 [IRQ_DM646X_TSIFINT1] = 7,
197 [IRQ_DM646X_VDCEINT] = 7,
198 [IRQ_DM646X_USBINT] = 7,
199 [IRQ_DM646X_USBDMAINT] = 7,
200 [IRQ_DM646X_PCIINT] = 7,
201 [IRQ_CCINT0] = 7, /* dma */
202 [IRQ_CCERRINT] = 7, /* dma */
203 [IRQ_TCERRINT0] = 7, /* dma */
204 [IRQ_TCERRINT] = 7, /* dma */
205 [IRQ_DM646X_TCERRINT2] = 7,
206 [IRQ_DM646X_TCERRINT3] = 7,
207 [IRQ_DM646X_IDE] = 7,
208 [IRQ_DM646X_HPIINT] = 7,
209 [IRQ_DM646X_EMACRXTHINT] = 7,
210 [IRQ_DM646X_EMACRXINT] = 7,
211 [IRQ_DM646X_EMACTXINT] = 7,
212 [IRQ_DM646X_EMACMISCINT] = 7,
213 [IRQ_DM646X_MCASP0TXINT] = 7,
214 [IRQ_DM646X_MCASP0RXINT] = 7,
215 [IRQ_AEMIFINT] = 7,
216 [IRQ_DM646X_RESERVED_3] = 7,
217 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
218 [IRQ_TINT0_TINT34] = 7, /* clocksource */
219 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
220 [IRQ_TINT1_TINT34] = 7, /* system tick */
221 [IRQ_PWMINT0] = 7,
222 [IRQ_PWMINT1] = 7,
223 [IRQ_DM646X_VLQINT] = 7,
224 [IRQ_I2C] = 7,
225 [IRQ_UARTINT0] = 7,
226 [IRQ_UARTINT1] = 7,
227 [IRQ_DM646X_UARTINT2] = 7,
228 [IRQ_DM646X_SPINT0] = 7,
229 [IRQ_DM646X_SPINT1] = 7,
230 [IRQ_DM646X_DSP2ARMINT] = 7,
231 [IRQ_DM646X_RESERVED_4] = 7,
232 [IRQ_DM646X_PSCINT] = 7,
233 [IRQ_DM646X_GPIO0] = 7,
234 [IRQ_DM646X_GPIO1] = 7,
235 [IRQ_DM646X_GPIO2] = 7,
236 [IRQ_DM646X_GPIO3] = 7,
237 [IRQ_DM646X_GPIO4] = 7,
238 [IRQ_DM646X_GPIO5] = 7,
239 [IRQ_DM646X_GPIO6] = 7,
240 [IRQ_DM646X_GPIO7] = 7,
241 [IRQ_DM646X_GPIOBNK0] = 7,
242 [IRQ_DM646X_GPIOBNK1] = 7,
243 [IRQ_DM646X_GPIOBNK2] = 7,
244 [IRQ_DM646X_DDRINT] = 7,
245 [IRQ_DM646X_AEMIFINT] = 7,
246 [IRQ_COMMTX] = 7,
247 [IRQ_COMMRX] = 7,
248 [IRQ_EMUINT] = 7,
249};
250
251static const u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
252 [IRQ_DM355_CCDC_VDINT0] = 2,
253 [IRQ_DM355_CCDC_VDINT1] = 6,
254 [IRQ_DM355_CCDC_VDINT2] = 6,
255 [IRQ_DM355_IPIPE_HST] = 6,
256 [IRQ_DM355_H3AINT] = 6,
257 [IRQ_DM355_IPIPE_SDR] = 6,
258 [IRQ_DM355_IPIPEIFINT] = 6,
259 [IRQ_DM355_OSDINT] = 7,
260 [IRQ_DM355_VENCINT] = 6,
261 [IRQ_ASQINT] = 6,
262 [IRQ_IMXINT] = 6,
263 [IRQ_USBINT] = 4,
264 [IRQ_DM355_RTOINT] = 4,
265 [IRQ_DM355_UARTINT2] = 7,
266 [IRQ_DM355_TINT6] = 7,
267 [IRQ_CCINT0] = 5, /* dma */
268 [IRQ_CCERRINT] = 5, /* dma */
269 [IRQ_TCERRINT0] = 5, /* dma */
270 [IRQ_TCERRINT] = 5, /* dma */
271 [IRQ_DM355_SPINT2_1] = 7,
272 [IRQ_DM355_TINT7] = 4,
273 [IRQ_DM355_SDIOINT0] = 7,
274 [IRQ_MBXINT] = 7,
275 [IRQ_MBRINT] = 7,
276 [IRQ_MMCINT] = 7,
277 [IRQ_DM355_MMCINT1] = 7,
278 [IRQ_DM355_PWMINT3] = 7,
279 [IRQ_DDRINT] = 7,
280 [IRQ_AEMIFINT] = 7,
281 [IRQ_DM355_SDIOINT1] = 4,
282 [IRQ_TINT0_TINT12] = 2, /* clockevent */
283 [IRQ_TINT0_TINT34] = 2, /* clocksource */
284 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
285 [IRQ_TINT1_TINT34] = 7, /* system tick */
286 [IRQ_PWMINT0] = 7,
287 [IRQ_PWMINT1] = 7,
288 [IRQ_PWMINT2] = 7,
289 [IRQ_I2C] = 3,
290 [IRQ_UARTINT0] = 3,
291 [IRQ_UARTINT1] = 3,
292 [IRQ_DM355_SPINT0_0] = 3,
293 [IRQ_DM355_SPINT0_1] = 3,
294 [IRQ_DM355_GPIO0] = 3,
295 [IRQ_DM355_GPIO1] = 7,
296 [IRQ_DM355_GPIO2] = 4,
297 [IRQ_DM355_GPIO3] = 4,
298 [IRQ_DM355_GPIO4] = 7,
299 [IRQ_DM355_GPIO5] = 7,
300 [IRQ_DM355_GPIO6] = 7,
301 [IRQ_DM355_GPIO7] = 7,
302 [IRQ_DM355_GPIO8] = 7,
303 [IRQ_DM355_GPIO9] = 7,
304 [IRQ_DM355_GPIOBNK0] = 7,
305 [IRQ_DM355_GPIOBNK1] = 7,
306 [IRQ_DM355_GPIOBNK2] = 7,
307 [IRQ_DM355_GPIOBNK3] = 7,
308 [IRQ_DM355_GPIOBNK4] = 7,
309 [IRQ_DM355_GPIOBNK5] = 7,
310 [IRQ_DM355_GPIOBNK6] = 7,
311 [IRQ_COMMTX] = 7,
312 [IRQ_COMMRX] = 7,
313 [IRQ_EMUINT] = 7,
314};
315
316/* ARM Interrupt Controller Initialization */ 113/* ARM Interrupt Controller Initialization */
317void __init davinci_irq_init(void) 114void __init davinci_irq_init(void)
318{ 115{
319 unsigned i; 116 unsigned i;
320 117 const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
321 if (cpu_is_davinci_dm644x())
322 davinci_def_priorities = dm644x_default_priorities;
323 else if (cpu_is_davinci_dm646x())
324 davinci_def_priorities = dm646x_default_priorities;
325 else if (cpu_is_davinci_dm355())
326 davinci_def_priorities = dm355_default_priorities;
327 118
328 /* Clear all interrupt requests */ 119 /* Clear all interrupt requests */
329 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); 120 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 11:16:51 -0500