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authorSekhar Nori <nsekhar@ti.com>2009-11-16 06:51:32 -0500
committerKevin Hilman <khilman@deeprootsystems.com>2010-02-04 16:29:32 -0500
commitd2de05827cce9438dfc61d5a4cf13b6ca82ebdee (patch)
treed01e5756f23f6ffce94ae0891b9b1e7148d9d4ea /arch/arm/mach-davinci/include
parentf2a4c59df62f4493c7cf7dfd349ec66bdd4b9fec (diff)
davinci: da8xx/omapl1: add support for the second sysconfig module
OMAP-L138 adds a second SYSCFG region having useful functionality like deep sleep, pull up/down control and SATA clock stop. This patch makes provision for accessing registers from second SYSCFG region in da8xx code. Note that OMAP-L137 has a single SYSCFG region. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/include')
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h10
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 90704910d343..bddc4d4a806e 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -21,7 +21,8 @@
21#include <mach/mmc.h> 21#include <mach/mmc.h>
22#include <mach/usb.h> 22#include <mach/usb.h>
23 23
24extern void __iomem *da8xx_syscfg_base; 24extern void __iomem *da8xx_syscfg0_base;
25extern void __iomem *da8xx_syscfg1_base;
25 26
26/* 27/*
27 * The cp_intc interrupt controller for the da8xx isn't in the same 28 * The cp_intc interrupt controller for the da8xx isn't in the same
@@ -34,13 +35,16 @@ extern void __iomem *da8xx_syscfg_base;
34#define DA8XX_CP_INTC_SIZE SZ_8K 35#define DA8XX_CP_INTC_SIZE SZ_8K
35#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) 36#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
36 37
37#define DA8XX_SYSCFG_BASE (IO_PHYS + 0x14000) 38#define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
38#define DA8XX_SYSCFG_VIRT(x) (da8xx_syscfg_base + (x)) 39#define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x))
39#define DA8XX_JTAG_ID_REG 0x18 40#define DA8XX_JTAG_ID_REG 0x18
40#define DA8XX_CFGCHIP0_REG 0x17c 41#define DA8XX_CFGCHIP0_REG 0x17c
41#define DA8XX_CFGCHIP2_REG 0x184 42#define DA8XX_CFGCHIP2_REG 0x184
42#define DA8XX_CFGCHIP3_REG 0x188 43#define DA8XX_CFGCHIP3_REG 0x188
43 44
45#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000)
46#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x))
47
44#define DA8XX_PSC0_BASE 0x01c10000 48#define DA8XX_PSC0_BASE 0x01c10000
45#define DA8XX_PLL0_BASE 0x01c11000 49#define DA8XX_PLL0_BASE 0x01c11000
46#define DA8XX_TIMER64P0_BASE 0x01c20000 50#define DA8XX_TIMER64P0_BASE 0x01c20000