diff options
author | Kevin Hilman <khilman@deeprootsystems.com> | 2010-02-25 19:49:56 -0500 |
---|---|---|
committer | Kevin Hilman <khilman@deeprootsystems.com> | 2010-05-06 18:02:01 -0400 |
commit | 21ce873d211a42e315558d6ae09a8bb04508a592 (patch) | |
tree | bc409c611d9d77c61b109a97061584792753a186 /arch/arm/mach-davinci/gpio.c | |
parent | 28552c2eae472a0a52d1cdb02eb32766c7f690e1 (diff) |
davinci: sparse: gpio: void casting
Cleanup usage of void pointers when using genirq. genirq API
takes and returns void *, where this GPIO API is using those
as __iomem pointers.
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/gpio.c')
-rw-r--r-- | arch/arm/mach-davinci/gpio.c | 27 |
1 files changed, 18 insertions, 9 deletions
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 3f7706266ca6..5476ad132044 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c | |||
@@ -36,6 +36,15 @@ static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio) | |||
36 | return __gpio_to_controller(gpio); | 36 | return __gpio_to_controller(gpio); |
37 | } | 37 | } |
38 | 38 | ||
39 | static inline struct gpio_controller __iomem *irq2controller(int irq) | ||
40 | { | ||
41 | struct gpio_controller __iomem *g; | ||
42 | |||
43 | g = (__force struct gpio_controller __iomem *)get_irq_chip_data(irq); | ||
44 | |||
45 | return g; | ||
46 | } | ||
47 | |||
39 | static int __init davinci_gpio_irq_setup(void); | 48 | static int __init davinci_gpio_irq_setup(void); |
40 | 49 | ||
41 | /*--------------------------------------------------------------------------*/ | 50 | /*--------------------------------------------------------------------------*/ |
@@ -161,7 +170,7 @@ pure_initcall(davinci_gpio_setup); | |||
161 | 170 | ||
162 | static void gpio_irq_disable(unsigned irq) | 171 | static void gpio_irq_disable(unsigned irq) |
163 | { | 172 | { |
164 | struct gpio_controller __iomem *g = get_irq_chip_data(irq); | 173 | struct gpio_controller __iomem *g = irq2controller(irq); |
165 | u32 mask = (u32) get_irq_data(irq); | 174 | u32 mask = (u32) get_irq_data(irq); |
166 | 175 | ||
167 | __raw_writel(mask, &g->clr_falling); | 176 | __raw_writel(mask, &g->clr_falling); |
@@ -170,7 +179,7 @@ static void gpio_irq_disable(unsigned irq) | |||
170 | 179 | ||
171 | static void gpio_irq_enable(unsigned irq) | 180 | static void gpio_irq_enable(unsigned irq) |
172 | { | 181 | { |
173 | struct gpio_controller __iomem *g = get_irq_chip_data(irq); | 182 | struct gpio_controller __iomem *g = irq2controller(irq); |
174 | u32 mask = (u32) get_irq_data(irq); | 183 | u32 mask = (u32) get_irq_data(irq); |
175 | unsigned status = irq_desc[irq].status; | 184 | unsigned status = irq_desc[irq].status; |
176 | 185 | ||
@@ -186,7 +195,7 @@ static void gpio_irq_enable(unsigned irq) | |||
186 | 195 | ||
187 | static int gpio_irq_type(unsigned irq, unsigned trigger) | 196 | static int gpio_irq_type(unsigned irq, unsigned trigger) |
188 | { | 197 | { |
189 | struct gpio_controller __iomem *g = get_irq_chip_data(irq); | 198 | struct gpio_controller __iomem *g = irq2controller(irq); |
190 | u32 mask = (u32) get_irq_data(irq); | 199 | u32 mask = (u32) get_irq_data(irq); |
191 | 200 | ||
192 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | 201 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
@@ -215,7 +224,7 @@ static struct irq_chip gpio_irqchip = { | |||
215 | static void | 224 | static void |
216 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) | 225 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
217 | { | 226 | { |
218 | struct gpio_controller __iomem *g = get_irq_chip_data(irq); | 227 | struct gpio_controller __iomem *g = irq2controller(irq); |
219 | u32 mask = 0xffff; | 228 | u32 mask = 0xffff; |
220 | 229 | ||
221 | /* we only care about one bank */ | 230 | /* we only care about one bank */ |
@@ -276,7 +285,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |||
276 | 285 | ||
277 | static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger) | 286 | static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger) |
278 | { | 287 | { |
279 | struct gpio_controller __iomem *g = get_irq_chip_data(irq); | 288 | struct gpio_controller __iomem *g = irq2controller(irq); |
280 | u32 mask = (u32) get_irq_data(irq); | 289 | u32 mask = (u32) get_irq_data(irq); |
281 | 290 | ||
282 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | 291 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
@@ -362,7 +371,7 @@ static int __init davinci_gpio_irq_setup(void) | |||
362 | for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { | 371 | for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { |
363 | set_irq_chip(irq, &gpio_irqchip_unbanked); | 372 | set_irq_chip(irq, &gpio_irqchip_unbanked); |
364 | set_irq_data(irq, (void *) __gpio_mask(gpio)); | 373 | set_irq_data(irq, (void *) __gpio_mask(gpio)); |
365 | set_irq_chip_data(irq, g); | 374 | set_irq_chip_data(irq, (__force void *) g); |
366 | irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH; | 375 | irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH; |
367 | } | 376 | } |
368 | 377 | ||
@@ -385,12 +394,12 @@ static int __init davinci_gpio_irq_setup(void) | |||
385 | 394 | ||
386 | /* set up all irqs in this bank */ | 395 | /* set up all irqs in this bank */ |
387 | set_irq_chained_handler(bank_irq, gpio_irq_handler); | 396 | set_irq_chained_handler(bank_irq, gpio_irq_handler); |
388 | set_irq_chip_data(bank_irq, g); | 397 | set_irq_chip_data(bank_irq, (__force void *) g); |
389 | set_irq_data(bank_irq, (void *)irq); | 398 | set_irq_data(bank_irq, (void *) irq); |
390 | 399 | ||
391 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { | 400 | for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { |
392 | set_irq_chip(irq, &gpio_irqchip); | 401 | set_irq_chip(irq, &gpio_irqchip); |
393 | set_irq_chip_data(irq, g); | 402 | set_irq_chip_data(irq, (__force void *) g); |
394 | set_irq_data(irq, (void *) __gpio_mask(gpio)); | 403 | set_irq_data(irq, (void *) __gpio_mask(gpio)); |
395 | set_irq_handler(irq, handle_simple_irq); | 404 | set_irq_handler(irq, handle_simple_irq); |
396 | set_irq_flags(irq, IRQF_VALID); | 405 | set_irq_flags(irq, IRQF_VALID); |