diff options
author | Kevin Hilman <khilman@deeprootsystems.com> | 2010-02-25 18:36:38 -0500 |
---|---|---|
committer | Kevin Hilman <khilman@deeprootsystems.com> | 2010-05-06 18:02:01 -0400 |
commit | 28552c2eae472a0a52d1cdb02eb32766c7f690e1 (patch) | |
tree | b996bede5ecde42ad8b95d99b494418b1acd2a90 /arch/arm/mach-davinci/gpio.c | |
parent | 66f41d4c5c8a5deed66fdcc84509376c9a0bf9d8 (diff) |
davinci: misc cleanups from sparse
- Convert data/functions to static
- include headers for missing declarations
- pointer cleanups: struct foo *__iomem f --> struct foo __iomem *f;
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/gpio.c')
-rw-r--r-- | arch/arm/mach-davinci/gpio.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c index 744755b53236..3f7706266ca6 100644 --- a/arch/arm/mach-davinci/gpio.c +++ b/arch/arm/mach-davinci/gpio.c | |||
@@ -24,14 +24,14 @@ static DEFINE_SPINLOCK(gpio_lock); | |||
24 | 24 | ||
25 | struct davinci_gpio { | 25 | struct davinci_gpio { |
26 | struct gpio_chip chip; | 26 | struct gpio_chip chip; |
27 | struct gpio_controller *__iomem regs; | 27 | struct gpio_controller __iomem *regs; |
28 | int irq_base; | 28 | int irq_base; |
29 | }; | 29 | }; |
30 | 30 | ||
31 | static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; | 31 | static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; |
32 | 32 | ||
33 | /* create a non-inlined version */ | 33 | /* create a non-inlined version */ |
34 | static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio) | 34 | static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio) |
35 | { | 35 | { |
36 | return __gpio_to_controller(gpio); | 36 | return __gpio_to_controller(gpio); |
37 | } | 37 | } |
@@ -48,7 +48,7 @@ static int __init davinci_gpio_irq_setup(void); | |||
48 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) | 48 | static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) |
49 | { | 49 | { |
50 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); | 50 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
51 | struct gpio_controller *__iomem g = d->regs; | 51 | struct gpio_controller __iomem *g = d->regs; |
52 | u32 temp; | 52 | u32 temp; |
53 | 53 | ||
54 | spin_lock(&gpio_lock); | 54 | spin_lock(&gpio_lock); |
@@ -70,7 +70,7 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) | |||
70 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) | 70 | static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) |
71 | { | 71 | { |
72 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); | 72 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
73 | struct gpio_controller *__iomem g = d->regs; | 73 | struct gpio_controller __iomem *g = d->regs; |
74 | 74 | ||
75 | return (1 << offset) & __raw_readl(&g->in_data); | 75 | return (1 << offset) & __raw_readl(&g->in_data); |
76 | } | 76 | } |
@@ -79,7 +79,7 @@ static int | |||
79 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) | 79 | davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) |
80 | { | 80 | { |
81 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); | 81 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
82 | struct gpio_controller *__iomem g = d->regs; | 82 | struct gpio_controller __iomem *g = d->regs; |
83 | u32 temp; | 83 | u32 temp; |
84 | u32 mask = 1 << offset; | 84 | u32 mask = 1 << offset; |
85 | 85 | ||
@@ -99,7 +99,7 @@ static void | |||
99 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | 99 | davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
100 | { | 100 | { |
101 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); | 101 | struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip); |
102 | struct gpio_controller *__iomem g = d->regs; | 102 | struct gpio_controller __iomem *g = d->regs; |
103 | 103 | ||
104 | __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); | 104 | __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); |
105 | } | 105 | } |
@@ -161,7 +161,7 @@ pure_initcall(davinci_gpio_setup); | |||
161 | 161 | ||
162 | static void gpio_irq_disable(unsigned irq) | 162 | static void gpio_irq_disable(unsigned irq) |
163 | { | 163 | { |
164 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | 164 | struct gpio_controller __iomem *g = get_irq_chip_data(irq); |
165 | u32 mask = (u32) get_irq_data(irq); | 165 | u32 mask = (u32) get_irq_data(irq); |
166 | 166 | ||
167 | __raw_writel(mask, &g->clr_falling); | 167 | __raw_writel(mask, &g->clr_falling); |
@@ -170,7 +170,7 @@ static void gpio_irq_disable(unsigned irq) | |||
170 | 170 | ||
171 | static void gpio_irq_enable(unsigned irq) | 171 | static void gpio_irq_enable(unsigned irq) |
172 | { | 172 | { |
173 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | 173 | struct gpio_controller __iomem *g = get_irq_chip_data(irq); |
174 | u32 mask = (u32) get_irq_data(irq); | 174 | u32 mask = (u32) get_irq_data(irq); |
175 | unsigned status = irq_desc[irq].status; | 175 | unsigned status = irq_desc[irq].status; |
176 | 176 | ||
@@ -186,7 +186,7 @@ static void gpio_irq_enable(unsigned irq) | |||
186 | 186 | ||
187 | static int gpio_irq_type(unsigned irq, unsigned trigger) | 187 | static int gpio_irq_type(unsigned irq, unsigned trigger) |
188 | { | 188 | { |
189 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | 189 | struct gpio_controller __iomem *g = get_irq_chip_data(irq); |
190 | u32 mask = (u32) get_irq_data(irq); | 190 | u32 mask = (u32) get_irq_data(irq); |
191 | 191 | ||
192 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | 192 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
@@ -215,7 +215,7 @@ static struct irq_chip gpio_irqchip = { | |||
215 | static void | 215 | static void |
216 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) | 216 | gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
217 | { | 217 | { |
218 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | 218 | struct gpio_controller __iomem *g = get_irq_chip_data(irq); |
219 | u32 mask = 0xffff; | 219 | u32 mask = 0xffff; |
220 | 220 | ||
221 | /* we only care about one bank */ | 221 | /* we only care about one bank */ |
@@ -276,7 +276,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) | |||
276 | 276 | ||
277 | static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger) | 277 | static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger) |
278 | { | 278 | { |
279 | struct gpio_controller *__iomem g = get_irq_chip_data(irq); | 279 | struct gpio_controller __iomem *g = get_irq_chip_data(irq); |
280 | u32 mask = (u32) get_irq_data(irq); | 280 | u32 mask = (u32) get_irq_data(irq); |
281 | 281 | ||
282 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | 282 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
@@ -305,7 +305,7 @@ static int __init davinci_gpio_irq_setup(void) | |||
305 | u32 binten = 0; | 305 | u32 binten = 0; |
306 | unsigned ngpio, bank_irq; | 306 | unsigned ngpio, bank_irq; |
307 | struct davinci_soc_info *soc_info = &davinci_soc_info; | 307 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
308 | struct gpio_controller *__iomem g; | 308 | struct gpio_controller __iomem *g; |
309 | 309 | ||
310 | ngpio = soc_info->gpio_num; | 310 | ngpio = soc_info->gpio_num; |
311 | 311 | ||