diff options
author | Sudhakar Rajashekhara <sudhakar.raj@ti.com> | 2009-06-02 03:38:26 -0400 |
---|---|---|
committer | Kevin Hilman <khilman@deeprootsystems.com> | 2009-08-26 03:56:56 -0400 |
commit | 2bcb613a7919a0a6a7a00408fbfd1c8e471fe060 (patch) | |
tree | cd1eaf11d1ef0ef4571c21b5c295c5101aa6b15a /arch/arm/mach-davinci/dm646x.c | |
parent | 60902a2cb12c3c1682ee7a04ad7448ec16dc0c29 (diff) |
davinci: EDMA: add support for dm646x
Enables module clock for DM646x EDMA channel controller and transfer
controller.
Signed-off-by: Naresh Medisetty <naresh@ti.com>
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/dm646x.c')
-rw-r--r-- | arch/arm/mach-davinci/dm646x.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c index e2410738327c..19e989db6f70 100644 --- a/arch/arm/mach-davinci/dm646x.c +++ b/arch/arm/mach-davinci/dm646x.c | |||
@@ -162,6 +162,41 @@ static struct clk arm_clk = { | |||
162 | .flags = ALWAYS_ENABLED, | 162 | .flags = ALWAYS_ENABLED, |
163 | }; | 163 | }; |
164 | 164 | ||
165 | static struct clk edma_cc_clk = { | ||
166 | .name = "edma_cc", | ||
167 | .parent = &pll1_sysclk2, | ||
168 | .lpsc = DM646X_LPSC_TPCC, | ||
169 | .flags = ALWAYS_ENABLED, | ||
170 | }; | ||
171 | |||
172 | static struct clk edma_tc0_clk = { | ||
173 | .name = "edma_tc0", | ||
174 | .parent = &pll1_sysclk2, | ||
175 | .lpsc = DM646X_LPSC_TPTC0, | ||
176 | .flags = ALWAYS_ENABLED, | ||
177 | }; | ||
178 | |||
179 | static struct clk edma_tc1_clk = { | ||
180 | .name = "edma_tc1", | ||
181 | .parent = &pll1_sysclk2, | ||
182 | .lpsc = DM646X_LPSC_TPTC1, | ||
183 | .flags = ALWAYS_ENABLED, | ||
184 | }; | ||
185 | |||
186 | static struct clk edma_tc2_clk = { | ||
187 | .name = "edma_tc2", | ||
188 | .parent = &pll1_sysclk2, | ||
189 | .lpsc = DM646X_LPSC_TPTC2, | ||
190 | .flags = ALWAYS_ENABLED, | ||
191 | }; | ||
192 | |||
193 | static struct clk edma_tc3_clk = { | ||
194 | .name = "edma_tc3", | ||
195 | .parent = &pll1_sysclk2, | ||
196 | .lpsc = DM646X_LPSC_TPTC3, | ||
197 | .flags = ALWAYS_ENABLED, | ||
198 | }; | ||
199 | |||
165 | static struct clk uart0_clk = { | 200 | static struct clk uart0_clk = { |
166 | .name = "uart0", | 201 | .name = "uart0", |
167 | .parent = &aux_clkin, | 202 | .parent = &aux_clkin, |
@@ -269,6 +304,11 @@ struct davinci_clk dm646x_clks[] = { | |||
269 | CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), | 304 | CLK(NULL, "pll2_sysclk1", &pll2_sysclk1), |
270 | CLK(NULL, "dsp", &dsp_clk), | 305 | CLK(NULL, "dsp", &dsp_clk), |
271 | CLK(NULL, "arm", &arm_clk), | 306 | CLK(NULL, "arm", &arm_clk), |
307 | CLK(NULL, "edma_cc", &edma_cc_clk), | ||
308 | CLK(NULL, "edma_tc0", &edma_tc0_clk), | ||
309 | CLK(NULL, "edma_tc1", &edma_tc1_clk), | ||
310 | CLK(NULL, "edma_tc2", &edma_tc2_clk), | ||
311 | CLK(NULL, "edma_tc3", &edma_tc3_clk), | ||
272 | CLK(NULL, "uart0", &uart0_clk), | 312 | CLK(NULL, "uart0", &uart0_clk), |
273 | CLK(NULL, "uart1", &uart1_clk), | 313 | CLK(NULL, "uart1", &uart1_clk), |
274 | CLK(NULL, "uart2", &uart2_clk), | 314 | CLK(NULL, "uart2", &uart2_clk), |