davinci: dm365 gpio irq support

Support DM365 GPIOs ... primarily by handling non-banked GPIO IRQs:

 - Flag DM365 chips as using non-banked GPIO interrupts, using a
   new soc_info field.

 - Replace the gpio_to_irq() mapping logic.  This now uses some
   runtime infrastructure, keyed off that new soc_info field,
   which doesn't handle irq_to_gpio().

 - Provide a new irq_chip ... GPIO IRQs handled directly by AINTC
   still need edge triggering managed by the GPIO controller.

DM365 chips no longer falsely report 104 GPIO IRQs as they boot.

Intelligence about IRQ muxing is missing, so for the moment this
only exposes the first eight DM365 GPIOs, which are never muxed.
The next eight are muxed, half with Ethernet (which uses most of
those pins anyway).

Tested on DM355 (10 unbanked IRQs _or_ 104 banked ones) and also
on DM365 (16 unbanked ones, only 8 made available).

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>

1 files changed, 2 insertions, 1 deletions

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index e5873bc0a0fa..f02bce8eeba4 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -882,7 +882,8 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
         .timer_info             = &dm365_timer_info,
         .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
         .gpio_num               = 104,
-        .gpio_irq               = 44,
+        .gpio_irq               = IRQ_DM365_GPIO0,
+        .gpio_unbanked          = 8,    /* really 16 ... skip muxed GPIOs */
         .serial_dev             = &dm365_serial_device,
         .emac_pdata             = &dm365_emac_pdata,
         .sram_dma               = 0x00010000,