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authorRussell King <rmk+kernel@arm.linux.org.uk>2011-03-14 18:26:30 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-03-14 18:26:30 -0400
commit5821c95ffbfd368194927a4f7803125c5af8857c (patch)
tree87dccb04c93d3a7c0af704a0db07e496e76a7431 /arch/arm/mach-davinci/devices-da8xx.c
parent8688a1a8637c6b833b9b70148809db4538352d2e (diff)
parent9a9fb12a4832bdf22751e21df298ef3559643b43 (diff)
Merge branch 'davinci-next' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci into devel-stable
Diffstat (limited to 'arch/arm/mach-davinci/devices-da8xx.c')
-rw-r--r--arch/arm/mach-davinci/devices-da8xx.c125
1 files changed, 117 insertions, 8 deletions
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index beda8a4133a0..625d4b66718b 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -38,12 +38,23 @@
38#define DA8XX_EMAC_MDIO_BASE 0x01e24000 38#define DA8XX_EMAC_MDIO_BASE 0x01e24000
39#define DA8XX_GPIO_BASE 0x01e26000 39#define DA8XX_GPIO_BASE 0x01e26000
40#define DA8XX_I2C1_BASE 0x01e28000 40#define DA8XX_I2C1_BASE 0x01e28000
41#define DA8XX_SPI0_BASE 0x01c41000
42#define DA8XX_SPI1_BASE 0x01f0e000
41 43
42#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000 44#define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
43#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000 45#define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
44#define DA8XX_EMAC_RAM_OFFSET 0x0000 46#define DA8XX_EMAC_RAM_OFFSET 0x0000
45#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K 47#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
46 48
49#define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
50#define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
51#define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
52#define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
53#define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
54#define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
55#define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
56#define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
57
47void __iomem *da8xx_syscfg0_base; 58void __iomem *da8xx_syscfg0_base;
48void __iomem *da8xx_syscfg1_base; 59void __iomem *da8xx_syscfg1_base;
49 60
@@ -573,13 +584,13 @@ static struct resource da8xx_mmcsd0_resources[] = {
573 .flags = IORESOURCE_IRQ, 584 .flags = IORESOURCE_IRQ,
574 }, 585 },
575 { /* DMA RX */ 586 { /* DMA RX */
576 .start = EDMA_CTLR_CHAN(0, 16), 587 .start = DA8XX_DMA_MMCSD0_RX,
577 .end = EDMA_CTLR_CHAN(0, 16), 588 .end = DA8XX_DMA_MMCSD0_RX,
578 .flags = IORESOURCE_DMA, 589 .flags = IORESOURCE_DMA,
579 }, 590 },
580 { /* DMA TX */ 591 { /* DMA TX */
581 .start = EDMA_CTLR_CHAN(0, 17), 592 .start = DA8XX_DMA_MMCSD0_TX,
582 .end = EDMA_CTLR_CHAN(0, 17), 593 .end = DA8XX_DMA_MMCSD0_TX,
583 .flags = IORESOURCE_DMA, 594 .flags = IORESOURCE_DMA,
584 }, 595 },
585}; 596};
@@ -610,13 +621,13 @@ static struct resource da850_mmcsd1_resources[] = {
610 .flags = IORESOURCE_IRQ, 621 .flags = IORESOURCE_IRQ,
611 }, 622 },
612 { /* DMA RX */ 623 { /* DMA RX */
613 .start = EDMA_CTLR_CHAN(1, 28), 624 .start = DA850_DMA_MMCSD1_RX,
614 .end = EDMA_CTLR_CHAN(1, 28), 625 .end = DA850_DMA_MMCSD1_RX,
615 .flags = IORESOURCE_DMA, 626 .flags = IORESOURCE_DMA,
616 }, 627 },
617 { /* DMA TX */ 628 { /* DMA TX */
618 .start = EDMA_CTLR_CHAN(1, 29), 629 .start = DA850_DMA_MMCSD1_TX,
619 .end = EDMA_CTLR_CHAN(1, 29), 630 .end = DA850_DMA_MMCSD1_TX,
620 .flags = IORESOURCE_DMA, 631 .flags = IORESOURCE_DMA,
621 }, 632 },
622}; 633};
@@ -725,3 +736,101 @@ int __init da8xx_register_cpuidle(void)
725 736
726 return platform_device_register(&da8xx_cpuidle_device); 737 return platform_device_register(&da8xx_cpuidle_device);
727} 738}
739
740static struct resource da8xx_spi0_resources[] = {
741 [0] = {
742 .start = DA8XX_SPI0_BASE,
743 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
744 .flags = IORESOURCE_MEM,
745 },
746 [1] = {
747 .start = IRQ_DA8XX_SPINT0,
748 .end = IRQ_DA8XX_SPINT0,
749 .flags = IORESOURCE_IRQ,
750 },
751 [2] = {
752 .start = DA8XX_DMA_SPI0_RX,
753 .end = DA8XX_DMA_SPI0_RX,
754 .flags = IORESOURCE_DMA,
755 },
756 [3] = {
757 .start = DA8XX_DMA_SPI0_TX,
758 .end = DA8XX_DMA_SPI0_TX,
759 .flags = IORESOURCE_DMA,
760 },
761};
762
763static struct resource da8xx_spi1_resources[] = {
764 [0] = {
765 .start = DA8XX_SPI1_BASE,
766 .end = DA8XX_SPI1_BASE + SZ_4K - 1,
767 .flags = IORESOURCE_MEM,
768 },
769 [1] = {
770 .start = IRQ_DA8XX_SPINT1,
771 .end = IRQ_DA8XX_SPINT1,
772 .flags = IORESOURCE_IRQ,
773 },
774 [2] = {
775 .start = DA8XX_DMA_SPI1_RX,
776 .end = DA8XX_DMA_SPI1_RX,
777 .flags = IORESOURCE_DMA,
778 },
779 [3] = {
780 .start = DA8XX_DMA_SPI1_TX,
781 .end = DA8XX_DMA_SPI1_TX,
782 .flags = IORESOURCE_DMA,
783 },
784};
785
786struct davinci_spi_platform_data da8xx_spi_pdata[] = {
787 [0] = {
788 .version = SPI_VERSION_2,
789 .intr_line = 1,
790 .dma_event_q = EVENTQ_0,
791 },
792 [1] = {
793 .version = SPI_VERSION_2,
794 .intr_line = 1,
795 .dma_event_q = EVENTQ_0,
796 },
797};
798
799static struct platform_device da8xx_spi_device[] = {
800 [0] = {
801 .name = "spi_davinci",
802 .id = 0,
803 .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
804 .resource = da8xx_spi0_resources,
805 .dev = {
806 .platform_data = &da8xx_spi_pdata[0],
807 },
808 },
809 [1] = {
810 .name = "spi_davinci",
811 .id = 1,
812 .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
813 .resource = da8xx_spi1_resources,
814 .dev = {
815 .platform_data = &da8xx_spi_pdata[1],
816 },
817 },
818};
819
820int __init da8xx_register_spi(int instance, struct spi_board_info *info,
821 unsigned len)
822{
823 int ret;
824
825 if (instance < 0 || instance > 1)
826 return -EINVAL;
827
828 ret = spi_register_board_info(info, len);
829 if (ret)
830 pr_warning("%s: failed to register board info for spi %d :"
831 " %d\n", __func__, instance, ret);
832
833 da8xx_spi_pdata[instance].num_chipselect = len;
834
835 return platform_device_register(&da8xx_spi_device[instance]);
836}