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authorSekhar Nori <nsekhar@ti.com>2009-11-16 06:51:32 -0500
committerKevin Hilman <khilman@deeprootsystems.com>2010-02-04 16:29:32 -0500
commitd2de05827cce9438dfc61d5a4cf13b6ca82ebdee (patch)
treed01e5756f23f6ffce94ae0891b9b1e7148d9d4ea /arch/arm/mach-davinci/da850.c
parentf2a4c59df62f4493c7cf7dfd349ec66bdd4b9fec (diff)
davinci: da8xx/omapl1: add support for the second sysconfig module
OMAP-L138 adds a second SYSCFG region having useful functionality like deep sleep, pull up/down control and SATA clock stop. This patch makes provision for accessing registers from second SYSCFG region in da8xx code. Note that OMAP-L137 has a single SYSCFG region. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/da850.c')
-rw-r--r--arch/arm/mach-davinci/da850.c20
1 files changed, 12 insertions, 8 deletions
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 717806c6cef9..4f84ab4bb221 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -838,12 +838,12 @@ static void da850_set_async3_src(int pllnum)
838 } 838 }
839 } 839 }
840 840
841 v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG)); 841 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
842 if (pllnum) 842 if (pllnum)
843 v |= CFGCHIP3_ASYNC3_CLKSRC; 843 v |= CFGCHIP3_ASYNC3_CLKSRC;
844 else 844 else
845 v &= ~CFGCHIP3_ASYNC3_CLKSRC; 845 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
846 __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG)); 846 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
847} 847}
848 848
849#ifdef CONFIG_CPU_FREQ 849#ifdef CONFIG_CPU_FREQ
@@ -996,9 +996,9 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
996 postdiv = opp->postdiv; 996 postdiv = opp->postdiv;
997 997
998 /* Unlock writing to PLL registers */ 998 /* Unlock writing to PLL registers */
999 v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG)); 999 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1000 v &= ~CFGCHIP0_PLL_MASTER_LOCK; 1000 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1001 __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG)); 1001 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1002 1002
1003 ret = davinci_set_pllrate(pll, prediv, mult, postdiv); 1003 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1004 if (WARN_ON(ret)) 1004 if (WARN_ON(ret))
@@ -1053,13 +1053,17 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
1053 1053
1054void __init da850_init(void) 1054void __init da850_init(void)
1055{ 1055{
1056 da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K); 1056 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1057 if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module")) 1057 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1058 return;
1059
1060 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1061 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
1058 return; 1062 return;
1059 1063
1060 davinci_soc_info_da850.jtag_id_base = 1064 davinci_soc_info_da850.jtag_id_base =
1061 DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG); 1065 DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
1062 davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG_VIRT(0x120); 1066 davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
1063 1067
1064 davinci_common_init(&davinci_soc_info_da850); 1068 davinci_common_init(&davinci_soc_info_da850);
1065 1069