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authorMark A. Greer <mgreer@mvista.com>2009-06-03 21:36:54 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2009-08-26 03:56:59 -0400
commit55c79a40e34566e9d198f6205b0cf06e3d89ac0a (patch)
treedb18d12effb87c61cfe4d14635feb7807dd0be42 /arch/arm/mach-davinci/da830.c
parentff255c6caa389c90c68f5421f60ebfc40b68ea1b (diff)
davinci: da8xx: Add base DA830/OMAP-L137 SoC support
The da830/omap l137 is a new SoC from TI that is similar to the davinci line. Since its so similar to davinci, put the support for the da830 in the same directory as the davinci code. There are differences, however. Some of those differences prevent support for davinci and da830 platforms to work in the same kernel binary. Those differences are: 1) Different physical address for RAM. This is relevant to Makefile.boot addresses and PHYS_OFFSET. The Makefile.boot issue isn't truly a kernel issue but it means u-boot won't work with a uImage including both architectures. The PHYS_OFFSET issue is addressed by the "Allow for runtime-determined PHYS_OFFSET" patch by Lennert Buytenhek but it hasn't been accepted yet. 2) Different uart addresses. This is only an issue for the 'addruart' assembly macro when CONFIG_DEBUG_LL is enabled. Since the code in that macro is called so early (e.g., by _error_p in kernel/head.S when the processor lookup fails), we can't determine what platform the kernel is running on at runtime to use the correct uart address. These areas have compile errors intentionally inserted to indicate to the builder they're doing something wrong. A new config variable, CONFIG_ARCH_DAVINCI_DMx, is added to distinguish between a true davinci architecture and the da830 architecture. Note that the da830 currently has an issue with writeback data cache so CONFIG_CPU_DCACHE_WRITETHROUGH should be enabled when building a da830 kernel. Additional generalizations for future SoCs in the da8xx family done by Sudhakar Rajashekhara and Sekhar Nori. Signed-off-by: Steve Chen <schen@mvista.com> Signed-off-by: Mikhail Cherkashin <mcherkashin@ru.mvista.com> Signed-off-by: Mark A. Greer <mgreer@mvista.com> Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Cc: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/da830.c')
-rw-r--r--arch/arm/mach-davinci/da830.c1247
1 files changed, 1247 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
new file mode 100644
index 000000000000..ab4242869b66
--- /dev/null
+++ b/arch/arm/mach-davinci/da830.c
@@ -0,0 +1,1247 @@
1/*
2 * TI DA830/OMAP L137 chip specific setup
3 *
4 * Author: Mark A. Greer <mgreer@mvista.com>
5 *
6 * 2009 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h>
14#include <linux/platform_device.h>
15
16#include <asm/mach/map.h>
17
18#include <mach/clock.h>
19#include <mach/psc.h>
20#include <mach/mux.h>
21#include <mach/irqs.h>
22#include <mach/cputype.h>
23#include <mach/common.h>
24#include <mach/time.h>
25#include <mach/da8xx.h>
26
27#include "clock.h"
28#include "mux.h"
29
30#define DA830_PSC0_BASE 0x01c10000
31#define DA830_PLL0_BASE 0x01c11000
32#define DA830_JTAG_ID_REG 0x01c14018
33#define DA830_TIMER64P0_BASE 0x01c20000
34#define DA830_TIMER64P1_BASE 0x01c21000
35#define DA830_GPIO_BASE 0x01e26000
36#define DA830_PSC1_BASE 0x01e27000
37
38/* Offsets of the 8 compare registers on the da830 */
39#define DA830_CMP12_0 0x60
40#define DA830_CMP12_1 0x64
41#define DA830_CMP12_2 0x68
42#define DA830_CMP12_3 0x6c
43#define DA830_CMP12_4 0x70
44#define DA830_CMP12_5 0x74
45#define DA830_CMP12_6 0x78
46#define DA830_CMP12_7 0x7c
47
48#define DA830_REF_FREQ 24000000
49
50static struct pll_data pll0_data = {
51 .num = 1,
52 .phys_base = DA830_PLL0_BASE,
53 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
54};
55
56static struct clk ref_clk = {
57 .name = "ref_clk",
58 .rate = DA830_REF_FREQ,
59};
60
61static struct clk pll0_clk = {
62 .name = "pll0",
63 .parent = &ref_clk,
64 .pll_data = &pll0_data,
65 .flags = CLK_PLL,
66};
67
68static struct clk pll0_aux_clk = {
69 .name = "pll0_aux_clk",
70 .parent = &pll0_clk,
71 .flags = CLK_PLL | PRE_PLL,
72};
73
74static struct clk pll0_sysclk2 = {
75 .name = "pll0_sysclk2",
76 .parent = &pll0_clk,
77 .flags = CLK_PLL,
78 .div_reg = PLLDIV2,
79};
80
81static struct clk pll0_sysclk3 = {
82 .name = "pll0_sysclk3",
83 .parent = &pll0_clk,
84 .flags = CLK_PLL,
85 .div_reg = PLLDIV3,
86};
87
88static struct clk pll0_sysclk4 = {
89 .name = "pll0_sysclk4",
90 .parent = &pll0_clk,
91 .flags = CLK_PLL,
92 .div_reg = PLLDIV4,
93};
94
95static struct clk pll0_sysclk5 = {
96 .name = "pll0_sysclk5",
97 .parent = &pll0_clk,
98 .flags = CLK_PLL,
99 .div_reg = PLLDIV5,
100};
101
102static struct clk pll0_sysclk6 = {
103 .name = "pll0_sysclk6",
104 .parent = &pll0_clk,
105 .flags = CLK_PLL,
106 .div_reg = PLLDIV6,
107};
108
109static struct clk pll0_sysclk7 = {
110 .name = "pll0_sysclk7",
111 .parent = &pll0_clk,
112 .flags = CLK_PLL,
113 .div_reg = PLLDIV7,
114};
115
116static struct clk i2c0_clk = {
117 .name = "i2c0",
118 .parent = &pll0_aux_clk,
119};
120
121static struct clk timerp64_0_clk = {
122 .name = "timer0",
123 .parent = &pll0_aux_clk,
124};
125
126static struct clk timerp64_1_clk = {
127 .name = "timer1",
128 .parent = &pll0_aux_clk,
129};
130
131static struct clk arm_rom_clk = {
132 .name = "arm_rom",
133 .parent = &pll0_sysclk2,
134 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
135 .flags = ALWAYS_ENABLED,
136};
137
138static struct clk scr0_ss_clk = {
139 .name = "scr0_ss",
140 .parent = &pll0_sysclk2,
141 .lpsc = DA8XX_LPSC0_SCR0_SS,
142 .flags = ALWAYS_ENABLED,
143};
144
145static struct clk scr1_ss_clk = {
146 .name = "scr1_ss",
147 .parent = &pll0_sysclk2,
148 .lpsc = DA8XX_LPSC0_SCR1_SS,
149 .flags = ALWAYS_ENABLED,
150};
151
152static struct clk scr2_ss_clk = {
153 .name = "scr2_ss",
154 .parent = &pll0_sysclk2,
155 .lpsc = DA8XX_LPSC0_SCR2_SS,
156 .flags = ALWAYS_ENABLED,
157};
158
159static struct clk dmax_clk = {
160 .name = "dmax",
161 .parent = &pll0_sysclk2,
162 .lpsc = DA8XX_LPSC0_DMAX,
163 .flags = ALWAYS_ENABLED,
164};
165
166static struct clk tpcc_clk = {
167 .name = "tpcc",
168 .parent = &pll0_sysclk2,
169 .lpsc = DA8XX_LPSC0_TPCC,
170 .flags = ALWAYS_ENABLED | CLK_PSC,
171};
172
173static struct clk tptc0_clk = {
174 .name = "tptc0",
175 .parent = &pll0_sysclk2,
176 .lpsc = DA8XX_LPSC0_TPTC0,
177 .flags = ALWAYS_ENABLED,
178};
179
180static struct clk tptc1_clk = {
181 .name = "tptc1",
182 .parent = &pll0_sysclk2,
183 .lpsc = DA8XX_LPSC0_TPTC1,
184 .flags = ALWAYS_ENABLED,
185};
186
187static struct clk mmcsd_clk = {
188 .name = "mmcsd",
189 .parent = &pll0_sysclk2,
190 .lpsc = DA8XX_LPSC0_MMC_SD,
191};
192
193static struct clk uart0_clk = {
194 .name = "uart0",
195 .parent = &pll0_sysclk2,
196 .lpsc = DA8XX_LPSC0_UART0,
197};
198
199static struct clk uart1_clk = {
200 .name = "uart1",
201 .parent = &pll0_sysclk2,
202 .lpsc = DA8XX_LPSC1_UART1,
203 .psc_ctlr = 1,
204};
205
206static struct clk uart2_clk = {
207 .name = "uart2",
208 .parent = &pll0_sysclk2,
209 .lpsc = DA8XX_LPSC1_UART2,
210 .psc_ctlr = 1,
211};
212
213static struct clk spi0_clk = {
214 .name = "spi0",
215 .parent = &pll0_sysclk2,
216 .lpsc = DA8XX_LPSC0_SPI0,
217};
218
219static struct clk spi1_clk = {
220 .name = "spi1",
221 .parent = &pll0_sysclk2,
222 .lpsc = DA8XX_LPSC1_SPI1,
223 .psc_ctlr = 1,
224};
225
226static struct clk ecap0_clk = {
227 .name = "ecap0",
228 .parent = &pll0_sysclk2,
229 .lpsc = DA8XX_LPSC1_ECAP,
230 .psc_ctlr = 1,
231};
232
233static struct clk ecap1_clk = {
234 .name = "ecap1",
235 .parent = &pll0_sysclk2,
236 .lpsc = DA8XX_LPSC1_ECAP,
237 .psc_ctlr = 1,
238};
239
240static struct clk ecap2_clk = {
241 .name = "ecap2",
242 .parent = &pll0_sysclk2,
243 .lpsc = DA8XX_LPSC1_ECAP,
244 .psc_ctlr = 1,
245};
246
247static struct clk pwm0_clk = {
248 .name = "pwm0",
249 .parent = &pll0_sysclk2,
250 .lpsc = DA8XX_LPSC1_PWM,
251 .psc_ctlr = 1,
252};
253
254static struct clk pwm1_clk = {
255 .name = "pwm1",
256 .parent = &pll0_sysclk2,
257 .lpsc = DA8XX_LPSC1_PWM,
258 .psc_ctlr = 1,
259};
260
261static struct clk pwm2_clk = {
262 .name = "pwm2",
263 .parent = &pll0_sysclk2,
264 .lpsc = DA8XX_LPSC1_PWM,
265 .psc_ctlr = 1,
266};
267
268static struct clk eqep0_clk = {
269 .name = "eqep0",
270 .parent = &pll0_sysclk2,
271 .lpsc = DA830_LPSC1_EQEP,
272 .psc_ctlr = 1,
273};
274
275static struct clk eqep1_clk = {
276 .name = "eqep1",
277 .parent = &pll0_sysclk2,
278 .lpsc = DA830_LPSC1_EQEP,
279 .psc_ctlr = 1,
280};
281
282static struct clk lcdc_clk = {
283 .name = "lcdc",
284 .parent = &pll0_sysclk2,
285 .lpsc = DA8XX_LPSC1_LCDC,
286 .psc_ctlr = 1,
287};
288
289static struct clk mcasp0_clk = {
290 .name = "mcasp0",
291 .parent = &pll0_sysclk2,
292 .lpsc = DA8XX_LPSC1_McASP0,
293 .psc_ctlr = 1,
294};
295
296static struct clk mcasp1_clk = {
297 .name = "mcasp1",
298 .parent = &pll0_sysclk2,
299 .lpsc = DA830_LPSC1_McASP1,
300 .psc_ctlr = 1,
301};
302
303static struct clk mcasp2_clk = {
304 .name = "mcasp2",
305 .parent = &pll0_sysclk2,
306 .lpsc = DA830_LPSC1_McASP2,
307 .psc_ctlr = 1,
308};
309
310static struct clk usb20_clk = {
311 .name = "usb20",
312 .parent = &pll0_sysclk2,
313 .lpsc = DA8XX_LPSC1_USB20,
314 .psc_ctlr = 1,
315};
316
317static struct clk aemif_clk = {
318 .name = "aemif",
319 .parent = &pll0_sysclk3,
320 .lpsc = DA8XX_LPSC0_EMIF25,
321 .flags = ALWAYS_ENABLED,
322};
323
324static struct clk aintc_clk = {
325 .name = "aintc",
326 .parent = &pll0_sysclk4,
327 .lpsc = DA8XX_LPSC0_AINTC,
328 .flags = ALWAYS_ENABLED,
329};
330
331static struct clk secu_mgr_clk = {
332 .name = "secu_mgr",
333 .parent = &pll0_sysclk4,
334 .lpsc = DA8XX_LPSC0_SECU_MGR,
335 .flags = ALWAYS_ENABLED,
336};
337
338static struct clk emac_clk = {
339 .name = "emac",
340 .parent = &pll0_sysclk4,
341 .lpsc = DA8XX_LPSC1_CPGMAC,
342 .psc_ctlr = 1,
343};
344
345static struct clk gpio_clk = {
346 .name = "gpio",
347 .parent = &pll0_sysclk4,
348 .lpsc = DA8XX_LPSC1_GPIO,
349 .psc_ctlr = 1,
350};
351
352static struct clk i2c1_clk = {
353 .name = "i2c1",
354 .parent = &pll0_sysclk4,
355 .lpsc = DA8XX_LPSC1_I2C,
356 .psc_ctlr = 1,
357};
358
359static struct clk usb11_clk = {
360 .name = "usb11",
361 .parent = &pll0_sysclk4,
362 .lpsc = DA8XX_LPSC1_USB11,
363 .psc_ctlr = 1,
364};
365
366static struct clk emif3_clk = {
367 .name = "emif3",
368 .parent = &pll0_sysclk5,
369 .lpsc = DA8XX_LPSC1_EMIF3C,
370 .flags = ALWAYS_ENABLED,
371 .psc_ctlr = 1,
372};
373
374static struct clk arm_clk = {
375 .name = "arm",
376 .parent = &pll0_sysclk6,
377 .lpsc = DA8XX_LPSC0_ARM,
378 .flags = ALWAYS_ENABLED,
379};
380
381static struct clk rmii_clk = {
382 .name = "rmii",
383 .parent = &pll0_sysclk7,
384};
385
386static struct davinci_clk da830_clks[] = {
387 CLK(NULL, "ref", &ref_clk),
388 CLK(NULL, "pll0", &pll0_clk),
389 CLK(NULL, "pll0_aux", &pll0_aux_clk),
390 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
391 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
392 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
393 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
394 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
395 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
396 CLK("i2c_davinci.1", NULL, &i2c0_clk),
397 CLK(NULL, "timer0", &timerp64_0_clk),
398 CLK("watchdog", NULL, &timerp64_1_clk),
399 CLK(NULL, "arm_rom", &arm_rom_clk),
400 CLK(NULL, "scr0_ss", &scr0_ss_clk),
401 CLK(NULL, "scr1_ss", &scr1_ss_clk),
402 CLK(NULL, "scr2_ss", &scr2_ss_clk),
403 CLK(NULL, "dmax", &dmax_clk),
404 CLK(NULL, "tpcc", &tpcc_clk),
405 CLK(NULL, "tptc0", &tptc0_clk),
406 CLK(NULL, "tptc1", &tptc1_clk),
407 CLK("davinci_mmc.0", NULL, &mmcsd_clk),
408 CLK(NULL, "uart0", &uart0_clk),
409 CLK(NULL, "uart1", &uart1_clk),
410 CLK(NULL, "uart2", &uart2_clk),
411 CLK("dm_spi.0", NULL, &spi0_clk),
412 CLK("dm_spi.1", NULL, &spi1_clk),
413 CLK(NULL, "ecap0", &ecap0_clk),
414 CLK(NULL, "ecap1", &ecap1_clk),
415 CLK(NULL, "ecap2", &ecap2_clk),
416 CLK(NULL, "pwm0", &pwm0_clk),
417 CLK(NULL, "pwm1", &pwm1_clk),
418 CLK(NULL, "pwm2", &pwm2_clk),
419 CLK("eqep.0", NULL, &eqep0_clk),
420 CLK("eqep.1", NULL, &eqep1_clk),
421 CLK("da830_lcdc", NULL, &lcdc_clk),
422 CLK("soc-audio.0", NULL, &mcasp0_clk),
423 CLK("soc-audio.1", NULL, &mcasp1_clk),
424 CLK("soc-audio.2", NULL, &mcasp2_clk),
425 CLK("musb_hdrc", NULL, &usb20_clk),
426 CLK(NULL, "aemif", &aemif_clk),
427 CLK(NULL, "aintc", &aintc_clk),
428 CLK(NULL, "secu_mgr", &secu_mgr_clk),
429 CLK("davinci_emac.1", NULL, &emac_clk),
430 CLK(NULL, "gpio", &gpio_clk),
431 CLK("i2c_davinci.2", NULL, &i2c1_clk),
432 CLK(NULL, "usb11", &usb11_clk),
433 CLK(NULL, "emif3", &emif3_clk),
434 CLK(NULL, "arm", &arm_clk),
435 CLK(NULL, "rmii", &rmii_clk),
436 CLK(NULL, NULL, NULL),
437};
438
439#define PINMUX0 0x00
440#define PINMUX1 0x04
441#define PINMUX2 0x08
442#define PINMUX3 0x0c
443#define PINMUX4 0x10
444#define PINMUX5 0x14
445#define PINMUX6 0x18
446#define PINMUX7 0x1c
447#define PINMUX8 0x20
448#define PINMUX9 0x24
449#define PINMUX10 0x28
450#define PINMUX11 0x2c
451#define PINMUX12 0x30
452#define PINMUX13 0x34
453#define PINMUX14 0x38
454#define PINMUX15 0x3c
455#define PINMUX16 0x40
456#define PINMUX17 0x44
457#define PINMUX18 0x48
458#define PINMUX19 0x4c
459
460/*
461 * Device specific mux setup
462 *
463 * soc description mux mode mode mux dbg
464 * reg offset mask mode
465 */
466static const struct mux_config da830_pins[] = {
467#ifdef CONFIG_DAVINCI_MUX
468 MUX_CFG(DA830, GPIO7_14, 0, 0, 0xf, 1, false)
469 MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false)
470 MUX_CFG(DA830, GPIO7_15, 0, 4, 0xf, 1, false)
471 MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false)
472 MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false)
473 MUX_CFG(DA830, EMB_CLK_GLUE, 0, 12, 0xf, 1, false)
474 MUX_CFG(DA830, EMB_CLK, 0, 12, 0xf, 2, false)
475 MUX_CFG(DA830, NEMB_CS_0, 0, 16, 0xf, 1, false)
476 MUX_CFG(DA830, NEMB_CAS, 0, 20, 0xf, 1, false)
477 MUX_CFG(DA830, NEMB_RAS, 0, 24, 0xf, 1, false)
478 MUX_CFG(DA830, NEMB_WE, 0, 28, 0xf, 1, false)
479 MUX_CFG(DA830, EMB_BA_1, 1, 0, 0xf, 1, false)
480 MUX_CFG(DA830, EMB_BA_0, 1, 4, 0xf, 1, false)
481 MUX_CFG(DA830, EMB_A_0, 1, 8, 0xf, 1, false)
482 MUX_CFG(DA830, EMB_A_1, 1, 12, 0xf, 1, false)
483 MUX_CFG(DA830, EMB_A_2, 1, 16, 0xf, 1, false)
484 MUX_CFG(DA830, EMB_A_3, 1, 20, 0xf, 1, false)
485 MUX_CFG(DA830, EMB_A_4, 1, 24, 0xf, 1, false)
486 MUX_CFG(DA830, EMB_A_5, 1, 28, 0xf, 1, false)
487 MUX_CFG(DA830, GPIO7_0, 1, 0, 0xf, 8, false)
488 MUX_CFG(DA830, GPIO7_1, 1, 4, 0xf, 8, false)
489 MUX_CFG(DA830, GPIO7_2, 1, 8, 0xf, 8, false)
490 MUX_CFG(DA830, GPIO7_3, 1, 12, 0xf, 8, false)
491 MUX_CFG(DA830, GPIO7_4, 1, 16, 0xf, 8, false)
492 MUX_CFG(DA830, GPIO7_5, 1, 20, 0xf, 8, false)
493 MUX_CFG(DA830, GPIO7_6, 1, 24, 0xf, 8, false)
494 MUX_CFG(DA830, GPIO7_7, 1, 28, 0xf, 8, false)
495 MUX_CFG(DA830, EMB_A_6, 2, 0, 0xf, 1, false)
496 MUX_CFG(DA830, EMB_A_7, 2, 4, 0xf, 1, false)
497 MUX_CFG(DA830, EMB_A_8, 2, 8, 0xf, 1, false)
498 MUX_CFG(DA830, EMB_A_9, 2, 12, 0xf, 1, false)
499 MUX_CFG(DA830, EMB_A_10, 2, 16, 0xf, 1, false)
500 MUX_CFG(DA830, EMB_A_11, 2, 20, 0xf, 1, false)
501 MUX_CFG(DA830, EMB_A_12, 2, 24, 0xf, 1, false)
502 MUX_CFG(DA830, EMB_D_31, 2, 28, 0xf, 1, false)
503 MUX_CFG(DA830, GPIO7_8, 2, 0, 0xf, 8, false)
504 MUX_CFG(DA830, GPIO7_9, 2, 4, 0xf, 8, false)
505 MUX_CFG(DA830, GPIO7_10, 2, 8, 0xf, 8, false)
506 MUX_CFG(DA830, GPIO7_11, 2, 12, 0xf, 8, false)
507 MUX_CFG(DA830, GPIO7_12, 2, 16, 0xf, 8, false)
508 MUX_CFG(DA830, GPIO7_13, 2, 20, 0xf, 8, false)
509 MUX_CFG(DA830, GPIO3_13, 2, 24, 0xf, 8, false)
510 MUX_CFG(DA830, EMB_D_30, 3, 0, 0xf, 1, false)
511 MUX_CFG(DA830, EMB_D_29, 3, 4, 0xf, 1, false)
512 MUX_CFG(DA830, EMB_D_28, 3, 8, 0xf, 1, false)
513 MUX_CFG(DA830, EMB_D_27, 3, 12, 0xf, 1, false)
514 MUX_CFG(DA830, EMB_D_26, 3, 16, 0xf, 1, false)
515 MUX_CFG(DA830, EMB_D_25, 3, 20, 0xf, 1, false)
516 MUX_CFG(DA830, EMB_D_24, 3, 24, 0xf, 1, false)
517 MUX_CFG(DA830, EMB_D_23, 3, 28, 0xf, 1, false)
518 MUX_CFG(DA830, EMB_D_22, 4, 0, 0xf, 1, false)
519 MUX_CFG(DA830, EMB_D_21, 4, 4, 0xf, 1, false)
520 MUX_CFG(DA830, EMB_D_20, 4, 8, 0xf, 1, false)
521 MUX_CFG(DA830, EMB_D_19, 4, 12, 0xf, 1, false)
522 MUX_CFG(DA830, EMB_D_18, 4, 16, 0xf, 1, false)
523 MUX_CFG(DA830, EMB_D_17, 4, 20, 0xf, 1, false)
524 MUX_CFG(DA830, EMB_D_16, 4, 24, 0xf, 1, false)
525 MUX_CFG(DA830, NEMB_WE_DQM_3, 4, 28, 0xf, 1, false)
526 MUX_CFG(DA830, NEMB_WE_DQM_2, 5, 0, 0xf, 1, false)
527 MUX_CFG(DA830, EMB_D_0, 5, 4, 0xf, 1, false)
528 MUX_CFG(DA830, EMB_D_1, 5, 8, 0xf, 1, false)
529 MUX_CFG(DA830, EMB_D_2, 5, 12, 0xf, 1, false)
530 MUX_CFG(DA830, EMB_D_3, 5, 16, 0xf, 1, false)
531 MUX_CFG(DA830, EMB_D_4, 5, 20, 0xf, 1, false)
532 MUX_CFG(DA830, EMB_D_5, 5, 24, 0xf, 1, false)
533 MUX_CFG(DA830, EMB_D_6, 5, 28, 0xf, 1, false)
534 MUX_CFG(DA830, GPIO6_0, 5, 4, 0xf, 8, false)
535 MUX_CFG(DA830, GPIO6_1, 5, 8, 0xf, 8, false)
536 MUX_CFG(DA830, GPIO6_2, 5, 12, 0xf, 8, false)
537 MUX_CFG(DA830, GPIO6_3, 5, 16, 0xf, 8, false)
538 MUX_CFG(DA830, GPIO6_4, 5, 20, 0xf, 8, false)
539 MUX_CFG(DA830, GPIO6_5, 5, 24, 0xf, 8, false)
540 MUX_CFG(DA830, GPIO6_6, 5, 28, 0xf, 8, false)
541 MUX_CFG(DA830, EMB_D_7, 6, 0, 0xf, 1, false)
542 MUX_CFG(DA830, EMB_D_8, 6, 4, 0xf, 1, false)
543 MUX_CFG(DA830, EMB_D_9, 6, 8, 0xf, 1, false)
544 MUX_CFG(DA830, EMB_D_10, 6, 12, 0xf, 1, false)
545 MUX_CFG(DA830, EMB_D_11, 6, 16, 0xf, 1, false)
546 MUX_CFG(DA830, EMB_D_12, 6, 20, 0xf, 1, false)
547 MUX_CFG(DA830, EMB_D_13, 6, 24, 0xf, 1, false)
548 MUX_CFG(DA830, EMB_D_14, 6, 28, 0xf, 1, false)
549 MUX_CFG(DA830, GPIO6_7, 6, 0, 0xf, 8, false)
550 MUX_CFG(DA830, GPIO6_8, 6, 4, 0xf, 8, false)
551 MUX_CFG(DA830, GPIO6_9, 6, 8, 0xf, 8, false)
552 MUX_CFG(DA830, GPIO6_10, 6, 12, 0xf, 8, false)
553 MUX_CFG(DA830, GPIO6_11, 6, 16, 0xf, 8, false)
554 MUX_CFG(DA830, GPIO6_12, 6, 20, 0xf, 8, false)
555 MUX_CFG(DA830, GPIO6_13, 6, 24, 0xf, 8, false)
556 MUX_CFG(DA830, GPIO6_14, 6, 28, 0xf, 8, false)
557 MUX_CFG(DA830, EMB_D_15, 7, 0, 0xf, 1, false)
558 MUX_CFG(DA830, NEMB_WE_DQM_1, 7, 4, 0xf, 1, false)
559 MUX_CFG(DA830, NEMB_WE_DQM_0, 7, 8, 0xf, 1, false)
560 MUX_CFG(DA830, SPI0_SOMI_0, 7, 12, 0xf, 1, false)
561 MUX_CFG(DA830, SPI0_SIMO_0, 7, 16, 0xf, 1, false)
562 MUX_CFG(DA830, SPI0_CLK, 7, 20, 0xf, 1, false)
563 MUX_CFG(DA830, NSPI0_ENA, 7, 24, 0xf, 1, false)
564 MUX_CFG(DA830, NSPI0_SCS_0, 7, 28, 0xf, 1, false)
565 MUX_CFG(DA830, EQEP0I, 7, 12, 0xf, 2, false)
566 MUX_CFG(DA830, EQEP0S, 7, 16, 0xf, 2, false)
567 MUX_CFG(DA830, EQEP1I, 7, 20, 0xf, 2, false)
568 MUX_CFG(DA830, NUART0_CTS, 7, 24, 0xf, 2, false)
569 MUX_CFG(DA830, NUART0_RTS, 7, 28, 0xf, 2, false)
570 MUX_CFG(DA830, EQEP0A, 7, 24, 0xf, 4, false)
571 MUX_CFG(DA830, EQEP0B, 7, 28, 0xf, 4, false)
572 MUX_CFG(DA830, GPIO6_15, 7, 0, 0xf, 8, false)
573 MUX_CFG(DA830, GPIO5_14, 7, 4, 0xf, 8, false)
574 MUX_CFG(DA830, GPIO5_15, 7, 8, 0xf, 8, false)
575 MUX_CFG(DA830, GPIO5_0, 7, 12, 0xf, 8, false)
576 MUX_CFG(DA830, GPIO5_1, 7, 16, 0xf, 8, false)
577 MUX_CFG(DA830, GPIO5_2, 7, 20, 0xf, 8, false)
578 MUX_CFG(DA830, GPIO5_3, 7, 24, 0xf, 8, false)
579 MUX_CFG(DA830, GPIO5_4, 7, 28, 0xf, 8, false)
580 MUX_CFG(DA830, SPI1_SOMI_0, 8, 0, 0xf, 1, false)
581 MUX_CFG(DA830, SPI1_SIMO_0, 8, 4, 0xf, 1, false)
582 MUX_CFG(DA830, SPI1_CLK, 8, 8, 0xf, 1, false)
583 MUX_CFG(DA830, UART0_RXD, 8, 12, 0xf, 1, false)
584 MUX_CFG(DA830, UART0_TXD, 8, 16, 0xf, 1, false)
585 MUX_CFG(DA830, AXR1_10, 8, 20, 0xf, 1, false)
586 MUX_CFG(DA830, AXR1_11, 8, 24, 0xf, 1, false)
587 MUX_CFG(DA830, NSPI1_ENA, 8, 28, 0xf, 1, false)
588 MUX_CFG(DA830, I2C1_SCL, 8, 0, 0xf, 2, false)
589 MUX_CFG(DA830, I2C1_SDA, 8, 4, 0xf, 2, false)
590 MUX_CFG(DA830, EQEP1S, 8, 8, 0xf, 2, false)
591 MUX_CFG(DA830, I2C0_SDA, 8, 12, 0xf, 2, false)
592 MUX_CFG(DA830, I2C0_SCL, 8, 16, 0xf, 2, false)
593 MUX_CFG(DA830, UART2_RXD, 8, 28, 0xf, 2, false)
594 MUX_CFG(DA830, TM64P0_IN12, 8, 12, 0xf, 4, false)
595 MUX_CFG(DA830, TM64P0_OUT12, 8, 16, 0xf, 4, false)
596 MUX_CFG(DA830, GPIO5_5, 8, 0, 0xf, 8, false)
597 MUX_CFG(DA830, GPIO5_6, 8, 4, 0xf, 8, false)
598 MUX_CFG(DA830, GPIO5_7, 8, 8, 0xf, 8, false)
599 MUX_CFG(DA830, GPIO5_8, 8, 12, 0xf, 8, false)
600 MUX_CFG(DA830, GPIO5_9, 8, 16, 0xf, 8, false)
601 MUX_CFG(DA830, GPIO5_10, 8, 20, 0xf, 8, false)
602 MUX_CFG(DA830, GPIO5_11, 8, 24, 0xf, 8, false)
603 MUX_CFG(DA830, GPIO5_12, 8, 28, 0xf, 8, false)
604 MUX_CFG(DA830, NSPI1_SCS_0, 9, 0, 0xf, 1, false)
605 MUX_CFG(DA830, USB0_DRVVBUS, 9, 4, 0xf, 1, false)
606 MUX_CFG(DA830, AHCLKX0, 9, 8, 0xf, 1, false)
607 MUX_CFG(DA830, ACLKX0, 9, 12, 0xf, 1, false)
608 MUX_CFG(DA830, AFSX0, 9, 16, 0xf, 1, false)
609 MUX_CFG(DA830, AHCLKR0, 9, 20, 0xf, 1, false)
610 MUX_CFG(DA830, ACLKR0, 9, 24, 0xf, 1, false)
611 MUX_CFG(DA830, AFSR0, 9, 28, 0xf, 1, false)
612 MUX_CFG(DA830, UART2_TXD, 9, 0, 0xf, 2, false)
613 MUX_CFG(DA830, AHCLKX2, 9, 8, 0xf, 2, false)
614 MUX_CFG(DA830, ECAP0_APWM0, 9, 12, 0xf, 2, false)
615 MUX_CFG(DA830, RMII_MHZ_50_CLK, 9, 20, 0xf, 2, false)
616 MUX_CFG(DA830, ECAP1_APWM1, 9, 24, 0xf, 2, false)
617 MUX_CFG(DA830, USB_REFCLKIN, 9, 8, 0xf, 4, false)
618 MUX_CFG(DA830, GPIO5_13, 9, 0, 0xf, 8, false)
619 MUX_CFG(DA830, GPIO4_15, 9, 4, 0xf, 8, false)
620 MUX_CFG(DA830, GPIO2_11, 9, 8, 0xf, 8, false)
621 MUX_CFG(DA830, GPIO2_12, 9, 12, 0xf, 8, false)
622 MUX_CFG(DA830, GPIO2_13, 9, 16, 0xf, 8, false)
623 MUX_CFG(DA830, GPIO2_14, 9, 20, 0xf, 8, false)
624 MUX_CFG(DA830, GPIO2_15, 9, 24, 0xf, 8, false)
625 MUX_CFG(DA830, GPIO3_12, 9, 28, 0xf, 8, false)
626 MUX_CFG(DA830, AMUTE0, 10, 0, 0xf, 1, false)
627 MUX_CFG(DA830, AXR0_0, 10, 4, 0xf, 1, false)
628 MUX_CFG(DA830, AXR0_1, 10, 8, 0xf, 1, false)
629 MUX_CFG(DA830, AXR0_2, 10, 12, 0xf, 1, false)
630 MUX_CFG(DA830, AXR0_3, 10, 16, 0xf, 1, false)
631 MUX_CFG(DA830, AXR0_4, 10, 20, 0xf, 1, false)
632 MUX_CFG(DA830, AXR0_5, 10, 24, 0xf, 1, false)
633 MUX_CFG(DA830, AXR0_6, 10, 28, 0xf, 1, false)
634 MUX_CFG(DA830, RMII_TXD_0, 10, 4, 0xf, 2, false)
635 MUX_CFG(DA830, RMII_TXD_1, 10, 8, 0xf, 2, false)
636 MUX_CFG(DA830, RMII_TXEN, 10, 12, 0xf, 2, false)
637 MUX_CFG(DA830, RMII_CRS_DV, 10, 16, 0xf, 2, false)
638 MUX_CFG(DA830, RMII_RXD_0, 10, 20, 0xf, 2, false)
639 MUX_CFG(DA830, RMII_RXD_1, 10, 24, 0xf, 2, false)
640 MUX_CFG(DA830, RMII_RXER, 10, 28, 0xf, 2, false)
641 MUX_CFG(DA830, AFSR2, 10, 4, 0xf, 4, false)
642 MUX_CFG(DA830, ACLKX2, 10, 8, 0xf, 4, false)
643 MUX_CFG(DA830, AXR2_3, 10, 12, 0xf, 4, false)
644 MUX_CFG(DA830, AXR2_2, 10, 16, 0xf, 4, false)
645 MUX_CFG(DA830, AXR2_1, 10, 20, 0xf, 4, false)
646 MUX_CFG(DA830, AFSX2, 10, 24, 0xf, 4, false)
647 MUX_CFG(DA830, ACLKR2, 10, 28, 0xf, 4, false)
648 MUX_CFG(DA830, NRESETOUT, 10, 0, 0xf, 8, false)
649 MUX_CFG(DA830, GPIO3_0, 10, 4, 0xf, 8, false)
650 MUX_CFG(DA830, GPIO3_1, 10, 8, 0xf, 8, false)
651 MUX_CFG(DA830, GPIO3_2, 10, 12, 0xf, 8, false)
652 MUX_CFG(DA830, GPIO3_3, 10, 16, 0xf, 8, false)
653 MUX_CFG(DA830, GPIO3_4, 10, 20, 0xf, 8, false)
654 MUX_CFG(DA830, GPIO3_5, 10, 24, 0xf, 8, false)
655 MUX_CFG(DA830, GPIO3_6, 10, 28, 0xf, 8, false)
656 MUX_CFG(DA830, AXR0_7, 11, 0, 0xf, 1, false)
657 MUX_CFG(DA830, AXR0_8, 11, 4, 0xf, 1, false)
658 MUX_CFG(DA830, UART1_RXD, 11, 8, 0xf, 1, false)
659 MUX_CFG(DA830, UART1_TXD, 11, 12, 0xf, 1, false)
660 MUX_CFG(DA830, AXR0_11, 11, 16, 0xf, 1, false)
661 MUX_CFG(DA830, AHCLKX1, 11, 20, 0xf, 1, false)
662 MUX_CFG(DA830, ACLKX1, 11, 24, 0xf, 1, false)
663 MUX_CFG(DA830, AFSX1, 11, 28, 0xf, 1, false)
664 MUX_CFG(DA830, MDIO_CLK, 11, 0, 0xf, 2, false)
665 MUX_CFG(DA830, MDIO_D, 11, 4, 0xf, 2, false)
666 MUX_CFG(DA830, AXR0_9, 11, 8, 0xf, 2, false)
667 MUX_CFG(DA830, AXR0_10, 11, 12, 0xf, 2, false)
668 MUX_CFG(DA830, EPWM0B, 11, 20, 0xf, 2, false)
669 MUX_CFG(DA830, EPWM0A, 11, 24, 0xf, 2, false)
670 MUX_CFG(DA830, EPWMSYNCI, 11, 28, 0xf, 2, false)
671 MUX_CFG(DA830, AXR2_0, 11, 16, 0xf, 4, false)
672 MUX_CFG(DA830, EPWMSYNC0, 11, 28, 0xf, 4, false)
673 MUX_CFG(DA830, GPIO3_7, 11, 0, 0xf, 8, false)
674 MUX_CFG(DA830, GPIO3_8, 11, 4, 0xf, 8, false)
675 MUX_CFG(DA830, GPIO3_9, 11, 8, 0xf, 8, false)
676 MUX_CFG(DA830, GPIO3_10, 11, 12, 0xf, 8, false)
677 MUX_CFG(DA830, GPIO3_11, 11, 16, 0xf, 8, false)
678 MUX_CFG(DA830, GPIO3_14, 11, 20, 0xf, 8, false)
679 MUX_CFG(DA830, GPIO3_15, 11, 24, 0xf, 8, false)
680 MUX_CFG(DA830, GPIO4_10, 11, 28, 0xf, 8, false)
681 MUX_CFG(DA830, AHCLKR1, 12, 0, 0xf, 1, false)
682 MUX_CFG(DA830, ACLKR1, 12, 4, 0xf, 1, false)
683 MUX_CFG(DA830, AFSR1, 12, 8, 0xf, 1, false)
684 MUX_CFG(DA830, AMUTE1, 12, 12, 0xf, 1, false)
685 MUX_CFG(DA830, AXR1_0, 12, 16, 0xf, 1, false)
686 MUX_CFG(DA830, AXR1_1, 12, 20, 0xf, 1, false)
687 MUX_CFG(DA830, AXR1_2, 12, 24, 0xf, 1, false)
688 MUX_CFG(DA830, AXR1_3, 12, 28, 0xf, 1, false)
689 MUX_CFG(DA830, ECAP2_APWM2, 12, 4, 0xf, 2, false)
690 MUX_CFG(DA830, EHRPWMGLUETZ, 12, 12, 0xf, 2, false)
691 MUX_CFG(DA830, EQEP1A, 12, 28, 0xf, 2, false)
692 MUX_CFG(DA830, GPIO4_11, 12, 0, 0xf, 8, false)
693 MUX_CFG(DA830, GPIO4_12, 12, 4, 0xf, 8, false)
694 MUX_CFG(DA830, GPIO4_13, 12, 8, 0xf, 8, false)
695 MUX_CFG(DA830, GPIO4_14, 12, 12, 0xf, 8, false)
696 MUX_CFG(DA830, GPIO4_0, 12, 16, 0xf, 8, false)
697 MUX_CFG(DA830, GPIO4_1, 12, 20, 0xf, 8, false)
698 MUX_CFG(DA830, GPIO4_2, 12, 24, 0xf, 8, false)
699 MUX_CFG(DA830, GPIO4_3, 12, 28, 0xf, 8, false)
700 MUX_CFG(DA830, AXR1_4, 13, 0, 0xf, 1, false)
701 MUX_CFG(DA830, AXR1_5, 13, 4, 0xf, 1, false)
702 MUX_CFG(DA830, AXR1_6, 13, 8, 0xf, 1, false)
703 MUX_CFG(DA830, AXR1_7, 13, 12, 0xf, 1, false)
704 MUX_CFG(DA830, AXR1_8, 13, 16, 0xf, 1, false)
705 MUX_CFG(DA830, AXR1_9, 13, 20, 0xf, 1, false)
706 MUX_CFG(DA830, EMA_D_0, 13, 24, 0xf, 1, false)
707 MUX_CFG(DA830, EMA_D_1, 13, 28, 0xf, 1, false)
708 MUX_CFG(DA830, EQEP1B, 13, 0, 0xf, 2, false)
709 MUX_CFG(DA830, EPWM2B, 13, 4, 0xf, 2, false)
710 MUX_CFG(DA830, EPWM2A, 13, 8, 0xf, 2, false)
711 MUX_CFG(DA830, EPWM1B, 13, 12, 0xf, 2, false)
712 MUX_CFG(DA830, EPWM1A, 13, 16, 0xf, 2, false)
713 MUX_CFG(DA830, MMCSD_DAT_0, 13, 24, 0xf, 2, false)
714 MUX_CFG(DA830, MMCSD_DAT_1, 13, 28, 0xf, 2, false)
715 MUX_CFG(DA830, UHPI_HD_0, 13, 24, 0xf, 4, false)
716 MUX_CFG(DA830, UHPI_HD_1, 13, 28, 0xf, 4, false)
717 MUX_CFG(DA830, GPIO4_4, 13, 0, 0xf, 8, false)
718 MUX_CFG(DA830, GPIO4_5, 13, 4, 0xf, 8, false)
719 MUX_CFG(DA830, GPIO4_6, 13, 8, 0xf, 8, false)
720 MUX_CFG(DA830, GPIO4_7, 13, 12, 0xf, 8, false)
721 MUX_CFG(DA830, GPIO4_8, 13, 16, 0xf, 8, false)
722 MUX_CFG(DA830, GPIO4_9, 13, 20, 0xf, 8, false)
723 MUX_CFG(DA830, GPIO0_0, 13, 24, 0xf, 8, false)
724 MUX_CFG(DA830, GPIO0_1, 13, 28, 0xf, 8, false)
725 MUX_CFG(DA830, EMA_D_2, 14, 0, 0xf, 1, false)
726 MUX_CFG(DA830, EMA_D_3, 14, 4, 0xf, 1, false)
727 MUX_CFG(DA830, EMA_D_4, 14, 8, 0xf, 1, false)
728 MUX_CFG(DA830, EMA_D_5, 14, 12, 0xf, 1, false)
729 MUX_CFG(DA830, EMA_D_6, 14, 16, 0xf, 1, false)
730 MUX_CFG(DA830, EMA_D_7, 14, 20, 0xf, 1, false)
731 MUX_CFG(DA830, EMA_D_8, 14, 24, 0xf, 1, false)
732 MUX_CFG(DA830, EMA_D_9, 14, 28, 0xf, 1, false)
733 MUX_CFG(DA830, MMCSD_DAT_2, 14, 0, 0xf, 2, false)
734 MUX_CFG(DA830, MMCSD_DAT_3, 14, 4, 0xf, 2, false)
735 MUX_CFG(DA830, MMCSD_DAT_4, 14, 8, 0xf, 2, false)
736 MUX_CFG(DA830, MMCSD_DAT_5, 14, 12, 0xf, 2, false)
737 MUX_CFG(DA830, MMCSD_DAT_6, 14, 16, 0xf, 2, false)
738 MUX_CFG(DA830, MMCSD_DAT_7, 14, 20, 0xf, 2, false)
739 MUX_CFG(DA830, UHPI_HD_8, 14, 24, 0xf, 2, false)
740 MUX_CFG(DA830, UHPI_HD_9, 14, 28, 0xf, 2, false)
741 MUX_CFG(DA830, UHPI_HD_2, 14, 0, 0xf, 4, false)
742 MUX_CFG(DA830, UHPI_HD_3, 14, 4, 0xf, 4, false)
743 MUX_CFG(DA830, UHPI_HD_4, 14, 8, 0xf, 4, false)
744 MUX_CFG(DA830, UHPI_HD_5, 14, 12, 0xf, 4, false)
745 MUX_CFG(DA830, UHPI_HD_6, 14, 16, 0xf, 4, false)
746 MUX_CFG(DA830, UHPI_HD_7, 14, 20, 0xf, 4, false)
747 MUX_CFG(DA830, LCD_D_8, 14, 24, 0xf, 4, false)
748 MUX_CFG(DA830, LCD_D_9, 14, 28, 0xf, 4, false)
749 MUX_CFG(DA830, GPIO0_2, 14, 0, 0xf, 8, false)
750 MUX_CFG(DA830, GPIO0_3, 14, 4, 0xf, 8, false)
751 MUX_CFG(DA830, GPIO0_4, 14, 8, 0xf, 8, false)
752 MUX_CFG(DA830, GPIO0_5, 14, 12, 0xf, 8, false)
753 MUX_CFG(DA830, GPIO0_6, 14, 16, 0xf, 8, false)
754 MUX_CFG(DA830, GPIO0_7, 14, 20, 0xf, 8, false)
755 MUX_CFG(DA830, GPIO0_8, 14, 24, 0xf, 8, false)
756 MUX_CFG(DA830, GPIO0_9, 14, 28, 0xf, 8, false)
757 MUX_CFG(DA830, EMA_D_10, 15, 0, 0xf, 1, false)
758 MUX_CFG(DA830, EMA_D_11, 15, 4, 0xf, 1, false)
759 MUX_CFG(DA830, EMA_D_12, 15, 8, 0xf, 1, false)
760 MUX_CFG(DA830, EMA_D_13, 15, 12, 0xf, 1, false)
761 MUX_CFG(DA830, EMA_D_14, 15, 16, 0xf, 1, false)
762 MUX_CFG(DA830, EMA_D_15, 15, 20, 0xf, 1, false)
763 MUX_CFG(DA830, EMA_A_0, 15, 24, 0xf, 1, false)
764 MUX_CFG(DA830, EMA_A_1, 15, 28, 0xf, 1, false)
765 MUX_CFG(DA830, UHPI_HD_10, 15, 0, 0xf, 2, false)
766 MUX_CFG(DA830, UHPI_HD_11, 15, 4, 0xf, 2, false)
767 MUX_CFG(DA830, UHPI_HD_12, 15, 8, 0xf, 2, false)
768 MUX_CFG(DA830, UHPI_HD_13, 15, 12, 0xf, 2, false)
769 MUX_CFG(DA830, UHPI_HD_14, 15, 16, 0xf, 2, false)
770 MUX_CFG(DA830, UHPI_HD_15, 15, 20, 0xf, 2, false)
771 MUX_CFG(DA830, LCD_D_7, 15, 24, 0xf, 2, false)
772 MUX_CFG(DA830, MMCSD_CLK, 15, 28, 0xf, 2, false)
773 MUX_CFG(DA830, LCD_D_10, 15, 0, 0xf, 4, false)
774 MUX_CFG(DA830, LCD_D_11, 15, 4, 0xf, 4, false)
775 MUX_CFG(DA830, LCD_D_12, 15, 8, 0xf, 4, false)
776 MUX_CFG(DA830, LCD_D_13, 15, 12, 0xf, 4, false)
777 MUX_CFG(DA830, LCD_D_14, 15, 16, 0xf, 4, false)
778 MUX_CFG(DA830, LCD_D_15, 15, 20, 0xf, 4, false)
779 MUX_CFG(DA830, UHPI_HCNTL0, 15, 28, 0xf, 4, false)
780 MUX_CFG(DA830, GPIO0_10, 15, 0, 0xf, 8, false)
781 MUX_CFG(DA830, GPIO0_11, 15, 4, 0xf, 8, false)
782 MUX_CFG(DA830, GPIO0_12, 15, 8, 0xf, 8, false)
783 MUX_CFG(DA830, GPIO0_13, 15, 12, 0xf, 8, false)
784 MUX_CFG(DA830, GPIO0_14, 15, 16, 0xf, 8, false)
785 MUX_CFG(DA830, GPIO0_15, 15, 20, 0xf, 8, false)
786 MUX_CFG(DA830, GPIO1_0, 15, 24, 0xf, 8, false)
787 MUX_CFG(DA830, GPIO1_1, 15, 28, 0xf, 8, false)
788 MUX_CFG(DA830, EMA_A_2, 16, 0, 0xf, 1, false)
789 MUX_CFG(DA830, EMA_A_3, 16, 4, 0xf, 1, false)
790 MUX_CFG(DA830, EMA_A_4, 16, 8, 0xf, 1, false)
791 MUX_CFG(DA830, EMA_A_5, 16, 12, 0xf, 1, false)
792 MUX_CFG(DA830, EMA_A_6, 16, 16, 0xf, 1, false)
793 MUX_CFG(DA830, EMA_A_7, 16, 20, 0xf, 1, false)
794 MUX_CFG(DA830, EMA_A_8, 16, 24, 0xf, 1, false)
795 MUX_CFG(DA830, EMA_A_9, 16, 28, 0xf, 1, false)
796 MUX_CFG(DA830, MMCSD_CMD, 16, 0, 0xf, 2, false)
797 MUX_CFG(DA830, LCD_D_6, 16, 4, 0xf, 2, false)
798 MUX_CFG(DA830, LCD_D_3, 16, 8, 0xf, 2, false)
799 MUX_CFG(DA830, LCD_D_2, 16, 12, 0xf, 2, false)
800 MUX_CFG(DA830, LCD_D_1, 16, 16, 0xf, 2, false)
801 MUX_CFG(DA830, LCD_D_0, 16, 20, 0xf, 2, false)
802 MUX_CFG(DA830, LCD_PCLK, 16, 24, 0xf, 2, false)
803 MUX_CFG(DA830, LCD_HSYNC, 16, 28, 0xf, 2, false)
804 MUX_CFG(DA830, UHPI_HCNTL1, 16, 0, 0xf, 4, false)
805 MUX_CFG(DA830, GPIO1_2, 16, 0, 0xf, 8, false)
806 MUX_CFG(DA830, GPIO1_3, 16, 4, 0xf, 8, false)
807 MUX_CFG(DA830, GPIO1_4, 16, 8, 0xf, 8, false)
808 MUX_CFG(DA830, GPIO1_5, 16, 12, 0xf, 8, false)
809 MUX_CFG(DA830, GPIO1_6, 16, 16, 0xf, 8, false)
810 MUX_CFG(DA830, GPIO1_7, 16, 20, 0xf, 8, false)
811 MUX_CFG(DA830, GPIO1_8, 16, 24, 0xf, 8, false)
812 MUX_CFG(DA830, GPIO1_9, 16, 28, 0xf, 8, false)
813 MUX_CFG(DA830, EMA_A_10, 17, 0, 0xf, 1, false)
814 MUX_CFG(DA830, EMA_A_11, 17, 4, 0xf, 1, false)
815 MUX_CFG(DA830, EMA_A_12, 17, 8, 0xf, 1, false)
816 MUX_CFG(DA830, EMA_BA_1, 17, 12, 0xf, 1, false)
817 MUX_CFG(DA830, EMA_BA_0, 17, 16, 0xf, 1, false)
818 MUX_CFG(DA830, EMA_CLK, 17, 20, 0xf, 1, false)
819 MUX_CFG(DA830, EMA_SDCKE, 17, 24, 0xf, 1, false)
820 MUX_CFG(DA830, NEMA_CAS, 17, 28, 0xf, 1, false)
821 MUX_CFG(DA830, LCD_VSYNC, 17, 0, 0xf, 2, false)
822 MUX_CFG(DA830, NLCD_AC_ENB_CS, 17, 4, 0xf, 2, false)
823 MUX_CFG(DA830, LCD_MCLK, 17, 8, 0xf, 2, false)
824 MUX_CFG(DA830, LCD_D_5, 17, 12, 0xf, 2, false)
825 MUX_CFG(DA830, LCD_D_4, 17, 16, 0xf, 2, false)
826 MUX_CFG(DA830, OBSCLK, 17, 20, 0xf, 2, false)
827 MUX_CFG(DA830, NEMA_CS_4, 17, 28, 0xf, 2, false)
828 MUX_CFG(DA830, UHPI_HHWIL, 17, 12, 0xf, 4, false)
829 MUX_CFG(DA830, AHCLKR2, 17, 20, 0xf, 4, false)
830 MUX_CFG(DA830, GPIO1_10, 17, 0, 0xf, 8, false)
831 MUX_CFG(DA830, GPIO1_11, 17, 4, 0xf, 8, false)
832 MUX_CFG(DA830, GPIO1_12, 17, 8, 0xf, 8, false)
833 MUX_CFG(DA830, GPIO1_13, 17, 12, 0xf, 8, false)
834 MUX_CFG(DA830, GPIO1_14, 17, 16, 0xf, 8, false)
835 MUX_CFG(DA830, GPIO1_15, 17, 20, 0xf, 8, false)
836 MUX_CFG(DA830, GPIO2_0, 17, 24, 0xf, 8, false)
837 MUX_CFG(DA830, GPIO2_1, 17, 28, 0xf, 8, false)
838 MUX_CFG(DA830, NEMA_RAS, 18, 0, 0xf, 1, false)
839 MUX_CFG(DA830, NEMA_WE, 18, 4, 0xf, 1, false)
840 MUX_CFG(DA830, NEMA_CS_0, 18, 8, 0xf, 1, false)
841 MUX_CFG(DA830, NEMA_CS_2, 18, 12, 0xf, 1, false)
842 MUX_CFG(DA830, NEMA_CS_3, 18, 16, 0xf, 1, false)
843 MUX_CFG(DA830, NEMA_OE, 18, 20, 0xf, 1, false)
844 MUX_CFG(DA830, NEMA_WE_DQM_1, 18, 24, 0xf, 1, false)
845 MUX_CFG(DA830, NEMA_WE_DQM_0, 18, 28, 0xf, 1, false)
846 MUX_CFG(DA830, NEMA_CS_5, 18, 0, 0xf, 2, false)
847 MUX_CFG(DA830, UHPI_HRNW, 18, 4, 0xf, 2, false)
848 MUX_CFG(DA830, NUHPI_HAS, 18, 8, 0xf, 2, false)
849 MUX_CFG(DA830, NUHPI_HCS, 18, 12, 0xf, 2, false)
850 MUX_CFG(DA830, NUHPI_HDS1, 18, 20, 0xf, 2, false)
851 MUX_CFG(DA830, NUHPI_HDS2, 18, 24, 0xf, 2, false)
852 MUX_CFG(DA830, NUHPI_HINT, 18, 28, 0xf, 2, false)
853 MUX_CFG(DA830, AXR0_12, 18, 4, 0xf, 4, false)
854 MUX_CFG(DA830, AMUTE2, 18, 16, 0xf, 4, false)
855 MUX_CFG(DA830, AXR0_13, 18, 20, 0xf, 4, false)
856 MUX_CFG(DA830, AXR0_14, 18, 24, 0xf, 4, false)
857 MUX_CFG(DA830, AXR0_15, 18, 28, 0xf, 4, false)
858 MUX_CFG(DA830, GPIO2_2, 18, 0, 0xf, 8, false)
859 MUX_CFG(DA830, GPIO2_3, 18, 4, 0xf, 8, false)
860 MUX_CFG(DA830, GPIO2_4, 18, 8, 0xf, 8, false)
861 MUX_CFG(DA830, GPIO2_5, 18, 12, 0xf, 8, false)
862 MUX_CFG(DA830, GPIO2_6, 18, 16, 0xf, 8, false)
863 MUX_CFG(DA830, GPIO2_7, 18, 20, 0xf, 8, false)
864 MUX_CFG(DA830, GPIO2_8, 18, 24, 0xf, 8, false)
865 MUX_CFG(DA830, GPIO2_9, 18, 28, 0xf, 8, false)
866 MUX_CFG(DA830, EMA_WAIT_0, 19, 0, 0xf, 1, false)
867 MUX_CFG(DA830, NUHPI_HRDY, 19, 0, 0xf, 2, false)
868 MUX_CFG(DA830, GPIO2_10, 19, 0, 0xf, 8, false)
869#endif
870};
871
872const short da830_emif25_pins[] __initdata = {
873 DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
874 DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
875 DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11,
876 DA830_EMA_D_12, DA830_EMA_D_13, DA830_EMA_D_14, DA830_EMA_D_15,
877 DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
878 DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
879 DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
880 DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_EMA_CLK,
881 DA830_EMA_SDCKE, DA830_NEMA_CS_4, DA830_NEMA_CS_5, DA830_NEMA_WE,
882 DA830_NEMA_CS_0, DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE,
883 DA830_NEMA_WE_DQM_1, DA830_NEMA_WE_DQM_0, DA830_EMA_WAIT_0,
884 -1
885};
886
887const short da830_spi0_pins[] __initdata = {
888 DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA,
889 DA830_NSPI0_SCS_0,
890 -1
891};
892
893const short da830_spi1_pins[] __initdata = {
894 DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA,
895 DA830_NSPI1_SCS_0,
896 -1
897};
898
899const short da830_mmc_sd_pins[] __initdata = {
900 DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
901 DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
902 DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
903 DA830_MMCSD_CMD,
904 -1
905};
906
907const short da830_uart0_pins[] __initdata = {
908 DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD,
909 -1
910};
911
912const short da830_uart1_pins[] __initdata = {
913 DA830_UART1_RXD, DA830_UART1_TXD,
914 -1
915};
916
917const short da830_uart2_pins[] __initdata = {
918 DA830_UART2_RXD, DA830_UART2_TXD,
919 -1
920};
921
922const short da830_usb20_pins[] __initdata = {
923 DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN,
924 -1
925};
926
927const short da830_usb11_pins[] __initdata = {
928 DA830_USB_REFCLKIN,
929 -1
930};
931
932const short da830_uhpi_pins[] __initdata = {
933 DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3,
934 DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7,
935 DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11,
936 DA830_UHPI_HD_12, DA830_UHPI_HD_13, DA830_UHPI_HD_14, DA830_UHPI_HD_15,
937 DA830_UHPI_HCNTL0, DA830_UHPI_HCNTL1, DA830_UHPI_HHWIL, DA830_UHPI_HRNW,
938 DA830_NUHPI_HAS, DA830_NUHPI_HCS, DA830_NUHPI_HDS1, DA830_NUHPI_HDS2,
939 DA830_NUHPI_HINT, DA830_NUHPI_HRDY,
940 -1
941};
942
943const short da830_cpgmac_pins[] __initdata = {
944 DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV,
945 DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK,
946 DA830_MDIO_D,
947 -1
948};
949
950const short da830_emif3c_pins[] __initdata = {
951 DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0,
952 DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1,
953 DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2,
954 DA830_EMB_A_3, DA830_EMB_A_4, DA830_EMB_A_5, DA830_EMB_A_6,
955 DA830_EMB_A_7, DA830_EMB_A_8, DA830_EMB_A_9, DA830_EMB_A_10,
956 DA830_EMB_A_11, DA830_EMB_A_12, DA830_NEMB_WE_DQM_3,
957 DA830_NEMB_WE_DQM_2, DA830_EMB_D_0, DA830_EMB_D_1, DA830_EMB_D_2,
958 DA830_EMB_D_3, DA830_EMB_D_4, DA830_EMB_D_5, DA830_EMB_D_6,
959 DA830_EMB_D_7, DA830_EMB_D_8, DA830_EMB_D_9, DA830_EMB_D_10,
960 DA830_EMB_D_11, DA830_EMB_D_12, DA830_EMB_D_13, DA830_EMB_D_14,
961 DA830_EMB_D_15, DA830_EMB_D_16, DA830_EMB_D_17, DA830_EMB_D_18,
962 DA830_EMB_D_19, DA830_EMB_D_20, DA830_EMB_D_21, DA830_EMB_D_22,
963 DA830_EMB_D_23, DA830_EMB_D_24, DA830_EMB_D_25, DA830_EMB_D_26,
964 DA830_EMB_D_27, DA830_EMB_D_28, DA830_EMB_D_29, DA830_EMB_D_30,
965 DA830_EMB_D_31, DA830_NEMB_WE_DQM_1, DA830_NEMB_WE_DQM_0,
966 -1
967};
968
969const short da830_mcasp0_pins[] __initdata = {
970 DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0,
971 DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0,
972 DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3,
973 DA830_AXR0_4, DA830_AXR0_5, DA830_AXR0_6, DA830_AXR0_7,
974 DA830_AXR0_8, DA830_AXR0_9, DA830_AXR0_10, DA830_AXR0_11,
975 DA830_AXR0_12, DA830_AXR0_13, DA830_AXR0_14, DA830_AXR0_15,
976 -1
977};
978
979const short da830_mcasp1_pins[] __initdata = {
980 DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1,
981 DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1,
982 DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3,
983 DA830_AXR1_4, DA830_AXR1_5, DA830_AXR1_6, DA830_AXR1_7,
984 DA830_AXR1_8, DA830_AXR1_9, DA830_AXR1_10, DA830_AXR1_11,
985 -1
986};
987
988const short da830_mcasp2_pins[] __initdata = {
989 DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2,
990 DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2,
991 DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3,
992 -1
993};
994
995const short da830_i2c0_pins[] __initdata = {
996 DA830_I2C0_SDA, DA830_I2C0_SCL,
997 -1
998};
999
1000const short da830_i2c1_pins[] __initdata = {
1001 DA830_I2C1_SCL, DA830_I2C1_SDA,
1002 -1
1003};
1004
1005const short da830_lcdcntl_pins[] __initdata = {
1006 DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3,
1007 DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7,
1008 DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11,
1009 DA830_LCD_D_12, DA830_LCD_D_13, DA830_LCD_D_14, DA830_LCD_D_15,
1010 DA830_LCD_PCLK, DA830_LCD_HSYNC, DA830_LCD_VSYNC, DA830_NLCD_AC_ENB_CS,
1011 DA830_LCD_MCLK,
1012 -1
1013};
1014
1015const short da830_pwm_pins[] __initdata = {
1016 DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A,
1017 DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ,
1018 DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A,
1019 -1
1020};
1021
1022const short da830_ecap0_pins[] __initdata = {
1023 DA830_ECAP0_APWM0,
1024 -1
1025};
1026
1027const short da830_ecap1_pins[] __initdata = {
1028 DA830_ECAP1_APWM1,
1029 -1
1030};
1031
1032const short da830_ecap2_pins[] __initdata = {
1033 DA830_ECAP2_APWM2,
1034 -1
1035};
1036
1037const short da830_eqep0_pins[] __initdata = {
1038 DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B,
1039 -1
1040};
1041
1042const short da830_eqep1_pins[] __initdata = {
1043 DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B,
1044 -1
1045};
1046
1047int da830_pinmux_setup(const short pins[])
1048{
1049 int i, error = -EINVAL;
1050
1051 if (pins)
1052 for (i = 0; pins[i] >= 0; i++) {
1053 error = davinci_cfg_reg(pins[i]);
1054 if (error)
1055 break;
1056 }
1057
1058 return error;
1059}
1060
1061/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
1062static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = {
1063 [IRQ_DA8XX_COMMTX] = 7,
1064 [IRQ_DA8XX_COMMRX] = 7,
1065 [IRQ_DA8XX_NINT] = 7,
1066 [IRQ_DA8XX_EVTOUT0] = 7,
1067 [IRQ_DA8XX_EVTOUT1] = 7,
1068 [IRQ_DA8XX_EVTOUT2] = 7,
1069 [IRQ_DA8XX_EVTOUT3] = 7,
1070 [IRQ_DA8XX_EVTOUT4] = 7,
1071 [IRQ_DA8XX_EVTOUT5] = 7,
1072 [IRQ_DA8XX_EVTOUT6] = 7,
1073 [IRQ_DA8XX_EVTOUT6] = 7,
1074 [IRQ_DA8XX_EVTOUT7] = 7,
1075 [IRQ_DA8XX_CCINT0] = 7,
1076 [IRQ_DA8XX_CCERRINT] = 7,
1077 [IRQ_DA8XX_TCERRINT0] = 7,
1078 [IRQ_DA8XX_AEMIFINT] = 7,
1079 [IRQ_DA8XX_I2CINT0] = 7,
1080 [IRQ_DA8XX_MMCSDINT0] = 7,
1081 [IRQ_DA8XX_MMCSDINT1] = 7,
1082 [IRQ_DA8XX_ALLINT0] = 7,
1083 [IRQ_DA8XX_RTC] = 7,
1084 [IRQ_DA8XX_SPINT0] = 7,
1085 [IRQ_DA8XX_TINT12_0] = 7,
1086 [IRQ_DA8XX_TINT34_0] = 7,
1087 [IRQ_DA8XX_TINT12_1] = 7,
1088 [IRQ_DA8XX_TINT34_1] = 7,
1089 [IRQ_DA8XX_UARTINT0] = 7,
1090 [IRQ_DA8XX_KEYMGRINT] = 7,
1091 [IRQ_DA8XX_SECINT] = 7,
1092 [IRQ_DA8XX_SECKEYERR] = 7,
1093 [IRQ_DA830_MPUERR] = 7,
1094 [IRQ_DA830_IOPUERR] = 7,
1095 [IRQ_DA830_BOOTCFGERR] = 7,
1096 [IRQ_DA8XX_CHIPINT0] = 7,
1097 [IRQ_DA8XX_CHIPINT1] = 7,
1098 [IRQ_DA8XX_CHIPINT2] = 7,
1099 [IRQ_DA8XX_CHIPINT3] = 7,
1100 [IRQ_DA8XX_TCERRINT1] = 7,
1101 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
1102 [IRQ_DA8XX_C0_RX_PULSE] = 7,
1103 [IRQ_DA8XX_C0_TX_PULSE] = 7,
1104 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
1105 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
1106 [IRQ_DA8XX_C1_RX_PULSE] = 7,
1107 [IRQ_DA8XX_C1_TX_PULSE] = 7,
1108 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
1109 [IRQ_DA8XX_MEMERR] = 7,
1110 [IRQ_DA8XX_GPIO0] = 7,
1111 [IRQ_DA8XX_GPIO1] = 7,
1112 [IRQ_DA8XX_GPIO2] = 7,
1113 [IRQ_DA8XX_GPIO3] = 7,
1114 [IRQ_DA8XX_GPIO4] = 7,
1115 [IRQ_DA8XX_GPIO5] = 7,
1116 [IRQ_DA8XX_GPIO6] = 7,
1117 [IRQ_DA8XX_GPIO7] = 7,
1118 [IRQ_DA8XX_GPIO8] = 7,
1119 [IRQ_DA8XX_I2CINT1] = 7,
1120 [IRQ_DA8XX_LCDINT] = 7,
1121 [IRQ_DA8XX_UARTINT1] = 7,
1122 [IRQ_DA8XX_MCASPINT] = 7,
1123 [IRQ_DA8XX_ALLINT1] = 7,
1124 [IRQ_DA8XX_SPINT1] = 7,
1125 [IRQ_DA8XX_UHPI_INT1] = 7,
1126 [IRQ_DA8XX_USB_INT] = 7,
1127 [IRQ_DA8XX_IRQN] = 7,
1128 [IRQ_DA8XX_RWAKEUP] = 7,
1129 [IRQ_DA8XX_UARTINT2] = 7,
1130 [IRQ_DA8XX_DFTSSINT] = 7,
1131 [IRQ_DA8XX_EHRPWM0] = 7,
1132 [IRQ_DA8XX_EHRPWM0TZ] = 7,
1133 [IRQ_DA8XX_EHRPWM1] = 7,
1134 [IRQ_DA8XX_EHRPWM1TZ] = 7,
1135 [IRQ_DA830_EHRPWM2] = 7,
1136 [IRQ_DA830_EHRPWM2TZ] = 7,
1137 [IRQ_DA8XX_ECAP0] = 7,
1138 [IRQ_DA8XX_ECAP1] = 7,
1139 [IRQ_DA8XX_ECAP2] = 7,
1140 [IRQ_DA830_EQEP0] = 7,
1141 [IRQ_DA830_EQEP1] = 7,
1142 [IRQ_DA830_T12CMPINT0_0] = 7,
1143 [IRQ_DA830_T12CMPINT1_0] = 7,
1144 [IRQ_DA830_T12CMPINT2_0] = 7,
1145 [IRQ_DA830_T12CMPINT3_0] = 7,
1146 [IRQ_DA830_T12CMPINT4_0] = 7,
1147 [IRQ_DA830_T12CMPINT5_0] = 7,
1148 [IRQ_DA830_T12CMPINT6_0] = 7,
1149 [IRQ_DA830_T12CMPINT7_0] = 7,
1150 [IRQ_DA830_T12CMPINT0_1] = 7,
1151 [IRQ_DA830_T12CMPINT1_1] = 7,
1152 [IRQ_DA830_T12CMPINT2_1] = 7,
1153 [IRQ_DA830_T12CMPINT3_1] = 7,
1154 [IRQ_DA830_T12CMPINT4_1] = 7,
1155 [IRQ_DA830_T12CMPINT5_1] = 7,
1156 [IRQ_DA830_T12CMPINT6_1] = 7,
1157 [IRQ_DA830_T12CMPINT7_1] = 7,
1158 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
1159};
1160
1161static struct map_desc da830_io_desc[] = {
1162 {
1163 .virtual = IO_VIRT,
1164 .pfn = __phys_to_pfn(IO_PHYS),
1165 .length = IO_SIZE,
1166 .type = MT_DEVICE
1167 },
1168 {
1169 .virtual = DA8XX_CP_INTC_VIRT,
1170 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
1171 .length = DA8XX_CP_INTC_SIZE,
1172 .type = MT_DEVICE
1173 },
1174};
1175
1176static void __iomem *da830_psc_bases[] = {
1177 IO_ADDRESS(DA830_PSC0_BASE),
1178 IO_ADDRESS(DA830_PSC1_BASE),
1179};
1180
1181/* Contents of JTAG ID register used to identify exact cpu type */
1182static struct davinci_id da830_ids[] = {
1183 {
1184 .variant = 0x0,
1185 .part_no = 0xb7df,
1186 .manufacturer = 0x017, /* 0x02f >> 1 */
1187 .cpu_id = DAVINCI_CPU_ID_DA830,
1188 .name = "da830/omap l137",
1189 },
1190};
1191
1192static struct davinci_timer_instance da830_timer_instance[2] = {
1193 {
1194 .base = IO_ADDRESS(DA830_TIMER64P0_BASE),
1195 .bottom_irq = IRQ_DA8XX_TINT12_0,
1196 .top_irq = IRQ_DA8XX_TINT34_0,
1197 .cmp_off = DA830_CMP12_0,
1198 .cmp_irq = IRQ_DA830_T12CMPINT0_0,
1199 },
1200 {
1201 .base = IO_ADDRESS(DA830_TIMER64P1_BASE),
1202 .bottom_irq = IRQ_DA8XX_TINT12_1,
1203 .top_irq = IRQ_DA8XX_TINT34_1,
1204 .cmp_off = DA830_CMP12_0,
1205 .cmp_irq = IRQ_DA830_T12CMPINT0_1,
1206 },
1207};
1208
1209/*
1210 * T0_BOT: Timer 0, bottom : Used for clock_event & clocksource
1211 * T0_TOP: Timer 0, top : Used by DSP
1212 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
1213 */
1214static struct davinci_timer_info da830_timer_info = {
1215 .timers = da830_timer_instance,
1216 .clockevent_id = T0_BOT,
1217 .clocksource_id = T0_BOT,
1218};
1219
1220static struct davinci_soc_info davinci_soc_info_da830 = {
1221 .io_desc = da830_io_desc,
1222 .io_desc_num = ARRAY_SIZE(da830_io_desc),
1223 .jtag_id_base = IO_ADDRESS(DA830_JTAG_ID_REG),
1224 .ids = da830_ids,
1225 .ids_num = ARRAY_SIZE(da830_ids),
1226 .cpu_clks = da830_clks,
1227 .psc_bases = da830_psc_bases,
1228 .psc_bases_num = ARRAY_SIZE(da830_psc_bases),
1229 .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120),
1230 .pinmux_pins = da830_pins,
1231 .pinmux_pins_num = ARRAY_SIZE(da830_pins),
1232 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
1233 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1234 .intc_irq_prios = da830_default_priorities,
1235 .intc_irq_num = DA830_N_CP_INTC_IRQ,
1236 .timer_info = &da830_timer_info,
1237 .gpio_base = IO_ADDRESS(DA830_GPIO_BASE),
1238 .gpio_num = 128,
1239 .gpio_irq = IRQ_DA8XX_GPIO0,
1240 .serial_dev = &da8xx_serial_device,
1241 .emac_pdata = &da8xx_emac_pdata,
1242};
1243
1244void __init da830_init(void)
1245{
1246 davinci_common_init(&davinci_soc_info_da830);
1247}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 22:53:15 -0500