diff options
author | Sekhar Nori <nsekhar@ti.com> | 2009-08-31 06:18:03 -0400 |
---|---|---|
committer | Kevin Hilman <khilman@deeprootsystems.com> | 2009-11-25 13:21:20 -0500 |
commit | d6a61563f9e934ef20a1338780082f63802c8908 (patch) | |
tree | 543d650b9c87c6a63974db565d803ad26bf1ee38 /arch/arm/mach-davinci/clock.h | |
parent | de381a91f544008f4f99571e2ef1f60b92d5f0cf (diff) |
davinci: support changing the clock rate in clock framework
clk_round_rate, clk_set_rate have been updated to handle dynamic
frequency changes.
The motivation behind the changes is to support dynamic CPU frequency
change.
davinci_set_pllrate() changes the PLL rate of a given PLL. This function
has been presented as a generic function though it has been tested only
on OMAP-L138 EVM. No other currently available DaVinci device will probably
use this function, but any future device specific changes will hopefully be
small enough to get taken care using a cpu_is_xxx() macro.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/clock.h')
-rw-r--r-- | arch/arm/mach-davinci/clock.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h index 202b9ff27b9d..a75d3f70b351 100644 --- a/arch/arm/mach-davinci/clock.h +++ b/arch/arm/mach-davinci/clock.h | |||
@@ -22,6 +22,10 @@ | |||
22 | /* PLL/Reset register offsets */ | 22 | /* PLL/Reset register offsets */ |
23 | #define PLLCTL 0x100 | 23 | #define PLLCTL 0x100 |
24 | #define PLLCTL_PLLEN BIT(0) | 24 | #define PLLCTL_PLLEN BIT(0) |
25 | #define PLLCTL_PLLPWRDN BIT(1) | ||
26 | #define PLLCTL_PLLRST BIT(3) | ||
27 | #define PLLCTL_PLLDIS BIT(4) | ||
28 | #define PLLCTL_PLLENSRC BIT(5) | ||
25 | #define PLLCTL_CLKMODE BIT(8) | 29 | #define PLLCTL_CLKMODE BIT(8) |
26 | 30 | ||
27 | #define PLLM 0x110 | 31 | #define PLLM 0x110 |
@@ -74,6 +78,8 @@ struct clk { | |||
74 | struct pll_data *pll_data; | 78 | struct pll_data *pll_data; |
75 | u32 div_reg; | 79 | u32 div_reg; |
76 | unsigned long (*recalc) (struct clk *); | 80 | unsigned long (*recalc) (struct clk *); |
81 | int (*set_rate) (struct clk *clk, unsigned long rate); | ||
82 | int (*round_rate) (struct clk *clk, unsigned long rate); | ||
77 | }; | 83 | }; |
78 | 84 | ||
79 | /* Clock flags */ | 85 | /* Clock flags */ |
@@ -97,6 +103,8 @@ struct davinci_clk { | |||
97 | } | 103 | } |
98 | 104 | ||
99 | int davinci_clk_init(struct davinci_clk *clocks); | 105 | int davinci_clk_init(struct davinci_clk *clocks); |
106 | int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, | ||
107 | unsigned int mult, unsigned int postdiv); | ||
100 | 108 | ||
101 | extern struct platform_device davinci_wdt_device; | 109 | extern struct platform_device davinci_wdt_device; |
102 | 110 | ||