davinci: DA850/OMAP-L138: allow async3 source to be changed

The patch allows Async3 clock source to be selected between PLL1 SYSCLK2
and PLL0 SYSCLK2.

Having Async3 source from PLL1 SYSCLK2 allows peripherals on that
domain to remain unaffected by frequency scaling on PLL0.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index a75d3f70b351..d45dc6960a94 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -69,9 +69,9 @@ struct clk {
         const char              *name;
         unsigned long           rate;
         u8                      usecount;
-        u8                      flags;
         u8                      lpsc;
         u8                      psc_ctlr;
+        u32                     flags;
         struct clk              *parent;
         struct list_head        children;       /* list of children */
         struct list_head        childnode;      /* parent's child list node */
@@ -82,7 +82,7 @@ struct clk {
         int (*round_rate) (struct clk *clk, unsigned long rate);
 };
 
-/* Clock flags */
+/* Clock flags: SoC-specific flags start at BIT(16) */
 #define ALWAYS_ENABLED          BIT(1)
 #define CLK_PSC                 BIT(2)
 #define PSC_DSP                 BIT(3) /* PSC uses DSP domain, not ARM */