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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2010-04-21 10:11:33 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2010-05-06 18:02:07 -0400
commit7a9978a1e2225507025a8b90b4289d506a416bd9 (patch)
tree163a66035df8ed7a510ad692eaf7259c885a932e /arch/arm/mach-davinci/board-neuros-osd2.c
parent280faffb4e059b3f453e297af7060d9c277c0ca9 (diff)
DaVinci: move IDE platform device to its proper place
The IDE platform device is registered in three different places (2 board files for DM644x and in dm646x.c for DM646x) while both the IDE base address and the IDE IRQ are the same for both SoCs -- therefore, the proper place for the IDE platform seems to be in devices.c. Merge the IDE platform data and registration code and create davinci_init_ide() in place of dm646x_init_ide()... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/board-neuros-osd2.c')
-rw-r--r--arch/arm/mach-davinci/board-neuros-osd2.c34
1 files changed, 2 insertions, 32 deletions
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 5afe37e3a4cb..875770cdea0a 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -31,6 +31,7 @@
31#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
32 32
33#include <mach/dm644x.h> 33#include <mach/dm644x.h>
34#include <mach/common.h>
34#include <mach/i2c.h> 35#include <mach/i2c.h>
35#include <mach/serial.h> 36#include <mach/serial.h>
36#include <mach/mux.h> 37#include <mach/mux.h>
@@ -41,8 +42,6 @@
41#define NEUROS_OSD2_PHY_MASK 0x2 42#define NEUROS_OSD2_PHY_MASK 0x2
42#define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ 43#define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
43 44
44#define DAVINCI_CFC_ATA_BASE 0x01C66000
45
46#define LXT971_PHY_ID 0x001378e2 45#define LXT971_PHY_ID 0x001378e2
47#define LXT971_PHY_MASK 0xfffffff0 46#define LXT971_PHY_MASK 0xfffffff0
48 47
@@ -127,32 +126,6 @@ static struct platform_device davinci_fb_device = {
127 .num_resources = 0, 126 .num_resources = 0,
128}; 127};
129 128
130static struct resource ide_resources[] = {
131 {
132 .start = DAVINCI_CFC_ATA_BASE,
133 .end = DAVINCI_CFC_ATA_BASE + 0x7ff,
134 .flags = IORESOURCE_MEM,
135 },
136 {
137 .start = IRQ_IDE,
138 .end = IRQ_IDE,
139 .flags = IORESOURCE_IRQ,
140 },
141};
142
143static u64 ide_dma_mask = DMA_BIT_MASK(32);
144
145static struct platform_device ide_dev = {
146 .name = "palm_bk3710",
147 .id = -1,
148 .resource = ide_resources,
149 .num_resources = ARRAY_SIZE(ide_resources),
150 .dev = {
151 .dma_mask = &ide_dma_mask,
152 .coherent_dma_mask = DMA_BIT_MASK(32),
153 },
154};
155
156static struct snd_platform_data dm644x_ntosd2_snd_data; 129static struct snd_platform_data dm644x_ntosd2_snd_data;
157 130
158static struct gpio_led ntosd2_leds[] = { 131static struct gpio_led ntosd2_leds[] = {
@@ -256,10 +229,7 @@ static __init void davinci_ntosd2_init(void)
256 pr_warning("WARNING: both IDE and Flash are " 229 pr_warning("WARNING: both IDE and Flash are "
257 "enabled, but they share AEMIF pins.\n" 230 "enabled, but they share AEMIF pins.\n"
258 "\tDisable IDE for NAND/NOR support.\n"); 231 "\tDisable IDE for NAND/NOR support.\n");
259 davinci_cfg_reg(DM644X_HPIEN_DISABLE); 232 davinci_init_ide();
260 davinci_cfg_reg(DM644X_ATAEN);
261 davinci_cfg_reg(DM644X_HDIREN);
262 platform_device_register(&ide_dev);
263 } else if (HAS_NAND) { 233 } else if (HAS_NAND) {
264 davinci_cfg_reg(DM644X_HPIEN_DISABLE); 234 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
265 davinci_cfg_reg(DM644X_ATAEN_DISABLE); 235 davinci_cfg_reg(DM644X_ATAEN_DISABLE);