Merge branch 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci

* 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci: (40 commits)
  DaVinci DM365: Adding support for SPI EEPROM
  DaVinci DM365: Adding DM365 SPI support
  DaVinci DM355: Modifications to DM355 SPI support
  DaVinci: SPI: Adding header file for SPI support.
  davinci: dm646x: CDCE clocks: davinci_clk converted to clk_lookup
  davinci: clkdev cleanup: remove clk_lookup wrapper, use clkdev_add_table()
  DaVinci: DM365: Voice codec support for the DM365 SoC
  davinci: clock: let clk->set_rate function sleep
  Add SDA and SCL pin numbers to i2c platform data
  davinci: da8xx/omap-l1xx: Add EDMA platform data for da850/omap-l138
  davinci: build list of unused EDMA events dynamically
  davinci: Fix edma_alloc_channel api for EDMA_CHANNEL_ANY case
  davinci: Keep count of channel controllers on a platform
  davinci: Correct return value of edma_alloc_channel api
  davinci: add CDCE949 support on DM6467 EVM
  davinci: add support for CDCE949 clock synthesizer
  davinci: da850/omap-l138 EVM: register for suspend support
  davinci: da850/omap-l138: add support for SoC suspend
  davinci: add power management support
  DaVinci: DM365: Changing default queue for DM365.
  ...

1 files changed, 99 insertions, 44 deletions

diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 8d0b0e01c59b..5ba3cb2daaa0 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -30,6 +30,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/clk.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -39,54 +40,13 @@
 #include <mach/serial.h>
 #include <mach/i2c.h>
 #include <mach/nand.h>
+#include <mach/clock.h>
+#include <mach/cdce949.h>
 
-#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
-    defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
-#define HAS_ATA 1
-#else
-#define HAS_ATA 0
-#endif
-
-#define DAVINCI_ASYNC_EMIF_CONTROL_BASE         0x20008000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE        0x42000000
+#include "clock.h"
 
 #define NAND_BLOCK_SIZE         SZ_128K
 
-/* CPLD Register 0 bits to control ATA */
-#define DM646X_EVM_ATA_RST              BIT(0)
-#define DM646X_EVM_ATA_PWD              BIT(1)
-
-#define DM646X_EVM_PHY_MASK             (0x2)
-#define DM646X_EVM_MDIO_FREQUENCY       (2200000) /* PHY bus frequency */
-
-#define VIDCLKCTL_OFFSET        (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
-#define VSCLKDIS_OFFSET         (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
-#define VCH2CLK_MASK            (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
-#define VCH2CLK_SYSCLK8         (BIT(9))
-#define VCH2CLK_AUXCLK          (BIT(9) | BIT(8))
-#define VCH3CLK_MASK            (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
-#define VCH3CLK_SYSCLK8         (BIT(13))
-#define VCH3CLK_AUXCLK          (BIT(14) | BIT(13))
-
-#define VIDCH2CLK               (BIT(10))
-#define VIDCH3CLK               (BIT(11))
-#define VIDCH1CLK               (BIT(4))
-#define TVP7002_INPUT           (BIT(4))
-#define TVP5147_INPUT           (~BIT(4))
-#define VPIF_INPUT_ONE_CHANNEL  (BIT(5))
-#define VPIF_INPUT_TWO_CHANNEL  (~BIT(5))
-#define TVP5147_CH0             "tvp514x-0"
-#define TVP5147_CH1             "tvp514x-1"
-
-static void __iomem *vpif_vidclkctl_reg;
-static void __iomem *vpif_vsclkdis_reg;
-/* spin lock for updating above registers */
-static spinlock_t vpif_reg_lock;
-
-static struct davinci_uart_config uart_config __initdata = {
-        .enabled_uarts = (1 << 0),
-};
-
 /* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
  * and U-Boot environment this avoids dependency on any particular combination
  * of UBL, U-Boot or flashing tools etc.
@@ -120,6 +80,9 @@ static struct davinci_nand_pdata davinci_nand_data = {
         .options                = 0,
 };
 
+#define DAVINCI_ASYNC_EMIF_CONTROL_BASE         0x20008000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE        0x42000000
+
 static struct resource davinci_nand_resources[] = {
         {
                 .start          = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
@@ -144,6 +107,17 @@ static struct platform_device davinci_nand_device = {
         },
 };
 
+#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
+    defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
+#define HAS_ATA 1
+#else
+#define HAS_ATA 0
+#endif
+
+/* CPLD Register 0 bits to control ATA */
+#define DM646X_EVM_ATA_RST              BIT(0)
+#define DM646X_EVM_ATA_PWD              BIT(1)
+
 /* CPLD Register 0 Client: used for I/O Control */
 static int cpld_reg0_probe(struct i2c_client *client,
                            const struct i2c_device_id *id)
@@ -417,6 +391,9 @@ static struct i2c_board_info __initdata i2c_info[] =  {
         {
                 I2C_BOARD_INFO("cpld_video", 0x3b),
         },
+        {
+                I2C_BOARD_INFO("cdce949", 0x6c),
+        },
 };
 
 static struct davinci_i2c_platform_data i2c_pdata = {
@@ -424,6 +401,30 @@ static struct davinci_i2c_platform_data i2c_pdata = {
         .bus_delay      = 0 /* usec */,
 };
 
+#define VIDCLKCTL_OFFSET        (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
+#define VSCLKDIS_OFFSET         (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
+#define VCH2CLK_MASK            (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
+#define VCH2CLK_SYSCLK8         (BIT(9))
+#define VCH2CLK_AUXCLK          (BIT(9) | BIT(8))
+#define VCH3CLK_MASK            (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
+#define VCH3CLK_SYSCLK8         (BIT(13))
+#define VCH3CLK_AUXCLK          (BIT(14) | BIT(13))
+
+#define VIDCH2CLK               (BIT(10))
+#define VIDCH3CLK               (BIT(11))
+#define VIDCH1CLK               (BIT(4))
+#define TVP7002_INPUT           (BIT(4))
+#define TVP5147_INPUT           (~BIT(4))
+#define VPIF_INPUT_ONE_CHANNEL  (BIT(5))
+#define VPIF_INPUT_TWO_CHANNEL  (~BIT(5))
+#define TVP5147_CH0             "tvp514x-0"
+#define TVP5147_CH1             "tvp514x-1"
+
+static void __iomem *vpif_vidclkctl_reg;
+static void __iomem *vpif_vsclkdis_reg;
+/* spin lock for updating above registers */
+static spinlock_t vpif_reg_lock;
+
 static int set_vpif_clock(int mux_mode, int hd)
 {
         unsigned long flags;
@@ -685,11 +686,44 @@ static void __init evm_init_i2c(void)
         evm_init_video();
 }
 
+#define CDCE949_XIN_RATE        27000000
+
+/* CDCE949 support - "lpsc" field is overridden to work as clock number */
+static struct clk cdce_clk_in = {
+        .name   = "cdce_xin",
+        .rate   = CDCE949_XIN_RATE,
+};
+
+static struct clk_lookup cdce_clks[] = {
+        CLK(NULL, "xin", &cdce_clk_in),
+        CLK(NULL, NULL, NULL),
+};
+
+static void __init cdce_clk_init(void)
+{
+        struct clk_lookup *c;
+        struct clk *clk;
+
+        for (c = cdce_clks; c->clk; c++) {
+                clk = c->clk;
+                clkdev_add(c);
+                clk_register(clk);
+        }
+}
+
 static void __init davinci_map_io(void)
 {
         dm646x_init();
+        cdce_clk_init();
 }
 
+static struct davinci_uart_config uart_config __initdata = {
+        .enabled_uarts = (1 << 0),
+};
+
+#define DM646X_EVM_PHY_MASK             (0x2)
+#define DM646X_EVM_MDIO_FREQUENCY       (2200000) /* PHY bus frequency */
+
 static __init void evm_init(void)
 {
         struct davinci_soc_info *soc_info = &davinci_soc_info;
@@ -713,6 +747,17 @@ static __init void davinci_dm646x_evm_irq_init(void)
         davinci_irq_init();
 }
 
+#define DM646X_EVM_REF_FREQ             27000000
+#define DM6467T_EVM_REF_FREQ            33000000
+
+void __init dm646x_board_setup_refclk(struct clk *clk)
+{
+        if (machine_is_davinci_dm6467tevm())
+                clk->rate = DM6467T_EVM_REF_FREQ;
+        else
+                clk->rate = DM646X_EVM_REF_FREQ;
+}
+
 MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
         .phys_io      = IO_PHYS,
         .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
@@ -723,3 +768,13 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
         .init_machine = evm_init,
 MACHINE_END
 
+MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
+        .phys_io      = IO_PHYS,
+        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
+        .boot_params  = (0x80000100),
+        .map_io       = davinci_map_io,
+        .init_irq     = davinci_dm646x_evm_irq_init,
+        .timer        = &davinci_timer,
+        .init_machine = evm_init,
+MACHINE_END
+