diff options
author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2010-04-16 13:29:20 -0400 |
---|---|---|
committer | Kevin Hilman <khilman@deeprootsystems.com> | 2010-05-06 18:02:06 -0400 |
commit | 002cb2d2f1dde524b2aef6e43922984f6d1c8adc (patch) | |
tree | 0759d468cc34005aafcacf54e673eae7f7a8a326 /arch/arm/mach-davinci/board-da830-evm.c | |
parent | 7034217467abe91b5bc63fc2993bb8eec1cf3c9f (diff) |
DA830 EVM: use DA8XX_AEMIF_*_BASE #define's
The board file #define's its own version of EMIFA base addresses, while there
are DA8XX_AEMIF_*_BASE macros #define'd in <mach/da8xx.h>. Start using them
instead.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-davinci/board-da830-evm.c')
-rw-r--r-- | arch/arm/mach-davinci/board-da830-evm.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c index 925705649ed0..8f079d2f1af9 100644 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ b/arch/arm/mach-davinci/board-da830-evm.c | |||
@@ -33,9 +33,6 @@ | |||
33 | #define DA830_EVM_PHY_MASK 0x0 | 33 | #define DA830_EVM_PHY_MASK 0x0 |
34 | #define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ | 34 | #define DA830_EVM_MDIO_FREQUENCY 2200000 /* PHY bus frequency */ |
35 | 35 | ||
36 | #define DA830_EMIF25_ASYNC_DATA_CE3_BASE 0x62000000 | ||
37 | #define DA830_EMIF25_CONTROL_BASE 0x68000000 | ||
38 | |||
39 | /* | 36 | /* |
40 | * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4]. | 37 | * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4]. |
41 | */ | 38 | */ |
@@ -375,13 +372,13 @@ static struct davinci_nand_pdata da830_evm_nand_pdata = { | |||
375 | 372 | ||
376 | static struct resource da830_evm_nand_resources[] = { | 373 | static struct resource da830_evm_nand_resources[] = { |
377 | [0] = { /* First memory resource is NAND I/O window */ | 374 | [0] = { /* First memory resource is NAND I/O window */ |
378 | .start = DA830_EMIF25_ASYNC_DATA_CE3_BASE, | 375 | .start = DA8XX_AEMIF_CS3_BASE, |
379 | .end = DA830_EMIF25_ASYNC_DATA_CE3_BASE + PAGE_SIZE - 1, | 376 | .end = DA8XX_AEMIF_CS3_BASE + PAGE_SIZE - 1, |
380 | .flags = IORESOURCE_MEM, | 377 | .flags = IORESOURCE_MEM, |
381 | }, | 378 | }, |
382 | [1] = { /* Second memory resource is AEMIF control registers */ | 379 | [1] = { /* Second memory resource is AEMIF control registers */ |
383 | .start = DA830_EMIF25_CONTROL_BASE, | 380 | .start = DA8XX_AEMIF_CTL_BASE, |
384 | .end = DA830_EMIF25_CONTROL_BASE + SZ_32K - 1, | 381 | .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, |
385 | .flags = IORESOURCE_MEM, | 382 | .flags = IORESOURCE_MEM, |
386 | }, | 383 | }, |
387 | }; | 384 | }; |