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authorAnton Vorontsov <avorontsov@mvista.com>2010-03-25 10:12:41 -0400
committerAnton Vorontsov <avorontsov@mvista.com>2010-05-02 13:55:46 -0400
commitd94f944e108da21badabd99f527b25e03b677b96 (patch)
tree3c150c38dcf4c6749eff881bacad872347ab3edd /arch/arm/mach-cns3xxx
parentea5ce655b90f5debb7b9768284eaafcca218ddef (diff)
ARM: cns3xxx: Add basic support for Cavium Networks CNS3xxx processors
This patch adds very basic support for ECONA CNS3xxx ARM11 MPcore (ARMv6) dual-core processors. Note that SMP is not yet supported, as well as many peripheral devices. Support for these features will be added later. Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>
Diffstat (limited to 'arch/arm/mach-cns3xxx')
-rw-r--r--arch/arm/mach-cns3xxx/Kconfig4
-rw-r--r--arch/arm/mach-cns3xxx/Makefile1
-rw-r--r--arch/arm/mach-cns3xxx/Makefile.boot3
-rw-r--r--arch/arm/mach-cns3xxx/core.c249
-rw-r--r--arch/arm/mach-cns3xxx/core.h23
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/cns3xxx.h635
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/debug-macro.S21
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/entry-macro.S82
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/hardware.h22
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/io.h17
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/irqs.h24
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/memory.h26
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/system.h29
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/timex.h12
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/uncompress.h55
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/vmalloc.h11
-rw-r--r--arch/arm/mach-cns3xxx/pm.c86
17 files changed, 1300 insertions, 0 deletions
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
new file mode 100644
index 000000000000..20284cdcb18b
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -0,0 +1,4 @@
1menu "CNS3XXX platform type"
2 depends on ARCH_CNS3XXX
3
4endmenu
diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
new file mode 100644
index 000000000000..e5e76dd2111a
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o
diff --git a/arch/arm/mach-cns3xxx/Makefile.boot b/arch/arm/mach-cns3xxx/Makefile.boot
new file mode 100644
index 000000000000..777012865220
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00C00000
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
new file mode 100644
index 000000000000..9ca4d581016f
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -0,0 +1,249 @@
1/*
2 * Copyright 1999 - 2003 ARM Limited
3 * Copyright 2000 Deep Blue Solutions Ltd
4 * Copyright 2008 Cavium Networks
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/clockchips.h>
14#include <linux/io.h>
15#include <asm/mach/map.h>
16#include <asm/mach/time.h>
17#include <asm/mach/irq.h>
18#include <asm/hardware/gic.h>
19#include <mach/cns3xxx.h>
20#include "core.h"
21
22static struct map_desc cns3xxx_io_desc[] __initdata = {
23 {
24 .virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT,
25 .pfn = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE),
26 .length = SZ_4K,
27 .type = MT_DEVICE,
28 }, {
29 .virtual = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT,
30 .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE),
31 .length = SZ_4K,
32 .type = MT_DEVICE,
33 }, {
34 .virtual = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT,
35 .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE),
36 .length = SZ_4K,
37 .type = MT_DEVICE,
38 }, {
39 .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT,
40 .pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE),
41 .length = SZ_4K,
42 .type = MT_DEVICE,
43 }, {
44 .virtual = CNS3XXX_GPIOA_BASE_VIRT,
45 .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
46 .length = SZ_4K,
47 .type = MT_DEVICE,
48 }, {
49 .virtual = CNS3XXX_GPIOB_BASE_VIRT,
50 .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
51 .length = SZ_4K,
52 .type = MT_DEVICE,
53 }, {
54 .virtual = CNS3XXX_MISC_BASE_VIRT,
55 .pfn = __phys_to_pfn(CNS3XXX_MISC_BASE),
56 .length = SZ_4K,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = CNS3XXX_PM_BASE_VIRT,
60 .pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
61 .length = SZ_4K,
62 .type = MT_DEVICE,
63 },
64};
65
66void __init cns3xxx_map_io(void)
67{
68 iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
69}
70
71/* used by entry-macro.S */
72void __iomem *gic_cpu_base_addr;
73
74void __init cns3xxx_init_irq(void)
75{
76 gic_cpu_base_addr = __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT);
77 gic_dist_init(0, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), 29);
78 gic_cpu_init(0, gic_cpu_base_addr);
79}
80
81void cns3xxx_power_off(void)
82{
83 u32 __iomem *pm_base = __io(CNS3XXX_PM_BASE_VIRT);
84 u32 clkctrl;
85
86 printk(KERN_INFO "powering system down...\n");
87
88 clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET);
89 clkctrl &= 0xfffff1ff;
90 clkctrl |= (0x5 << 9); /* Hibernate */
91 writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET);
92
93}
94
95/*
96 * Timer
97 */
98static void __iomem *cns3xxx_tmr1;
99
100static void cns3xxx_timer_set_mode(enum clock_event_mode mode,
101 struct clock_event_device *clk)
102{
103 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
104 int pclk = cns3xxx_cpu_clock() / 8;
105 int reload;
106
107 switch (mode) {
108 case CLOCK_EVT_MODE_PERIODIC:
109 reload = pclk * 20 / (3 * HZ) * 0x25000;
110 writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
111 ctrl |= (1 << 0) | (1 << 2) | (1 << 9);
112 break;
113 case CLOCK_EVT_MODE_ONESHOT:
114 /* period set, and timer enabled in 'next_event' hook */
115 ctrl |= (1 << 2) | (1 << 9);
116 break;
117 case CLOCK_EVT_MODE_UNUSED:
118 case CLOCK_EVT_MODE_SHUTDOWN:
119 default:
120 ctrl = 0;
121 }
122
123 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
124}
125
126static int cns3xxx_timer_set_next_event(unsigned long evt,
127 struct clock_event_device *unused)
128{
129 unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
130
131 writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
132 writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
133
134 return 0;
135}
136
137static struct clock_event_device cns3xxx_tmr1_clockevent = {
138 .name = "cns3xxx timer1",
139 .shift = 8,
140 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
141 .set_mode = cns3xxx_timer_set_mode,
142 .set_next_event = cns3xxx_timer_set_next_event,
143 .rating = 350,
144 .cpumask = cpu_all_mask,
145};
146
147static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
148{
149 cns3xxx_tmr1_clockevent.irq = timer_irq;
150 cns3xxx_tmr1_clockevent.mult =
151 div_sc((cns3xxx_cpu_clock() >> 3) * 1000000, NSEC_PER_SEC,
152 cns3xxx_tmr1_clockevent.shift);
153 cns3xxx_tmr1_clockevent.max_delta_ns =
154 clockevent_delta2ns(0xffffffff, &cns3xxx_tmr1_clockevent);
155 cns3xxx_tmr1_clockevent.min_delta_ns =
156 clockevent_delta2ns(0xf, &cns3xxx_tmr1_clockevent);
157
158 clockevents_register_device(&cns3xxx_tmr1_clockevent);
159}
160
161/*
162 * IRQ handler for the timer
163 */
164static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id)
165{
166 struct clock_event_device *evt = &cns3xxx_tmr1_clockevent;
167 u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET;
168 u32 val;
169
170 /* Clear the interrupt */
171 val = readl(stat);
172 writel(val & ~(1 << 2), stat);
173
174 evt->event_handler(evt);
175
176 return IRQ_HANDLED;
177}
178
179static struct irqaction cns3xxx_timer_irq = {
180 .name = "timer",
181 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
182 .handler = cns3xxx_timer_interrupt,
183};
184
185/*
186 * Set up the clock source and clock events devices
187 */
188static void __init __cns3xxx_timer_init(unsigned int timer_irq)
189{
190 u32 val;
191 u32 irq_mask;
192
193 /*
194 * Initialise to a known state (all timers off)
195 */
196
197 /* disable timer1 and timer2 */
198 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
199 /* stop free running timer3 */
200 writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET);
201
202 /* timer1 */
203 writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET);
204 writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET);
205
206 writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET);
207 writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET);
208
209 /* mask irq, non-mask timer1 overflow */
210 irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
211 irq_mask &= ~(1 << 2);
212 irq_mask |= 0x03;
213 writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
214
215 /* down counter */
216 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
217 val |= (1 << 9);
218 writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
219
220 /* timer2 */
221 writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET);
222 writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET);
223
224 /* mask irq */
225 irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
226 irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5));
227 writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET);
228
229 /* down counter */
230 val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
231 val |= (1 << 10);
232 writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET);
233
234 /* Make irqs happen for the system timer */
235 setup_irq(timer_irq, &cns3xxx_timer_irq);
236
237 cns3xxx_clockevents_init(timer_irq);
238}
239
240static void __init cns3xxx_timer_init(void)
241{
242 cns3xxx_tmr1 = __io(CNS3XXX_TIMER1_2_3_BASE_VIRT);
243
244 __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0);
245}
246
247struct sys_timer cns3xxx_timer = {
248 .init = cns3xxx_timer_init,
249};
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
new file mode 100644
index 000000000000..6b33ec11346e
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -0,0 +1,23 @@
1/*
2 * Copyright 2000 Deep Blue Solutions Ltd
3 * Copyright 2004 ARM Limited
4 * Copyright 2008 Cavium Networks
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __CNS3XXX_CORE_H
12#define __CNS3XXX_CORE_H
13
14extern void __iomem *gic_cpu_base_addr;
15extern struct sys_timer cns3xxx_timer;
16
17void __init cns3xxx_map_io(void);
18void __init cns3xxx_init_irq(void);
19void cns3xxx_power_off(void);
20void cns3xxx_pwr_power_up(unsigned int block);
21void cns3xxx_pwr_power_down(unsigned int block);
22
23#endif /* __CNS3XXX_CORE_H */
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
new file mode 100644
index 000000000000..8a2f5a21d4ee
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -0,0 +1,635 @@
1/*
2 * Copyright 2008 Cavium Networks
3 *
4 * This file is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License, Version 2, as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __MACH_BOARD_CNS3XXXH
10#define __MACH_BOARD_CNS3XXXH
11
12/*
13 * Memory map
14 */
15#define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */
16#define CNS3XXX_FLASH_SIZE SZ_256M
17
18#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */
19
20#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */
21
22#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */
23#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000
24
25#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */
26#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000
27
28#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */
29#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000
30
31#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */
32#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000
33
34#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */
35#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000
36
37#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */
38#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000
39
40#define SMC_MEMC_STATUS_OFFSET 0x000
41#define SMC_MEMIF_CFG_OFFSET 0x004
42#define SMC_MEMC_CFG_SET_OFFSET 0x008
43#define SMC_MEMC_CFG_CLR_OFFSET 0x00C
44#define SMC_DIRECT_CMD_OFFSET 0x010
45#define SMC_SET_CYCLES_OFFSET 0x014
46#define SMC_SET_OPMODE_OFFSET 0x018
47#define SMC_REFRESH_PERIOD_0_OFFSET 0x020
48#define SMC_REFRESH_PERIOD_1_OFFSET 0x024
49#define SMC_SRAM_CYCLES0_0_OFFSET 0x100
50#define SMC_NAND_CYCLES0_0_OFFSET 0x100
51#define SMC_OPMODE0_0_OFFSET 0x104
52#define SMC_SRAM_CYCLES0_1_OFFSET 0x120
53#define SMC_NAND_CYCLES0_1_OFFSET 0x120
54#define SMC_OPMODE0_1_OFFSET 0x124
55#define SMC_USER_STATUS_OFFSET 0x200
56#define SMC_USER_CONFIG_OFFSET 0x204
57#define SMC_ECC_STATUS_OFFSET 0x300
58#define SMC_ECC_MEMCFG_OFFSET 0x304
59#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308
60#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C
61#define SMC_ECC_ADDR0_OFFSET 0x310
62#define SMC_ECC_ADDR1_OFFSET 0x314
63#define SMC_ECC_VALUE0_OFFSET 0x318
64#define SMC_ECC_VALUE1_OFFSET 0x31C
65#define SMC_ECC_VALUE2_OFFSET 0x320
66#define SMC_ECC_VALUE3_OFFSET 0x324
67#define SMC_PERIPH_ID_0_OFFSET 0xFE0
68#define SMC_PERIPH_ID_1_OFFSET 0xFE4
69#define SMC_PERIPH_ID_2_OFFSET 0xFE8
70#define SMC_PERIPH_ID_3_OFFSET 0xFEC
71#define SMC_PCELL_ID_0_OFFSET 0xFF0
72#define SMC_PCELL_ID_1_OFFSET 0xFF4
73#define SMC_PCELL_ID_2_OFFSET 0xFF8
74#define SMC_PCELL_ID_3_OFFSET 0xFFC
75
76#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
77#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000
78
79#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
80#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000
81
82#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
83#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000
84
85#define RTC_SEC_OFFSET 0x00
86#define RTC_MIN_OFFSET 0x04
87#define RTC_HOUR_OFFSET 0x08
88#define RTC_DAY_OFFSET 0x0C
89#define RTC_SEC_ALM_OFFSET 0x10
90#define RTC_MIN_ALM_OFFSET 0x14
91#define RTC_HOUR_ALM_OFFSET 0x18
92#define RTC_REC_OFFSET 0x1C
93#define RTC_CTRL_OFFSET 0x20
94#define RTC_INTR_STS_OFFSET 0x34
95
96#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */
97#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */
98
99#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */
100#define CNS3XXX_PM_BASE_VIRT 0xFFF08000
101
102#define PM_CLK_GATE_OFFSET 0x00
103#define PM_SOFT_RST_OFFSET 0x04
104#define PM_HS_CFG_OFFSET 0x08
105#define PM_CACTIVE_STA_OFFSET 0x0C
106#define PM_PWR_STA_OFFSET 0x10
107#define PM_SYS_CLK_CTRL_OFFSET 0x14
108#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18
109#define PM_PLL_HM_PD_OFFSET 0x1C
110
111#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */
112#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000
113
114#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
115#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000
116
117#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */
118#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000
119
120#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */
121#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000
122
123#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */
124#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000
125
126#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */
127#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000
128
129#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */
130#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000
131
132#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
133#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800
134
135#define TIMER1_COUNTER_OFFSET 0x00
136#define TIMER1_AUTO_RELOAD_OFFSET 0x04
137#define TIMER1_MATCH_V1_OFFSET 0x08
138#define TIMER1_MATCH_V2_OFFSET 0x0C
139
140#define TIMER2_COUNTER_OFFSET 0x10
141#define TIMER2_AUTO_RELOAD_OFFSET 0x14
142#define TIMER2_MATCH_V1_OFFSET 0x18
143#define TIMER2_MATCH_V2_OFFSET 0x1C
144
145#define TIMER1_2_CONTROL_OFFSET 0x30
146#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34
147#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38
148
149#define TIMER_FREERUN_OFFSET 0x40
150#define TIMER_FREERUN_CONTROL_OFFSET 0x44
151
152#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */
153#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000
154
155#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */
156#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000
157
158#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */
159#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000
160
161#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */
162#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000
163
164#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */
165#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000
166
167#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */
168#define CNS3XXX_USB_BASE_VIRT 0xFFF16000
169
170#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */
171#define CNS3XXX_SATA2_SIZE SZ_16M
172#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000
173
174#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */
175#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000
176
177#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */
178#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000
179
180#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */
181#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000
182
183#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */
184#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000
185
186#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */
187#define CNS3XXX_USB_OHCI_BASE_VIRT 0xFFF1C000
188
189#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
190#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000
191
192#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */
193#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000
194
195#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */
196#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000
197
198#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */
199#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000
200
201#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */
202#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000
203
204#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */
205#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000
206
207#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */
208#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000
209
210#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */
211#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000
212
213#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */
214#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000
215
216#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */
217#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000
218
219#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */
220#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000
221
222#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */
223#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000
224
225#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */
226#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000
227
228/*
229 * Testchip peripheral and fpga gic regions
230 */
231#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */
232#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000
233
234#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */
235#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100
236
237#define CNS3XXX_TC11MP_TWD_BASE 0x90000600
238#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600
239
240#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */
241#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000
242
243#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
244#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000
245
246/*
247 * Misc block
248 */
249#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
250#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset))))
251
252#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP_VALUE(0x00)
253#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP_VALUE(0x04)
254#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP_VALUE(0x08)
255#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP_VALUE(0x0C)
256#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP_VALUE(0x10)
257#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x14)
258#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP_VALUE(0x18)
259#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP_VALUE(0x1C)
260#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP_VALUE(0x20)
261#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x24)
262#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x28)
263#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x2C)
264#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x30)
265#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP_VALUE(0x34)
266#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP_VALUE(0x40)
267#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP_VALUE(0x44)
268#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP_VALUE(0x48)
269#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP_VALUE(0x4C)
270#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP_VALUE(0x50)
271#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP_VALUE(0x54)
272
273#define MISC_SATA_POWER_MODE MISC_MEM_MAP_VALUE(0x310)
274
275#define MISC_USB_CFG_REG MISC_MEM_MAP_VALUE(0x800)
276#define MISC_USB_STS_REG MISC_MEM_MAP_VALUE(0x804)
277#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP_VALUE(0x808)
278#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP_VALUE(0x80c)
279#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP_VALUE(0x810)
280#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP_VALUE(0x814)
281
282#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004)
283#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100)
284#define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100)
285#define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100)
286#define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100)
287#define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100)
288#define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100)
289#define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100)
290#define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100)
291#define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100)
292#define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100)
293#define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100)
294#define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100)
295#define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100)
296#define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100)
297#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
298#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
299
300/*
301 * Power management and clock control
302 */
303#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset))))
304
305#define PM_CLK_GATE_REG PMU_REG_VALUE(0x000)
306#define PM_SOFT_RST_REG PMU_REG_VALUE(0x004)
307#define PM_HS_CFG_REG PMU_REG_VALUE(0x008)
308#define PM_CACTIVE_STA_REG PMU_REG_VALUE(0x00C)
309#define PM_PWR_STA_REG PMU_REG_VALUE(0x010)
310#define PM_CLK_CTRL_REG PMU_REG_VALUE(0x014)
311#define PM_PLL_LCD_I2S_CTRL_REG PMU_REG_VALUE(0x018)
312#define PM_PLL_HM_PD_CTRL_REG PMU_REG_VALUE(0x01C)
313#define PM_REGULAT_CTRL_REG PMU_REG_VALUE(0x020)
314#define PM_WDT_CTRL_REG PMU_REG_VALUE(0x024)
315#define PM_WU_CTRL0_REG PMU_REG_VALUE(0x028)
316#define PM_WU_CTRL1_REG PMU_REG_VALUE(0x02C)
317#define PM_CSR_REG PMU_REG_VALUE(0x030)
318
319/* PM_CLK_GATE_REG */
320#define PM_CLK_GATE_REG_OFFSET_SDIO (25)
321#define PM_CLK_GATE_REG_OFFSET_GPU (24)
322#define PM_CLK_GATE_REG_OFFSET_CIM (23)
323#define PM_CLK_GATE_REG_OFFSET_LCDC (22)
324#define PM_CLK_GATE_REG_OFFSET_I2S (21)
325#define PM_CLK_GATE_REG_OFFSET_RAID (20)
326#define PM_CLK_GATE_REG_OFFSET_SATA (19)
327#define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x))
328#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16)
329#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15)
330#define PM_CLK_GATE_REG_OFFSET_TIMER (14)
331#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13)
332#define PM_CLK_GATE_REG_OFFSET_HCIE (12)
333#define PM_CLK_GATE_REG_OFFSET_SWITCH (11)
334#define PM_CLK_GATE_REG_OFFSET_GPIO (10)
335#define PM_CLK_GATE_REG_OFFSET_UART3 (9)
336#define PM_CLK_GATE_REG_OFFSET_UART2 (8)
337#define PM_CLK_GATE_REG_OFFSET_UART1 (7)
338#define PM_CLK_GATE_REG_OFFSET_RTC (5)
339#define PM_CLK_GATE_REG_OFFSET_GDMA (4)
340#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3)
341#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1)
342#define PM_CLK_GATE_REG_MASK (0x03FFFFBA)
343
344/* PM_SOFT_RST_REG */
345#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31)
346#define PM_SOFT_RST_REG_OFFST_CPU1 (29)
347#define PM_SOFT_RST_REG_OFFST_CPU0 (28)
348#define PM_SOFT_RST_REG_OFFST_SDIO (25)
349#define PM_SOFT_RST_REG_OFFST_GPU (24)
350#define PM_SOFT_RST_REG_OFFST_CIM (23)
351#define PM_SOFT_RST_REG_OFFST_LCDC (22)
352#define PM_SOFT_RST_REG_OFFST_I2S (21)
353#define PM_SOFT_RST_REG_OFFST_RAID (20)
354#define PM_SOFT_RST_REG_OFFST_SATA (19)
355#define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x))
356#define PM_SOFT_RST_REG_OFFST_USB_HOST (16)
357#define PM_SOFT_RST_REG_OFFST_USB_OTG (15)
358#define PM_SOFT_RST_REG_OFFST_TIMER (14)
359#define PM_SOFT_RST_REG_OFFST_CRYPTO (13)
360#define PM_SOFT_RST_REG_OFFST_HCIE (12)
361#define PM_SOFT_RST_REG_OFFST_SWITCH (11)
362#define PM_SOFT_RST_REG_OFFST_GPIO (10)
363#define PM_SOFT_RST_REG_OFFST_UART3 (9)
364#define PM_SOFT_RST_REG_OFFST_UART2 (8)
365#define PM_SOFT_RST_REG_OFFST_UART1 (7)
366#define PM_SOFT_RST_REG_OFFST_RTC (5)
367#define PM_SOFT_RST_REG_OFFST_GDMA (4)
368#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3)
369#define PM_SOFT_RST_REG_OFFST_DMC (2)
370#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1)
371#define PM_SOFT_RST_REG_OFFST_GLOBAL (0)
372#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF)
373
374/* PMHS_CFG_REG */
375#define PM_HS_CFG_REG_OFFSET_SDIO (25)
376#define PM_HS_CFG_REG_OFFSET_GPU (24)
377#define PM_HS_CFG_REG_OFFSET_CIM (23)
378#define PM_HS_CFG_REG_OFFSET_LCDC (22)
379#define PM_HS_CFG_REG_OFFSET_I2S (21)
380#define PM_HS_CFG_REG_OFFSET_RAID (20)
381#define PM_HS_CFG_REG_OFFSET_SATA (19)
382#define PM_HS_CFG_REG_OFFSET_PCIE1 (18)
383#define PM_HS_CFG_REG_OFFSET_PCIE0 (17)
384#define PM_HS_CFG_REG_OFFSET_USB_HOST (16)
385#define PM_HS_CFG_REG_OFFSET_USB_OTG (15)
386#define PM_HS_CFG_REG_OFFSET_TIMER (14)
387#define PM_HS_CFG_REG_OFFSET_CRYPTO (13)
388#define PM_HS_CFG_REG_OFFSET_HCIE (12)
389#define PM_HS_CFG_REG_OFFSET_SWITCH (11)
390#define PM_HS_CFG_REG_OFFSET_GPIO (10)
391#define PM_HS_CFG_REG_OFFSET_UART3 (9)
392#define PM_HS_CFG_REG_OFFSET_UART2 (8)
393#define PM_HS_CFG_REG_OFFSET_UART1 (7)
394#define PM_HS_CFG_REG_OFFSET_RTC (5)
395#define PM_HS_CFG_REG_OFFSET_GDMA (4)
396#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3)
397#define PM_HS_CFG_REG_OFFSET_DMC (2)
398#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1)
399#define PM_HS_CFG_REG_MASK (0x03FFFFBE)
400#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806)
401
402/* PM_CACTIVE_STA_REG */
403#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25)
404#define PM_CACTIVE_STA_REG_OFFSET_GPU (24)
405#define PM_CACTIVE_STA_REG_OFFSET_CIM (23)
406#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22)
407#define PM_CACTIVE_STA_REG_OFFSET_I2S (21)
408#define PM_CACTIVE_STA_REG_OFFSET_RAID (20)
409#define PM_CACTIVE_STA_REG_OFFSET_SATA (19)
410#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18)
411#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17)
412#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16)
413#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15)
414#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14)
415#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13)
416#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12)
417#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11)
418#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10)
419#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9)
420#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8)
421#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7)
422#define PM_CACTIVE_STA_REG_OFFSET_RTC (5)
423#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4)
424#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3)
425#define PM_CACTIVE_STA_REG_OFFSET_DMC (2)
426#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1)
427#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE)
428
429/* PM_PWR_STA_REG */
430#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25)
431#define PM_PWR_STA_REG_REG_OFFSET_GPU (24)
432#define PM_PWR_STA_REG_REG_OFFSET_CIM (23)
433#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22)
434#define PM_PWR_STA_REG_REG_OFFSET_I2S (21)
435#define PM_PWR_STA_REG_REG_OFFSET_RAID (20)
436#define PM_PWR_STA_REG_REG_OFFSET_SATA (19)
437#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18)
438#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17)
439#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16)
440#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15)
441#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14)
442#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13)
443#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12)
444#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11)
445#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10)
446#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9)
447#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8)
448#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7)
449#define PM_PWR_STA_REG_REG_OFFSET_RTC (5)
450#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4)
451#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3)
452#define PM_PWR_STA_REG_REG_OFFSET_DMC (2)
453#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1)
454#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE)
455
456/* PM_CLK_CTRL_REG */
457#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31)
458#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30)
459#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29)
460#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28)
461#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27)
462#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24)
463#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22)
464#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20)
465#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16)
466#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14)
467#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12)
468#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9)
469#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7)
470#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6)
471#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4)
472#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0)
473
474#define PM_CPU_CLK_DIV(DIV) { \
475 PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
476 PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \
477}
478
479#define PM_PLL_CPU_SEL(CPU) { \
480 PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
481 PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \
482}
483
484/* PM_PLL_LCD_I2S_CTRL_REG */
485#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22)
486#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17)
487#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11)
488#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3)
489#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0)
490
491/* PM_PLL_HM_PD_CTRL_REG */
492#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11)
493#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10)
494#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6)
495#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5)
496#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4)
497#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3)
498#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2)
499#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C)
500
501/* PM_WDT_CTRL_REG */
502#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0)
503
504/* PM_CSR_REG - Clock Scaling Register*/
505#define PM_CSR_REG_OFFSET_CSR_EN (30)
506#define PM_CSR_REG_OFFSET_CSR_NUM (0)
507
508#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1<<PM_CLK_GATE_REG_OFFSET_##BLOCK)
509
510/* Software reset*/
511#define CNS3XXX_PWR_SOFTWARE_RST(BLOCK) (0x1<<PM_SOFT_RST_REG_OFFST_##BLOCK)
512
513/*
514 * CNS3XXX support several power saving mode as following,
515 * DFS, IDLE, HALT, DOZE, SLEEP, Hibernate
516 */
517#define CNS3XXX_PWR_CPU_MODE_DFS (0)
518#define CNS3XXX_PWR_CPU_MODE_IDLE (1)
519#define CNS3XXX_PWR_CPU_MODE_HALT (2)
520#define CNS3XXX_PWR_CPU_MODE_DOZE (3)
521#define CNS3XXX_PWR_CPU_MODE_SLEEP (4)
522#define CNS3XXX_PWR_CPU_MODE_HIBERNATE (5)
523
524#define CNS3XXX_PWR_PLL(BLOCK) (0x1<<PM_PLL_HM_PD_CTRL_REG_OFFSET_##BLOCK)
525#define CNS3XXX_PWR_PLL_ALL PM_PLL_HM_PD_CTRL_REG_MASK
526
527/* Change CPU frequency and divider */
528#define CNS3XXX_PWR_PLL_CPU_300MHZ (0)
529#define CNS3XXX_PWR_PLL_CPU_333MHZ (1)
530#define CNS3XXX_PWR_PLL_CPU_366MHZ (2)
531#define CNS3XXX_PWR_PLL_CPU_400MHZ (3)
532#define CNS3XXX_PWR_PLL_CPU_433MHZ (4)
533#define CNS3XXX_PWR_PLL_CPU_466MHZ (5)
534#define CNS3XXX_PWR_PLL_CPU_500MHZ (6)
535#define CNS3XXX_PWR_PLL_CPU_533MHZ (7)
536#define CNS3XXX_PWR_PLL_CPU_566MHZ (8)
537#define CNS3XXX_PWR_PLL_CPU_600MHZ (9)
538#define CNS3XXX_PWR_PLL_CPU_633MHZ (10)
539#define CNS3XXX_PWR_PLL_CPU_666MHZ (11)
540#define CNS3XXX_PWR_PLL_CPU_700MHZ (12)
541
542#define CNS3XXX_PWR_CPU_CLK_DIV_BY1 (0)
543#define CNS3XXX_PWR_CPU_CLK_DIV_BY2 (1)
544#define CNS3XXX_PWR_CPU_CLK_DIV_BY4 (2)
545
546/* Change DDR2 frequency */
547#define CNS3XXX_PWR_PLL_DDR2_200MHZ (0)
548#define CNS3XXX_PWR_PLL_DDR2_266MHZ (1)
549#define CNS3XXX_PWR_PLL_DDR2_333MHZ (2)
550#define CNS3XXX_PWR_PLL_DDR2_400MHZ (3)
551
552void cns3xxx_pwr_soft_rst(unsigned int block);
553void cns3xxx_pwr_clk_en(unsigned int block);
554int cns3xxx_cpu_clock(void);
555
556/*
557 * ARM11 MPCore interrupt sources (primary GIC)
558 */
559#define IRQ_CNS3XXX_PMU (IRQ_TC11MP_GIC_START + 0)
560#define IRQ_CNS3XXX_SDIO (IRQ_TC11MP_GIC_START + 1)
561#define IRQ_CNS3XXX_L2CC (IRQ_TC11MP_GIC_START + 2)
562#define IRQ_CNS3XXX_RTC (IRQ_TC11MP_GIC_START + 3)
563#define IRQ_CNS3XXX_I2S (IRQ_TC11MP_GIC_START + 4)
564#define IRQ_CNS3XXX_PCM (IRQ_TC11MP_GIC_START + 5)
565#define IRQ_CNS3XXX_SPI (IRQ_TC11MP_GIC_START + 6)
566#define IRQ_CNS3XXX_I2C (IRQ_TC11MP_GIC_START + 7)
567#define IRQ_CNS3XXX_CIM (IRQ_TC11MP_GIC_START + 8)
568#define IRQ_CNS3XXX_GPU (IRQ_TC11MP_GIC_START + 9)
569#define IRQ_CNS3XXX_LCD (IRQ_TC11MP_GIC_START + 10)
570#define IRQ_CNS3XXX_GPIOA (IRQ_TC11MP_GIC_START + 11)
571#define IRQ_CNS3XXX_GPIOB (IRQ_TC11MP_GIC_START + 12)
572#define IRQ_CNS3XXX_UART0 (IRQ_TC11MP_GIC_START + 13)
573#define IRQ_CNS3XXX_UART1 (IRQ_TC11MP_GIC_START + 14)
574#define IRQ_CNS3XXX_UART2 (IRQ_TC11MP_GIC_START + 15)
575#define IRQ_CNS3XXX_ARM11 (IRQ_TC11MP_GIC_START + 16)
576
577#define IRQ_CNS3XXX_SW_STATUS (IRQ_TC11MP_GIC_START + 17)
578#define IRQ_CNS3XXX_SW_R0TXC (IRQ_TC11MP_GIC_START + 18)
579#define IRQ_CNS3XXX_SW_R0RXC (IRQ_TC11MP_GIC_START + 19)
580#define IRQ_CNS3XXX_SW_R0QE (IRQ_TC11MP_GIC_START + 20)
581#define IRQ_CNS3XXX_SW_R0QF (IRQ_TC11MP_GIC_START + 21)
582#define IRQ_CNS3XXX_SW_R1TXC (IRQ_TC11MP_GIC_START + 22)
583#define IRQ_CNS3XXX_SW_R1RXC (IRQ_TC11MP_GIC_START + 23)
584#define IRQ_CNS3XXX_SW_R1QE (IRQ_TC11MP_GIC_START + 24)
585#define IRQ_CNS3XXX_SW_R1QF (IRQ_TC11MP_GIC_START + 25)
586#define IRQ_CNS3XXX_SW_PPE (IRQ_TC11MP_GIC_START + 26)
587
588#define IRQ_CNS3XXX_CRYPTO (IRQ_TC11MP_GIC_START + 27)
589#define IRQ_CNS3XXX_HCIE (IRQ_TC11MP_GIC_START + 28)
590#define IRQ_CNS3XXX_PCIE0_DEVICE (IRQ_TC11MP_GIC_START + 29)
591#define IRQ_CNS3XXX_PCIE1_DEVICE (IRQ_TC11MP_GIC_START + 30)
592#define IRQ_CNS3XXX_USB_OTG (IRQ_TC11MP_GIC_START + 31)
593#define IRQ_CNS3XXX_USB_EHCI (IRQ_TC11MP_GIC_START + 32)
594#define IRQ_CNS3XXX_SATA (IRQ_TC11MP_GIC_START + 33)
595#define IRQ_CNS3XXX_RAID (IRQ_TC11MP_GIC_START + 34)
596#define IRQ_CNS3XXX_SMC (IRQ_TC11MP_GIC_START + 35)
597
598#define IRQ_CNS3XXX_DMAC_ABORT (IRQ_TC11MP_GIC_START + 36)
599#define IRQ_CNS3XXX_DMAC0 (IRQ_TC11MP_GIC_START + 37)
600#define IRQ_CNS3XXX_DMAC1 (IRQ_TC11MP_GIC_START + 38)
601#define IRQ_CNS3XXX_DMAC2 (IRQ_TC11MP_GIC_START + 39)
602#define IRQ_CNS3XXX_DMAC3 (IRQ_TC11MP_GIC_START + 40)
603#define IRQ_CNS3XXX_DMAC4 (IRQ_TC11MP_GIC_START + 41)
604#define IRQ_CNS3XXX_DMAC5 (IRQ_TC11MP_GIC_START + 42)
605#define IRQ_CNS3XXX_DMAC6 (IRQ_TC11MP_GIC_START + 43)
606#define IRQ_CNS3XXX_DMAC7 (IRQ_TC11MP_GIC_START + 44)
607#define IRQ_CNS3XXX_DMAC8 (IRQ_TC11MP_GIC_START + 45)
608#define IRQ_CNS3XXX_DMAC9 (IRQ_TC11MP_GIC_START + 46)
609#define IRQ_CNS3XXX_DMAC10 (IRQ_TC11MP_GIC_START + 47)
610#define IRQ_CNS3XXX_DMAC11 (IRQ_TC11MP_GIC_START + 48)
611#define IRQ_CNS3XXX_DMAC12 (IRQ_TC11MP_GIC_START + 49)
612#define IRQ_CNS3XXX_DMAC13 (IRQ_TC11MP_GIC_START + 50)
613#define IRQ_CNS3XXX_DMAC14 (IRQ_TC11MP_GIC_START + 51)
614#define IRQ_CNS3XXX_DMAC15 (IRQ_TC11MP_GIC_START + 52)
615#define IRQ_CNS3XXX_DMAC16 (IRQ_TC11MP_GIC_START + 53)
616#define IRQ_CNS3XXX_DMAC17 (IRQ_TC11MP_GIC_START + 54)
617
618#define IRQ_CNS3XXX_PCIE0_RC (IRQ_TC11MP_GIC_START + 55)
619#define IRQ_CNS3XXX_PCIE1_RC (IRQ_TC11MP_GIC_START + 56)
620#define IRQ_CNS3XXX_TIMER0 (IRQ_TC11MP_GIC_START + 57)
621#define IRQ_CNS3XXX_TIMER1 (IRQ_TC11MP_GIC_START + 58)
622#define IRQ_CNS3XXX_USB_OHCI (IRQ_TC11MP_GIC_START + 59)
623#define IRQ_CNS3XXX_TIMER2 (IRQ_TC11MP_GIC_START + 60)
624#define IRQ_CNS3XXX_EXTERNAL_PIN0 (IRQ_TC11MP_GIC_START + 61)
625#define IRQ_CNS3XXX_EXTERNAL_PIN1 (IRQ_TC11MP_GIC_START + 62)
626#define IRQ_CNS3XXX_EXTERNAL_PIN2 (IRQ_TC11MP_GIC_START + 63)
627
628#define NR_IRQS_CNS3XXX (IRQ_TC11MP_GIC_START + 64)
629
630#if !defined(NR_IRQS) || (NR_IRQS < NR_IRQS_CNS3XXX)
631#undef NR_IRQS
632#define NR_IRQS NR_IRQS_CNS3XXX
633#endif
634
635#endif /* __MACH_BOARD_CNS3XXX_H */
diff --git a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..d16ce7eb00e9
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
@@ -0,0 +1,21 @@
1/*
2 * Debugging macro include header
3 *
4 * Copyright 1994-1999 Russell King
5 * Copyright 2008 Cavium Networks
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This file is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License, Version 2, as
10 * published by the Free Software Foundation.
11 */
12
13 .macro addruart,rx
14 mrc p15, 0, \rx, c1, c0
15 tst \rx, #1 @ MMU enabled?
16 moveq \rx, #0x10000000
17 movne \rx, #0xf0000000 @ virtual base
18 orr \rx, \rx, #0x00009000
19 .endm
20
21#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..5e1c5545680f
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
@@ -0,0 +1,82 @@
1/*
2 * Low-level IRQ helper macros for Cavium Networks platforms
3 *
4 * Copyright 2008 Cavium Networks
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
9 */
10
11#include <mach/hardware.h>
12#include <asm/hardware/gic.h>
13
14 .macro disable_fiq
15 .endm
16
17 .macro get_irqnr_preamble, base, tmp
18 ldr \base, =gic_cpu_base_addr
19 ldr \base, [\base]
20 .endm
21
22 .macro arch_ret_to_user, tmp1, tmp2
23 .endm
24
25 /*
26 * The interrupt numbering scheme is defined in the
27 * interrupt controller spec. To wit:
28 *
29 * Interrupts 0-15 are IPI
30 * 16-28 are reserved
31 * 29-31 are local. We allow 30 to be used for the watchdog.
32 * 32-1020 are global
33 * 1021-1022 are reserved
34 * 1023 is "spurious" (no interrupt)
35 *
36 * For now, we ignore all local interrupts so only return an interrupt if it's
37 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
38 *
39 * A simple read from the controller will tell us the number of the highest
40 * priority enabled interrupt. We then just need to check whether it is in the
41 * valid range for an IRQ (30-1020 inclusive).
42 */
43
44 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
45
46 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
47
48 ldr \tmp, =1021
49
50 bic \irqnr, \irqstat, #0x1c00
51
52 cmp \irqnr, #29
53 cmpcc \irqnr, \irqnr
54 cmpne \irqnr, \tmp
55 cmpcs \irqnr, \irqnr
56
57 .endm
58
59 /* We assume that irqstat (the raw value of the IRQ acknowledge
60 * register) is preserved from the macro above.
61 * If there is an IPI, we immediately signal end of interrupt on the
62 * controller, since this requires the original irqstat value which
63 * we won't easily be able to recreate later.
64 */
65
66 .macro test_for_ipi, irqnr, irqstat, base, tmp
67 bic \irqnr, \irqstat, #0x1c00
68 cmp \irqnr, #16
69 strcc \irqstat, [\base, #GIC_CPU_EOI]
70 cmpcs \irqnr, \irqnr
71 .endm
72
73 /* As above, this assumes that irqstat and base are preserved.. */
74
75 .macro test_for_ltirq, irqnr, irqstat, base, tmp
76 bic \irqnr, \irqstat, #0x1c00
77 mov \tmp, #0
78 cmp \irqnr, #29
79 moveq \tmp, #1
80 streq \irqstat, [\base, #GIC_CPU_EOI]
81 cmp \tmp, #0
82 .endm
diff --git a/arch/arm/mach-cns3xxx/include/mach/hardware.h b/arch/arm/mach-cns3xxx/include/mach/hardware.h
new file mode 100644
index 000000000000..57e09836f9d7
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/hardware.h
@@ -0,0 +1,22 @@
1/*
2 * This file contains the hardware definitions of the Cavium Networks boards.
3 *
4 * Copyright 2003 ARM Limited.
5 * Copyright 2008 Cavium Networks
6 *
7 * This file is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, Version 2, as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __MACH_HARDWARE_H
13#define __MACH_HARDWARE_H
14
15#include <asm/sizes.h>
16
17/* macro to get at IO space when running virtually */
18#define PCIBIOS_MIN_IO 0x00000000
19#define PCIBIOS_MIN_MEM 0x00000000
20#define pcibios_assign_all_busses() 1
21
22#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/io.h b/arch/arm/mach-cns3xxx/include/mach/io.h
new file mode 100644
index 000000000000..33b6fc1ece7c
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/io.h
@@ -0,0 +1,17 @@
1/*
2 * Copyright 2008 Cavium Networks
3 * Copyright 2003 ARM Limited
4 *
5 * This file is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, Version 2, as
7 * published by the Free Software Foundation.
8 */
9#ifndef __MACH_IO_H
10#define __MACH_IO_H
11
12#define IO_SPACE_LIMIT 0xffffffff
13
14#define __io(a) __typesafe_io(a)
15#define __mem_pci(a) (a)
16
17#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/irqs.h b/arch/arm/mach-cns3xxx/include/mach/irqs.h
new file mode 100644
index 000000000000..2ab96f8085c8
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/irqs.h
@@ -0,0 +1,24 @@
1/*
2 * Copyright 2000 Deep Blue Solutions Ltd.
3 * Copyright 2003 ARM Limited
4 * Copyright 2008 Cavium Networks
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __MACH_IRQS_H
12#define __MACH_IRQS_H
13
14#define IRQ_LOCALTIMER 29
15#define IRQ_LOCALWDOG 30
16#define IRQ_TC11MP_GIC_START 32
17
18#include <mach/cns3xxx.h>
19
20#ifndef NR_IRQS
21#error "NR_IRQS not defined by the board-specific files"
22#endif
23
24#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/memory.h b/arch/arm/mach-cns3xxx/include/mach/memory.h
new file mode 100644
index 000000000000..3b6b769b7a27
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/memory.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright 2003 ARM Limited
3 * Copyright 2008 Cavium Networks
4 *
5 * This file is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, Version 2, as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef __MACH_MEMORY_H
11#define __MACH_MEMORY_H
12
13/*
14 * Physical DRAM offset.
15 */
16#define PHYS_OFFSET UL(0x00000000)
17
18#define __phys_to_bus(x) ((x) + PHYS_OFFSET)
19#define __bus_to_phys(x) ((x) - PHYS_OFFSET)
20
21#define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v))
22#define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b))
23#define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p))
24#define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b))
25
26#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/system.h b/arch/arm/mach-cns3xxx/include/mach/system.h
new file mode 100644
index 000000000000..58bb03ae3cf4
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/system.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright 2000 Deep Blue Solutions Ltd
3 * Copyright 2003 ARM Limited
4 * Copyright 2008 Cavium Networks
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __MACH_SYSTEM_H
12#define __MACH_SYSTEM_H
13
14#include <linux/io.h>
15#include <asm/proc-fns.h>
16#include <mach/hardware.h>
17
18static inline void arch_idle(void)
19{
20 /*
21 * This should do all the clock switching
22 * and wait for interrupt tricks
23 */
24 cpu_do_idle();
25}
26
27void arch_reset(char mode, const char *cmd);
28
29#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/timex.h b/arch/arm/mach-cns3xxx/include/mach/timex.h
new file mode 100644
index 000000000000..1fd04217cacb
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/timex.h
@@ -0,0 +1,12 @@
1/*
2 * Cavium Networks architecture timex specifications
3 *
4 * Copyright 2003 ARM Limited
5 * Copyright 2008 Cavium Networks
6 *
7 * This file is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, Version 2, as
9 * published by the Free Software Foundation.
10 */
11
12#define CLOCK_TICK_RATE (50000000 / 16)
diff --git a/arch/arm/mach-cns3xxx/include/mach/uncompress.h b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
new file mode 100644
index 000000000000..de8ead9b91f7
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/uncompress.h
@@ -0,0 +1,55 @@
1/*
2 * Copyright 2003 ARM Limited
3 * Copyright 2008 Cavium Networks
4 *
5 * This file is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, Version 2, as
7 * published by the Free Software Foundation.
8 */
9
10#include <asm/mach-types.h>
11#include <mach/hardware.h>
12#include <mach/cns3xxx.h>
13
14#define AMBA_UART_DR(base) (*(volatile unsigned char *)((base) + 0x00))
15#define AMBA_UART_LCRH(base) (*(volatile unsigned char *)((base) + 0x2c))
16#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
17#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
18
19/*
20 * Return the UART base address
21 */
22static inline unsigned long get_uart_base(void)
23{
24 if (machine_is_cns3420vb())
25 return CNS3XXX_UART0_BASE;
26 else
27 return 0;
28}
29
30/*
31 * This does not append a newline
32 */
33static inline void putc(int c)
34{
35 unsigned long base = get_uart_base();
36
37 while (AMBA_UART_FR(base) & (1 << 5))
38 barrier();
39
40 AMBA_UART_DR(base) = c;
41}
42
43static inline void flush(void)
44{
45 unsigned long base = get_uart_base();
46
47 while (AMBA_UART_FR(base) & (1 << 3))
48 barrier();
49}
50
51/*
52 * nothing to do
53 */
54#define arch_decomp_setup()
55#define arch_decomp_wdog()
diff --git a/arch/arm/mach-cns3xxx/include/mach/vmalloc.h b/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..4d381ec05278
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
@@ -0,0 +1,11 @@
1/*
2 * Copyright 2000 Russell King.
3 * Copyright 2003 ARM Limited
4 * Copyright 2008 Cavium Networks
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
9 */
10
11#define VMALLOC_END 0xd8000000
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
new file mode 100644
index 000000000000..725e1a4fc231
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -0,0 +1,86 @@
1/*
2 * Copyright 2008 Cavium Networks
3 *
4 * This file is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License, Version 2, as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/delay.h>
10#include <mach/system.h>
11#include <mach/cns3xxx.h>
12
13void cns3xxx_pwr_clk_en(unsigned int block)
14{
15 PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK);
16}
17
18void cns3xxx_pwr_power_up(unsigned int block)
19{
20 PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL);
21
22 /* Wait for 300us for the PLL output clock locked. */
23 udelay(300);
24};
25
26void cns3xxx_pwr_power_down(unsigned int block)
27{
28 /* write '1' to power down */
29 PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL);
30};
31
32static void cns3xxx_pwr_soft_rst_force(unsigned int block)
33{
34 /*
35 * bit 0, 28, 29 => program low to reset,
36 * the other else program low and then high
37 */
38 if (block & 0x30000001) {
39 PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
40 } else {
41 PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
42 PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK);
43 }
44}
45
46void cns3xxx_pwr_soft_rst(unsigned int block)
47{
48 static unsigned int soft_reset;
49
50 if (soft_reset & block) {
51 /* SPI/I2C/GPIO use the same block, reset once. */
52 return;
53 } else {
54 soft_reset |= block;
55 }
56 cns3xxx_pwr_soft_rst_force(block);
57}
58
59void arch_reset(char mode, const char *cmd)
60{
61 /*
62 * To reset, we hit the on-board reset register
63 * in the system FPGA.
64 */
65 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
66}
67
68/*
69 * cns3xxx_cpu_clock - return CPU/L2 clock
70 * aclk: cpu clock/2
71 * hclk: cpu clock/4
72 * pclk: cpu clock/8
73 */
74int cns3xxx_cpu_clock(void)
75{
76 int cpu;
77 int cpu_sel;
78 int div_sel;
79
80 cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
81 div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
82
83 cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
84
85 return cpu;
86}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 00:28:57 -0500