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authorKimball Murray <kimball.murray@gmail.com>2006-05-08 09:17:16 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-05-08 12:34:56 -0400
commite0c1e9bf81badc7ba59e120d6218101903d5d103 (patch)
tree78f53a42795c935ff7a212d479c3fc00f0357ea3 /arch/arm/mach-clps7500
parentabfd3057187812352cd8502c29ca50cd010b3ccc (diff)
[PATCH] x86_64: avoid IRQ0 ioapic pin collision
The patch addresses a problem with ACPI SCI interrupt entry, which gets re-used, and the IRQ is assigned to another unrelated device. The patch corrects the code such that SCI IRQ is skipped and duplicate entry is avoided. Second issue came up with VIA chipset, the problem was caused by original patch assigning IRQs starting 16 and up. The VIA chipset uses 4-bit IRQ register for internal interrupt routing, and therefore cannot handle IRQ numbers assigned to its devices. The patch corrects this problem by allowing PCI IRQs below 16. Cc: len.brown@intel.com Signed-off by: Natalie Protasevich <Natalie.Protasevich@unisys.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/arm/mach-clps7500')
0 files changed, 0 insertions, 0 deletions