ARM: clps711x: autcpu12: Special driver for handling NAND memory is removed

This patch provide migration to using "gpio-nand" and "basic-mmio-gpio"
drivers instead of using special driver for handling NAND memory.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Olof Johansson <olof@lixom.net>

2 files changed, 98 insertions, 10 deletions

diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c
index 3de19554d800..3fbf43f72589 100644
--- a/arch/arm/mach-clps711x/autcpu12.c
+++ b/arch/arm/mach-clps711x/autcpu12.c
@@ -23,9 +23,13 @@
 #include <linux/string.h>
 #include <linux/mm.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand-gpio.h>
 #include <linux/platform_device.h>
+#include <linux/basic_mmio_gpio.h>
 
 #include <mach/hardware.h>
 #include <asm/sizes.h>
@@ -43,6 +47,15 @@
 #define AUTCPU12_CS8900_BASE    (CS2_PHYS_BASE + 0x300)
 #define AUTCPU12_CS8900_IRQ     (IRQ_EINT3)
 
+#define AUTCPU12_SMC_BASE       (CS1_PHYS_BASE + 0x06000000)
+#define AUTCPU12_SMC_SEL_BASE   (AUTCPU12_SMC_BASE + 0x10)
+
+#define AUTCPU12_MMGPIO_BASE    (CLPS711X_NR_GPIO)
+#define AUTCPU12_SMC_NCE        (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
+#define AUTCPU12_SMC_RDY        CLPS711X_GPIO(1, 2)
+#define AUTCPU12_SMC_ALE        CLPS711X_GPIO(1, 3)
+#define AUTCPU12_SMC_CLE        CLPS711X_GPIO(1, 3)
+
 static struct resource autcpu12_cs8900_resource[] __initdata = {
         DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
         DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
@@ -59,14 +72,98 @@ static struct platform_device autcpu12_nvram_pdev __initdata = {
         .num_resources  = ARRAY_SIZE(autcpu12_nvram_resource),
 };
 
+static struct resource autcpu12_nand_resource[] __initdata = {
+        DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16),
+};
+
+static struct mtd_partition autcpu12_nand_parts[] __initdata = {
+        {
+                .name   = "Flash partition 1",
+                .offset = 0,
+                .size   = SZ_8M,
+        },
+        {
+                .name   = "Flash partition 2",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static void __init autcpu12_adjust_parts(struct gpio_nand_platdata *pdata,
+                                         size_t sz)
+{
+        switch (sz) {
+        case SZ_16M:
+        case SZ_32M:
+                break;
+        case SZ_64M:
+        case SZ_128M:
+                pdata->parts[0].size = SZ_16M;
+                break;
+        default:
+                pr_warn("Unsupported SmartMedia device size %u\n", sz);
+                break;
+        }
+}
+
+static struct gpio_nand_platdata autcpu12_nand_pdata __initdata = {
+        .gpio_rdy       = AUTCPU12_SMC_RDY,
+        .gpio_nce       = AUTCPU12_SMC_NCE,
+        .gpio_ale       = AUTCPU12_SMC_ALE,
+        .gpio_cle       = AUTCPU12_SMC_CLE,
+        .gpio_nwp       = -1,
+        .chip_delay     = 20,
+        .parts          = autcpu12_nand_parts,
+        .num_parts      = ARRAY_SIZE(autcpu12_nand_parts),
+        .adjust_parts   = autcpu12_adjust_parts,
+};
+
+static struct platform_device autcpu12_nand_pdev __initdata = {
+        .name           = "gpio-nand",
+        .id             = -1,
+        .resource       = autcpu12_nand_resource,
+        .num_resources  = ARRAY_SIZE(autcpu12_nand_resource),
+        .dev            = {
+                .platform_data = &autcpu12_nand_pdata,
+        },
+};
+
+static struct resource autcpu12_mmgpio_resource[] __initdata = {
+        DEFINE_RES_MEM_NAMED(AUTCPU12_SMC_SEL_BASE, SZ_1, "dat"),
+};
+
+static struct bgpio_pdata autcpu12_mmgpio_pdata __initdata = {
+        .base   = AUTCPU12_MMGPIO_BASE,
+        .ngpio  = 8,
+};
+
+static struct platform_device autcpu12_mmgpio_pdev __initdata = {
+        .name           = "basic-mmio-gpio",
+        .id             = -1,
+        .resource       = autcpu12_mmgpio_resource,
+        .num_resources  = ARRAY_SIZE(autcpu12_mmgpio_resource),
+        .dev            = {
+                .platform_data = &autcpu12_mmgpio_pdata,
+        },
+};
+
 static void __init autcpu12_init(void)
 {
         platform_device_register_simple("video-clps711x", 0, NULL, 0);
         platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
                                         ARRAY_SIZE(autcpu12_cs8900_resource));
+        platform_device_register(&autcpu12_mmgpio_pdev);
         platform_device_register(&autcpu12_nvram_pdev);
 }
 
+static void __init autcpu12_init_late(void)
+{
+        if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) {
+                /* We are need both drivers to handle NAND */
+                platform_device_register(&autcpu12_nand_pdev);
+        }
+}
+
 MACHINE_START(AUTCPU12, "autronix autcpu12")
         /* Maintainer: Thomas Gleixner */
         .atag_offset    = 0x20000,
@@ -75,6 +172,7 @@ MACHINE_START(AUTCPU12, "autronix autcpu12")
         .init_irq       = clps711x_init_irq,
         .timer          = &clps711x_timer,
         .init_machine   = autcpu12_init,
+        .init_late      = autcpu12_init_late,
         .handle_irq     = clps711x_handle_irq,
         .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/include/mach/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h
index b077abd8a475..0452f5f3f034 100644
--- a/arch/arm/mach-clps711x/include/mach/autcpu12.h
+++ b/arch/arm/mach-clps711x/include/mach/autcpu12.h
@@ -40,8 +40,6 @@
 
 #define AUTCPU12_PHYS_CSAUX1            CS1_PHYS_BASE +0x04000000  /* physical */
 
-#define AUTCPU12_PHYS_SMC               CS1_PHYS_BASE +0x06000000  /* physical */
-
 #define AUTCPU12_PHYS_CAN               CS1_PHYS_BASE +0x08000000  /* physical */
 
 #define AUTCPU12_PHYS_TOUCH             CS1_PHYS_BASE +0x0A000000  /* physical */
@@ -50,14 +48,6 @@
 
 #define AUTCPU12_PHYS_LPT               CS1_PHYS_BASE +0x0E000000  /* physical */
 
-/* 
-* defines for smartmedia card access 
-*/
-#define AUTCPU12_SMC_RDY                (1<<2)
-#define AUTCPU12_SMC_ALE                (1<<3)
-#define AUTCPU12_SMC_CLE                (1<<4)
-#define AUTCPU12_SMC_PORT_OFFSET        PBDR
-#define AUTCPU12_SMC_SELECT_OFFSET      0x10
 /*
 * defines for lcd contrast 
 */