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authorAlexander Shiyan <shc_work@mail.ru>2012-08-21 12:59:34 -0400
committerArnd Bergmann <arnd@arndb.de>2012-09-28 15:14:07 -0400
commit7255f87a7169689be2d4722375744a1f932d4b28 (patch)
tree2b3e5f54e62ebdaa04cbb0199a1becddfb6c9b4e /arch/arm/mach-clps711x
parent61ae48c3cb6bcffd1c7e18164c3d103eb62f06aa (diff)
ARM: clps711x: Fix lowlevel debug-macro
CTS signal can not be used for the port and tied to any logic state. In this case we have an infinite loop waiting for the signal. For fix this problem, checking CTS removed, waiting for the signal "busy" was postponed after the byte write to the port. Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Diffstat (limited to 'arch/arm/mach-clps711x')
-rw-r--r--arch/arm/mach-clps711x/include/mach/debug-macro.S8
1 files changed, 1 insertions, 7 deletions
diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S
index 118b3d930573..cb3684f8dae0 100644
--- a/arch/arm/mach-clps711x/include/mach/debug-macro.S
+++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S
@@ -28,17 +28,11 @@
28 .endm 28 .endm
29 29
30 .macro waituart,rd,rx 30 .macro waituart,rd,rx
311001: ldr \rd, [\rx, #0x0140] @ SYSFLGx
32 tst \rd, #1 << 11 @ UBUSYx
33 bne 1001b
34 .endm 31 .endm
35 32
36 .macro busyuart,rd,rx 33 .macro busyuart,rd,rx
37 tst \rx, #0x1000 @ UART2 does not have CTS here
38 bne 1002f
391001: ldr \rd, [\rx, #0x0140] @ SYSFLGx 341001: ldr \rd, [\rx, #0x0140] @ SYSFLGx
40 tst \rd, #1 << 8 @ CTS 35 tst \rd, #1 << 11 @ UBUSYx
41 bne 1001b 36 bne 1001b
421002:
43 .endm 37 .endm
44 38