Merge commit 'linux-2.6/master' (early part) into oprofile/core

This branch depends on these apic patches:

      apic, x86: Use BIOS settings for IBS and MCE threshold interrupt LVT offsets
      apic, x86: Check if EILVT APIC registers are available (AMD only)

Signed-off-by: Robert Richter <robert.richter@amd.com>

1 files changed, 3 insertions, 3 deletions

diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
index dc1c4939b0ce..e3152631eb37 100644
--- a/arch/arm/mach-bcmring/irq.c
+++ b/arch/arm/mach-bcmring/irq.c
@@ -67,21 +67,21 @@ static void bcmring_unmask_irq2(unsigned int irq)
 }
 
 static struct irq_chip bcmring_irq0_chip = {
-        .typename = "ARM-INTC0",
+        .name = "ARM-INTC0",
         .ack = bcmring_mask_irq0,
         .mask = bcmring_mask_irq0,      /* mask a specific interrupt, blocking its delivery. */
         .unmask = bcmring_unmask_irq0,  /* unmaks an interrupt */
 };
 
 static struct irq_chip bcmring_irq1_chip = {
-        .typename = "ARM-INTC1",
+        .name = "ARM-INTC1",
         .ack = bcmring_mask_irq1,
         .mask = bcmring_mask_irq1,
         .unmask = bcmring_unmask_irq1,
 };
 
 static struct irq_chip bcmring_irq2_chip = {
-        .typename = "ARM-SINTC",
+        .name = "ARM-SINTC",
         .ack = bcmring_mask_irq2,
         .mask = bcmring_mask_irq2,
         .unmask = bcmring_unmask_irq2,