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authorLeo Chen <leochen@broadcom.com>2009-08-07 14:59:04 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-08-15 11:01:39 -0400
commitb7462d654f623738b4b3e03cff20f68b5b9a77f5 (patch)
tree4c3bdac52dd12b179b3cee85265b783955a9bc09 /arch/arm/mach-bcmring/include
parent278a6752e869b0f4a03ce5ac0588b31b50712903 (diff)
ARM: 5645/1: bcmring: add bcmring irq.c
init irq and handler add irq controller register file and header files Signed-off-by: Leo Chen <leochen@broadcom.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-bcmring/include')
-rw-r--r--arch/arm/mach-bcmring/include/csp/intcHw.h40
-rw-r--r--arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h246
-rw-r--r--arch/arm/mach-bcmring/include/mach/irqs.h132
3 files changed, 418 insertions, 0 deletions
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h
new file mode 100644
index 000000000000..1c639c8ee08f
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/intcHw.h
@@ -0,0 +1,40 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15
16/****************************************************************************/
17/**
18* @file intcHw.h
19*
20* @brief generic interrupt controller API
21*
22* @note
23* None
24*/
25/****************************************************************************/
26
27#ifndef _INTCHW_H
28#define _INTCHW_H
29
30/* ---- Include Files ---------------------------------------------------- */
31#include <mach/csp/intcHw_reg.h>
32
33/* ---- Public Constants and Types --------------------------------------- */
34/* ---- Public Variable Externs ------------------------------------------ */
35/* ---- Public Function Prototypes --------------------------------------- */
36static inline void intcHw_irq_disable(void *basep, uint32_t mask);
37static inline void intcHw_irq_enable(void *basep, uint32_t mask);
38
39#endif /* _INTCHW_H */
40
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
new file mode 100644
index 000000000000..e01fc4607c91
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
@@ -0,0 +1,246 @@
1/*****************************************************************************
2* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15/****************************************************************************/
16/**
17* @file intcHw_reg.h
18*
19* @brief platform specific interrupt controller bit assignments
20*
21* @note
22* None
23*/
24/****************************************************************************/
25
26#ifndef _INTCHW_REG_H
27#define _INTCHW_REG_H
28
29/* ---- Include Files ---------------------------------------------------- */
30#include <csp/stdint.h>
31#include <csp/reg.h>
32#include <mach/csp/mm_io.h>
33
34/* ---- Public Constants and Types --------------------------------------- */
35
36#define INTCHW_NUM_IRQ_PER_INTC 32 /* Maximum number of interrupt controllers */
37#define INTCHW_NUM_INTC 3
38
39/* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
40#define INTCHW_INTC0 ((void *)MM_IO_BASE_INTC0)
41#define INTCHW_INTC1 ((void *)MM_IO_BASE_INTC1)
42#define INTCHW_SINTC ((void *)MM_IO_BASE_SINTC)
43
44/* INTC0 - interrupt controller 0 */
45#define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */
46#define INTCHW_INTC0_CLCD_BITNUM 30 /* LCD Controller interrupt */
47#define INTCHW_INTC0_GE_BITNUM 29 /* Graphic engine interrupt */
48#define INTCHW_INTC0_APM_BITNUM 28 /* Audio process module interrupt */
49#define INTCHW_INTC0_ESW_BITNUM 27 /* Ethernet switch interrupt */
50#define INTCHW_INTC0_SPIH_BITNUM 26 /* SPI host interrupt */
51#define INTCHW_INTC0_TIMER3_BITNUM 25 /* Timer3 interrupt */
52#define INTCHW_INTC0_TIMER2_BITNUM 24 /* Timer2 interrupt */
53#define INTCHW_INTC0_TIMER1_BITNUM 23 /* Timer1 interrupt */
54#define INTCHW_INTC0_TIMER0_BITNUM 22 /* Timer0 interrupt */
55#define INTCHW_INTC0_SDIOH1_BITNUM 21 /* SDIO1 host interrupt */
56#define INTCHW_INTC0_SDIOH0_BITNUM 20 /* SDIO0 host interrupt */
57#define INTCHW_INTC0_USBD_BITNUM 19 /* USB device interrupt */
58#define INTCHW_INTC0_USBH1_BITNUM 18 /* USB1 host interrupt */
59#define INTCHW_INTC0_USBHD2_BITNUM 17 /* USB host2/device2 interrupt */
60#define INTCHW_INTC0_VPM_BITNUM 16 /* Voice process module interrupt */
61#define INTCHW_INTC0_DMA1C7_BITNUM 15 /* DMA1 channel 7 interrupt */
62#define INTCHW_INTC0_DMA1C6_BITNUM 14 /* DMA1 channel 6 interrupt */
63#define INTCHW_INTC0_DMA1C5_BITNUM 13 /* DMA1 channel 5 interrupt */
64#define INTCHW_INTC0_DMA1C4_BITNUM 12 /* DMA1 channel 4 interrupt */
65#define INTCHW_INTC0_DMA1C3_BITNUM 11 /* DMA1 channel 3 interrupt */
66#define INTCHW_INTC0_DMA1C2_BITNUM 10 /* DMA1 channel 2 interrupt */
67#define INTCHW_INTC0_DMA1C1_BITNUM 9 /* DMA1 channel 1 interrupt */
68#define INTCHW_INTC0_DMA1C0_BITNUM 8 /* DMA1 channel 0 interrupt */
69#define INTCHW_INTC0_DMA0C7_BITNUM 7 /* DMA0 channel 7 interrupt */
70#define INTCHW_INTC0_DMA0C6_BITNUM 6 /* DMA0 channel 6 interrupt */
71#define INTCHW_INTC0_DMA0C5_BITNUM 5 /* DMA0 channel 5 interrupt */
72#define INTCHW_INTC0_DMA0C4_BITNUM 4 /* DMA0 channel 4 interrupt */
73#define INTCHW_INTC0_DMA0C3_BITNUM 3 /* DMA0 channel 3 interrupt */
74#define INTCHW_INTC0_DMA0C2_BITNUM 2 /* DMA0 channel 2 interrupt */
75#define INTCHW_INTC0_DMA0C1_BITNUM 1 /* DMA0 channel 1 interrupt */
76#define INTCHW_INTC0_DMA0C0_BITNUM 0 /* DMA0 channel 0 interrupt */
77
78#define INTCHW_INTC0_PIF (1<<INTCHW_INTC0_PIF_BITNUM)
79#define INTCHW_INTC0_CLCD (1<<INTCHW_INTC0_CLCD_BITNUM)
80#define INTCHW_INTC0_GE (1<<INTCHW_INTC0_GE_BITNUM)
81#define INTCHW_INTC0_APM (1<<INTCHW_INTC0_APM_BITNUM)
82#define INTCHW_INTC0_ESW (1<<INTCHW_INTC0_ESW_BITNUM)
83#define INTCHW_INTC0_SPIH (1<<INTCHW_INTC0_SPIH_BITNUM)
84#define INTCHW_INTC0_TIMER3 (1<<INTCHW_INTC0_TIMER3_BITNUM)
85#define INTCHW_INTC0_TIMER2 (1<<INTCHW_INTC0_TIMER2_BITNUM)
86#define INTCHW_INTC0_TIMER1 (1<<INTCHW_INTC0_TIMER1_BITNUM)
87#define INTCHW_INTC0_TIMER0 (1<<INTCHW_INTC0_TIMER0_BITNUM)
88#define INTCHW_INTC0_SDIOH1 (1<<INTCHW_INTC0_SDIOH1_BITNUM)
89#define INTCHW_INTC0_SDIOH0 (1<<INTCHW_INTC0_SDIOH0_BITNUM)
90#define INTCHW_INTC0_USBD (1<<INTCHW_INTC0_USBD_BITNUM)
91#define INTCHW_INTC0_USBH1 (1<<INTCHW_INTC0_USBH1_BITNUM)
92#define INTCHW_INTC0_USBHD2 (1<<INTCHW_INTC0_USBHD2_BITNUM)
93#define INTCHW_INTC0_VPM (1<<INTCHW_INTC0_VPM_BITNUM)
94#define INTCHW_INTC0_DMA1C7 (1<<INTCHW_INTC0_DMA1C7_BITNUM)
95#define INTCHW_INTC0_DMA1C6 (1<<INTCHW_INTC0_DMA1C6_BITNUM)
96#define INTCHW_INTC0_DMA1C5 (1<<INTCHW_INTC0_DMA1C5_BITNUM)
97#define INTCHW_INTC0_DMA1C4 (1<<INTCHW_INTC0_DMA1C4_BITNUM)
98#define INTCHW_INTC0_DMA1C3 (1<<INTCHW_INTC0_DMA1C3_BITNUM)
99#define INTCHW_INTC0_DMA1C2 (1<<INTCHW_INTC0_DMA1C2_BITNUM)
100#define INTCHW_INTC0_DMA1C1 (1<<INTCHW_INTC0_DMA1C1_BITNUM)
101#define INTCHW_INTC0_DMA1C0 (1<<INTCHW_INTC0_DMA1C0_BITNUM)
102#define INTCHW_INTC0_DMA0C7 (1<<INTCHW_INTC0_DMA0C7_BITNUM)
103#define INTCHW_INTC0_DMA0C6 (1<<INTCHW_INTC0_DMA0C6_BITNUM)
104#define INTCHW_INTC0_DMA0C5 (1<<INTCHW_INTC0_DMA0C5_BITNUM)
105#define INTCHW_INTC0_DMA0C4 (1<<INTCHW_INTC0_DMA0C4_BITNUM)
106#define INTCHW_INTC0_DMA0C3 (1<<INTCHW_INTC0_DMA0C3_BITNUM)
107#define INTCHW_INTC0_DMA0C2 (1<<INTCHW_INTC0_DMA0C2_BITNUM)
108#define INTCHW_INTC0_DMA0C1 (1<<INTCHW_INTC0_DMA0C1_BITNUM)
109#define INTCHW_INTC0_DMA0C0 (1<<INTCHW_INTC0_DMA0C0_BITNUM)
110
111/* INTC1 - interrupt controller 1 */
112#define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interupt (Not for A0) */
113#define INTCHW_INTC1_DDRVPMT_BITNUM 26 /* DDR and VPM HW phase align timeout interrupt (Not for A0) */
114#define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interupt (For A0 only)) */
115#define INTCHW_INTC1_RTC2_BITNUM 25 /* Real time clock tamper interrupt */
116#define INTCHW_INTC1_VDEC_BITNUM 24 /* Hantro Video Decoder interrupt */
117/* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */
118#define INTCHW_INTC1_SPUM_BITNUM 23 /* Secure process module interrupt */
119#define INTCHW_INTC1_RTC1_BITNUM 22 /* Real time clock one-shot interrupt */
120#define INTCHW_INTC1_RTC0_BITNUM 21 /* Real time clock periodic interrupt */
121#define INTCHW_INTC1_RNG_BITNUM 20 /* Random number generator interrupt */
122#define INTCHW_INTC1_FMPU_BITNUM 19 /* Flash memory parition unit interrupt */
123#define INTCHW_INTC1_VMPU_BITNUM 18 /* VRAM memory partition interrupt */
124#define INTCHW_INTC1_DMPU_BITNUM 17 /* DDR2 memory partition interrupt */
125#define INTCHW_INTC1_KEYC_BITNUM 16 /* Key pad controller interrupt */
126#define INTCHW_INTC1_TSC_BITNUM 15 /* Touch screen controller interrupt */
127#define INTCHW_INTC1_UART0_BITNUM 14 /* UART 0 */
128#define INTCHW_INTC1_WDOG_BITNUM 13 /* Watchdog timer interrupt */
129
130#define INTCHW_INTC1_UART1_BITNUM 12 /* UART 1 */
131#define INTCHW_INTC1_PMUIRQ_BITNUM 11 /* ARM performance monitor interrupt */
132#define INTCHW_INTC1_COMMRX_BITNUM 10 /* ARM DDC receive interrupt */
133#define INTCHW_INTC1_COMMTX_BITNUM 9 /* ARM DDC transmit interrupt */
134#define INTCHW_INTC1_FLASHC_BITNUM 8 /* Flash controller interrupt */
135#define INTCHW_INTC1_GPHY_BITNUM 7 /* Gigabit Phy interrupt */
136#define INTCHW_INTC1_SPIS_BITNUM 6 /* SPI slave interrupt */
137#define INTCHW_INTC1_I2CS_BITNUM 5 /* I2C slave interrupt */
138#define INTCHW_INTC1_I2CH_BITNUM 4 /* I2C host interrupt */
139#define INTCHW_INTC1_I2S1_BITNUM 3 /* I2S1 interrupt */
140#define INTCHW_INTC1_I2S0_BITNUM 2 /* I2S0 interrupt */
141#define INTCHW_INTC1_GPIO1_BITNUM 1 /* GPIO bit 64//32 combined interrupt */
142#define INTCHW_INTC1_GPIO0_BITNUM 0 /* GPIO bit 31//0 combined interrupt */
143
144#define INTCHW_INTC1_DDRVPMT (1<<INTCHW_INTC1_DDRVPMT_BITNUM)
145#define INTCHW_INTC1_DDRVPMP (1<<INTCHW_INTC1_DDRVPMP_BITNUM)
146#define INTCHW_INTC1_DDRP (1<<INTCHW_INTC1_DDRP_BITNUM)
147#define INTCHW_INTC1_VDEC (1<<INTCHW_INTC1_VDEC_BITNUM)
148#define INTCHW_INTC1_SPUM (1<<INTCHW_INTC1_SPUM_BITNUM)
149#define INTCHW_INTC1_RTC2 (1<<INTCHW_INTC1_RTC2_BITNUM)
150#define INTCHW_INTC1_RTC1 (1<<INTCHW_INTC1_RTC1_BITNUM)
151#define INTCHW_INTC1_RTC0 (1<<INTCHW_INTC1_RTC0_BITNUM)
152#define INTCHW_INTC1_RNG (1<<INTCHW_INTC1_RNG_BITNUM)
153#define INTCHW_INTC1_FMPU (1<<INTCHW_INTC1_FMPU_BITNUM)
154#define INTCHW_INTC1_IMPU (1<<INTCHW_INTC1_IMPU_BITNUM)
155#define INTCHW_INTC1_DMPU (1<<INTCHW_INTC1_DMPU_BITNUM)
156#define INTCHW_INTC1_KEYC (1<<INTCHW_INTC1_KEYC_BITNUM)
157#define INTCHW_INTC1_TSC (1<<INTCHW_INTC1_TSC_BITNUM)
158#define INTCHW_INTC1_UART0 (1<<INTCHW_INTC1_UART0_BITNUM)
159#define INTCHW_INTC1_WDOG (1<<INTCHW_INTC1_WDOG_BITNUM)
160#define INTCHW_INTC1_UART1 (1<<INTCHW_INTC1_UART1_BITNUM)
161#define INTCHW_INTC1_PMUIRQ (1<<INTCHW_INTC1_PMUIRQ_BITNUM)
162#define INTCHW_INTC1_COMMRX (1<<INTCHW_INTC1_COMMRX_BITNUM)
163#define INTCHW_INTC1_COMMTX (1<<INTCHW_INTC1_COMMTX_BITNUM)
164#define INTCHW_INTC1_FLASHC (1<<INTCHW_INTC1_FLASHC_BITNUM)
165#define INTCHW_INTC1_GPHY (1<<INTCHW_INTC1_GPHY_BITNUM)
166#define INTCHW_INTC1_SPIS (1<<INTCHW_INTC1_SPIS_BITNUM)
167#define INTCHW_INTC1_I2CS (1<<INTCHW_INTC1_I2CS_BITNUM)
168#define INTCHW_INTC1_I2CH (1<<INTCHW_INTC1_I2CH_BITNUM)
169#define INTCHW_INTC1_I2S1 (1<<INTCHW_INTC1_I2S1_BITNUM)
170#define INTCHW_INTC1_I2S0 (1<<INTCHW_INTC1_I2S0_BITNUM)
171#define INTCHW_INTC1_GPIO1 (1<<INTCHW_INTC1_GPIO1_BITNUM)
172#define INTCHW_INTC1_GPIO0 (1<<INTCHW_INTC1_GPIO0_BITNUM)
173
174/* SINTC secure int controller */
175#define INTCHW_SINTC_RTC2_BITNUM 15 /* Real time clock tamper interrupt */
176#define INTCHW_SINTC_TIMER3_BITNUM 14 /* Secure timer3 interrupt */
177#define INTCHW_SINTC_TIMER2_BITNUM 13 /* Secure timer2 interrupt */
178#define INTCHW_SINTC_TIMER1_BITNUM 12 /* Secure timer1 interrupt */
179#define INTCHW_SINTC_TIMER0_BITNUM 11 /* Secure timer0 interrupt */
180#define INTCHW_SINTC_SPUM_BITNUM 10 /* Secure process module interrupt */
181#define INTCHW_SINTC_RTC1_BITNUM 9 /* Real time clock one-shot interrupt */
182#define INTCHW_SINTC_RTC0_BITNUM 8 /* Real time clock periodic interrupt */
183#define INTCHW_SINTC_RNG_BITNUM 7 /* Random number generator interrupt */
184#define INTCHW_SINTC_FMPU_BITNUM 6 /* Flash memory parition unit interrupt */
185#define INTCHW_SINTC_VMPU_BITNUM 5 /* VRAM memory partition interrupt */
186#define INTCHW_SINTC_DMPU_BITNUM 4 /* DDR2 memory partition interrupt */
187#define INTCHW_SINTC_KEYC_BITNUM 3 /* Key pad controller interrupt */
188#define INTCHW_SINTC_TSC_BITNUM 2 /* Touch screen controller interrupt */
189#define INTCHW_SINTC_UART0_BITNUM 1 /* UART0 interrupt */
190#define INTCHW_SINTC_WDOG_BITNUM 0 /* Watchdog timer interrupt */
191
192#define INTCHW_SINTC_TIMER3 (1<<INTCHW_SINTC_TIMER3_BITNUM)
193#define INTCHW_SINTC_TIMER2 (1<<INTCHW_SINTC_TIMER2_BITNUM)
194#define INTCHW_SINTC_TIMER1 (1<<INTCHW_SINTC_TIMER1_BITNUM)
195#define INTCHW_SINTC_TIMER0 (1<<INTCHW_SINTC_TIMER0_BITNUM)
196#define INTCHW_SINTC_SPUM (1<<INTCHW_SINTC_SPUM_BITNUM)
197#define INTCHW_SINTC_RTC2 (1<<INTCHW_SINTC_RTC2_BITNUM)
198#define INTCHW_SINTC_RTC1 (1<<INTCHW_SINTC_RTC1_BITNUM)
199#define INTCHW_SINTC_RTC0 (1<<INTCHW_SINTC_RTC0_BITNUM)
200#define INTCHW_SINTC_RNG (1<<INTCHW_SINTC_RNG_BITNUM)
201#define INTCHW_SINTC_FMPU (1<<INTCHW_SINTC_FMPU_BITNUM)
202#define INTCHW_SINTC_IMPU (1<<INTCHW_SINTC_IMPU_BITNUM)
203#define INTCHW_SINTC_DMPU (1<<INTCHW_SINTC_DMPU_BITNUM)
204#define INTCHW_SINTC_KEYC (1<<INTCHW_SINTC_KEYC_BITNUM)
205#define INTCHW_SINTC_TSC (1<<INTCHW_SINTC_TSC_BITNUM)
206#define INTCHW_SINTC_UART0 (1<<INTCHW_SINTC_UART0_BITNUM)
207#define INTCHW_SINTC_WDOG (1<<INTCHW_SINTC_WDOG_BITNUM)
208
209/* PL192 Vectored Interrupt Controller (VIC) layout */
210#define INTCHW_IRQSTATUS 0x00 /* IRQ status register */
211#define INTCHW_FIQSTATUS 0x04 /* FIQ status register */
212#define INTCHW_RAWINTR 0x08 /* Raw Interrupt Status register */
213#define INTCHW_INTSELECT 0x0c /* Interrupt Select Register */
214#define INTCHW_INTENABLE 0x10 /* Interrupt Enable Register */
215#define INTCHW_INTENCLEAR 0x14 /* Interrupt Enable Clear Register */
216#define INTCHW_SOFTINT 0x18 /* Soft Interrupt Register */
217#define INTCHW_SOFTINTCLEAR 0x1c /* Soft Interrupt Clear Register */
218#define INTCHW_PROTECTION 0x20 /* Protection Enable Register */
219#define INTCHW_SWPRIOMASK 0x24 /* Software Priority Mask Register */
220#define INTCHW_PRIODAISY 0x28 /* Priority Daisy Chain Register */
221#define INTCHW_VECTADDR0 0x100 /* Vector Address Registers */
222#define INTCHW_VECTPRIO0 0x200 /* Vector Priority Registers 0-31 */
223#define INTCHW_ADDRESS 0xf00 /* Vector Address Register 0-31 */
224#define INTCHW_PID 0xfe0 /* Peripheral ID Register 0-3 */
225#define INTCHW_PCELLID 0xff0 /* PrimeCell ID Register 0-3 */
226
227/* Example Usage: intcHw_irq_enable(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
228/* intcHw_irq_clear(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
229/* uint32_t bits = intcHw_irq_status(INTCHW_INTC0); */
230/* uint32_t bits = intcHw_irq_raw_status(INTCHW_INTC0); */
231
232/* ---- Public Variable Externs ------------------------------------------ */
233/* ---- Public Function Prototypes --------------------------------------- */
234/* Clear one or more IRQ interrupts. */
235static inline void intcHw_irq_disable(void *basep, uint32_t mask)
236{
237 __REG32(basep + INTCHW_INTENCLEAR) = mask;
238}
239
240/* Enables one or more IRQ interrupts. */
241static inline void intcHw_irq_enable(void *basep, uint32_t mask)
242{
243 __REG32(basep + INTCHW_INTENABLE) = mask;
244}
245
246#endif /* _INTCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/irqs.h b/arch/arm/mach-bcmring/include/mach/irqs.h
new file mode 100644
index 000000000000..b279b825d4a7
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/irqs.h
@@ -0,0 +1,132 @@
1/*
2 * Copyright (C) 2007 Broadcom
3 * Copyright (C) 1999 ARM Limited
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#if !defined(ARCH_BCMRING_IRQS_H)
21#define ARCH_BCMRING_IRQS_H
22
23/* INTC0 - interrupt controller 0 */
24#define IRQ_INTC0_START 0
25#define IRQ_DMA0C0 0 /* DMA0 channel 0 interrupt */
26#define IRQ_DMA0C1 1 /* DMA0 channel 1 interrupt */
27#define IRQ_DMA0C2 2 /* DMA0 channel 2 interrupt */
28#define IRQ_DMA0C3 3 /* DMA0 channel 3 interrupt */
29#define IRQ_DMA0C4 4 /* DMA0 channel 4 interrupt */
30#define IRQ_DMA0C5 5 /* DMA0 channel 5 interrupt */
31#define IRQ_DMA0C6 6 /* DMA0 channel 6 interrupt */
32#define IRQ_DMA0C7 7 /* DMA0 channel 7 interrupt */
33#define IRQ_DMA1C0 8 /* DMA1 channel 0 interrupt */
34#define IRQ_DMA1C1 9 /* DMA1 channel 1 interrupt */
35#define IRQ_DMA1C2 10 /* DMA1 channel 2 interrupt */
36#define IRQ_DMA1C3 11 /* DMA1 channel 3 interrupt */
37#define IRQ_DMA1C4 12 /* DMA1 channel 4 interrupt */
38#define IRQ_DMA1C5 13 /* DMA1 channel 5 interrupt */
39#define IRQ_DMA1C6 14 /* DMA1 channel 6 interrupt */
40#define IRQ_DMA1C7 15 /* DMA1 channel 7 interrupt */
41#define IRQ_VPM 16 /* Voice process module interrupt */
42#define IRQ_USBHD2 17 /* USB host2/device2 interrupt */
43#define IRQ_USBH1 18 /* USB1 host interrupt */
44#define IRQ_USBD 19 /* USB device interrupt */
45#define IRQ_SDIOH0 20 /* SDIO0 host interrupt */
46#define IRQ_SDIOH1 21 /* SDIO1 host interrupt */
47#define IRQ_TIMER0 22 /* Timer0 interrupt */
48#define IRQ_TIMER1 23 /* Timer1 interrupt */
49#define IRQ_TIMER2 24 /* Timer2 interrupt */
50#define IRQ_TIMER3 25 /* Timer3 interrupt */
51#define IRQ_SPIH 26 /* SPI host interrupt */
52#define IRQ_ESW 27 /* Ethernet switch interrupt */
53#define IRQ_APM 28 /* Audio process module interrupt */
54#define IRQ_GE 29 /* Graphic engine interrupt */
55#define IRQ_CLCD 30 /* LCD Controller interrupt */
56#define IRQ_PIF 31 /* Peripheral interface interrupt */
57#define IRQ_INTC0_END 31
58
59/* INTC1 - interrupt controller 1 */
60#define IRQ_INTC1_START 32
61#define IRQ_GPIO0 32 /* 0 GPIO bit 31//0 combined interrupt */
62#define IRQ_GPIO1 33 /* 1 GPIO bit 64//32 combined interrupt */
63#define IRQ_I2S0 34 /* 2 I2S0 interrupt */
64#define IRQ_I2S1 35 /* 3 I2S1 interrupt */
65#define IRQ_I2CH 36 /* 4 I2C host interrupt */
66#define IRQ_I2CS 37 /* 5 I2C slave interrupt */
67#define IRQ_SPIS 38 /* 6 SPI slave interrupt */
68#define IRQ_GPHY 39 /* 7 Gigabit Phy interrupt */
69#define IRQ_FLASHC 40 /* 8 Flash controller interrupt */
70#define IRQ_COMMTX 41 /* 9 ARM DDC transmit interrupt */
71#define IRQ_COMMRX 42 /* 10 ARM DDC receive interrupt */
72#define IRQ_PMUIRQ 43 /* 11 ARM performance monitor interrupt */
73#define IRQ_UARTB 44 /* 12 UARTB */
74#define IRQ_WATCHDOG 45 /* 13 Watchdog timer interrupt */
75#define IRQ_UARTA 46 /* 14 UARTA */
76#define IRQ_TSC 47 /* 15 Touch screen controller interrupt */
77#define IRQ_KEYC 48 /* 16 Key pad controller interrupt */
78#define IRQ_DMPU 49 /* 17 DDR2 memory partition interrupt */
79#define IRQ_VMPU 50 /* 18 VRAM memory partition interrupt */
80#define IRQ_FMPU 51 /* 19 Flash memory parition unit interrupt */
81#define IRQ_RNG 52 /* 20 Random number generator interrupt */
82#define IRQ_RTC0 53 /* 21 Real time clock periodic interrupt */
83#define IRQ_RTC1 54 /* 22 Real time clock one-shot interrupt */
84#define IRQ_SPUM 55 /* 23 Secure process module interrupt */
85#define IRQ_VDEC 56 /* 24 Hantro video decoder interrupt */
86#define IRQ_RTC2 57 /* 25 Real time clock tamper interrupt */
87#define IRQ_DDRP 58 /* 26 DDR Panic interrupt */
88#define IRQ_INTC1_END 58
89
90/* SINTC secure int controller */
91#define IRQ_SINTC_START 59
92#define IRQ_SEC_WATCHDOG 59 /* 0 Watchdog timer interrupt */
93#define IRQ_SEC_UARTA 60 /* 1 UARTA interrupt */
94#define IRQ_SEC_TSC 61 /* 2 Touch screen controller interrupt */
95#define IRQ_SEC_KEYC 62 /* 3 Key pad controller interrupt */
96#define IRQ_SEC_DMPU 63 /* 4 DDR2 memory partition interrupt */
97#define IRQ_SEC_VMPU 64 /* 5 VRAM memory partition interrupt */
98#define IRQ_SEC_FMPU 65 /* 6 Flash memory parition unit interrupt */
99#define IRQ_SEC_RNG 66 /* 7 Random number generator interrupt */
100#define IRQ_SEC_RTC0 67 /* 8 Real time clock periodic interrupt */
101#define IRQ_SEC_RTC1 68 /* 9 Real time clock one-shot interrupt */
102#define IRQ_SEC_SPUM 69 /* 10 Secure process module interrupt */
103#define IRQ_SEC_TIMER0 70 /* 11 Secure timer0 interrupt */
104#define IRQ_SEC_TIMER1 71 /* 12 Secure timer1 interrupt */
105#define IRQ_SEC_TIMER2 72 /* 13 Secure timer2 interrupt */
106#define IRQ_SEC_TIMER3 73 /* 14 Secure timer3 interrupt */
107#define IRQ_SEC_RTC2 74 /* 15 Real time clock tamper interrupt */
108
109#define IRQ_SINTC_END 74
110
111/* Note: there are 3 INTC registers of 32 bits each. So internal IRQs could go from 0-95 */
112/* Since IRQs are typically viewed in decimal, we start the gpio based IRQs off at 100 */
113/* to make the mapping easy for humans to decipher. */
114
115#define IRQ_GPIO_0 100
116
117#define NUM_INTERNAL_IRQS (IRQ_SINTC_END+1)
118
119/* I couldn't get the gpioHw_reg.h file to be included cleanly, so I hardcoded it */
120/* define NUM_GPIO_IRQS GPIOHW_TOTAL_NUM_PINS */
121#define NUM_GPIO_IRQS 62
122
123#define NR_IRQS (IRQ_GPIO_0 + NUM_GPIO_IRQS)
124
125#define IRQ_UNKNOWN -1
126
127/* Tune these bits to preclude noisy or unsupported interrupt sources as required. */
128#define IRQ_INTC0_VALID_MASK 0xffffffff
129#define IRQ_INTC1_VALID_MASK 0x07ffffff
130#define IRQ_SINTC_VALID_MASK 0x0000ffff
131
132#endif /* ARCH_BCMRING_IRQS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 16:13:51 -0500