Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (257 commits)
  [ARM] Update mach-types
  ARM: 5636/1: Move vendor enum to AMBA include
  ARM: Fix pfn_valid() for sparse memory
  [ARM] orion5x: Add LaCie NAS 2Big Network support
  [ARM] pxa/sharpsl_pm: zaurus c3000 aka spitz: fix resume
  ARM: 5686/1: at91: Correct AC97 reset line in at91sam9263ek board
  ARM: 5640/1: This patch modifies the support of AC97 on the at91sam9263 ek board
  ARM: 5689/1: Update default config of HP Jornada 700-series machines
  ARM: 5691/1: fix cache aliasing issues between kmap() and kmap_atomic() with highmem
  ARM: 5688/1: ks8695_serial: disable_irq() lockup
  ARM: 5687/1: fix an oops with highmem
  ARM: 5684/1: Add nuc960 platform to w90x900
  ARM: 5683/1: Add nuc950 platform to w90x900
  ARM: 5682/1: Add cpu.c and dev.c and modify some files of w90p910 platform
  ARM: 5626/1: add suspend/resume functions to amba-pl011 serial driver
  ARM: 5625/1: fix hard coded 4K resource size in amba bus detection
  MMC: MMCI: convert realview MMC to use gpiolib
  ARM: 5685/1: Make MMCI driver compile without gpiolib
  ARM: implement highpte
  ARM: Show FIQ in /proc/interrupts on CONFIG_FIQ
  ...

Fix up trivial conflict in arch/arm/kernel/signal.c.

It was due to the TIF_NOTIFY_RESUME addition in commit d0420c83f ("KEYS:
Extend TIF_NOTIFY_RESUME to (almost) all architectures") and follow-ups.

1 files changed, 86 insertions, 0 deletions

diff --git a/arch/arm/mach-bcmring/include/mach/entry-macro.S b/arch/arm/mach-bcmring/include/mach/entry-macro.S
new file mode 100644
index 000000000000..7d393ca010ac
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/entry-macro.S
@@ -0,0 +1,86 @@
+/*****************************************************************************
+* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+
+/*
+ *
+ * Low-level IRQ helper macros for BCMRing-based platforms
+ *
+ */
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/csp/mm_io.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =(MM_IO_BASE_INTC0)
+                ldr     \irqstat, [\base, #0]           @ get status
+                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
+                ands    \irqstat, \irqstat, \irqnr
+                mov     \irqnr, #IRQ_INTC0_START
+                cmp     \irqstat, #0
+                bne     1001f
+
+                ldr     \base, =(MM_IO_BASE_INTC1)
+                ldr     \irqstat, [\base, #0]           @ get status
+                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
+                ands    \irqstat, \irqstat, \irqnr
+                mov     \irqnr, #IRQ_INTC1_START
+                cmp     \irqstat, #0
+                bne     1001f
+
+                ldr     \base, =(MM_IO_BASE_SINTC)
+                ldr     \irqstat, [\base, #0]           @ get status
+                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
+                ands    \irqstat, \irqstat, \irqnr
+                mov     \irqnr, #0xffffffff             @ code meaning no interrupt bits set
+                cmp     \irqstat, #0
+                beq     1002f
+
+                mov     \irqnr, #IRQ_SINTC_START        @ something is set, so fixup return value
+
+1001:
+                movs    \tmp, \irqstat, lsl #16
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #16
+
+                movs    \tmp, \irqstat, lsl #8
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #8
+
+                movs    \tmp, \irqstat, lsl #4
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #4
+
+                movs    \tmp, \irqstat, lsl #2
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #2
+
+                movs    \tmp, \irqstat, lsl #1
+                addeq   \irqnr, \irqnr, #1
+                orrs    \base, \base, #1
+
+1002:           @ irqnr will be set to 0xffffffff if no irq bits are set
+                .endm
+
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+
+                .macro  irq_prio_table
+                .endm
+