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authorSAN People <andrew@sanpeople.com>2006-01-09 12:05:41 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-01-09 12:05:41 -0500
commit73a59c1c4af06c675a168d698d3ebfbb3270ddbe (patch)
treefa1708e19cf89a6bd13c8f7725a9cc67cc4ae6fd /arch/arm/mach-at91rm9200/gpio.c
parent50365c57860cd931c2d806057e0987634797e9af (diff)
[ARM] 3240/2: AT91RM9200 support for 2.6 (Core)
Patch from SAN People Following changes were made to clock.c: 1) Replaced <asm/hardware/clock.h> with <linux/clk.h> 2) Removed old unused clk_enable & clk_disable. 3) Replaced clk_use/clk_unuse with clk_enable/clk_disable. Otherwise it's the same as the previous patch. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-at91rm9200/gpio.c')
-rw-r--r--arch/arm/mach-at91rm9200/gpio.c302
1 files changed, 302 insertions, 0 deletions
diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c
new file mode 100644
index 000000000000..2fd2ef583e4d
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/gpio.c
@@ -0,0 +1,302 @@
1/*
2 * linux/arch/arm/mach-at91rm9200/gpio.c
3 *
4 * Copyright (C) 2005 HP Labs
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/errno.h>
13#include <linux/kernel.h>
14#include <linux/list.h>
15#include <linux/module.h>
16
17#include <asm/io.h>
18#include <asm/mach/irq.h>
19#include <asm/arch/hardware.h>
20#include <asm/arch/gpio.h>
21
22static const u32 pio_controller_offset[4] = {
23 AT91_PIOA,
24 AT91_PIOB,
25 AT91_PIOC,
26 AT91_PIOD,
27};
28
29static inline void __iomem *pin_to_controller(unsigned pin)
30{
31 void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS;
32
33 pin -= PIN_BASE;
34 pin /= 32;
35 if (likely(pin < BGA_GPIO_BANKS))
36 return sys_base + pio_controller_offset[pin];
37
38 return NULL;
39}
40
41static inline unsigned pin_to_mask(unsigned pin)
42{
43 pin -= PIN_BASE;
44 return 1 << (pin % 32);
45}
46
47
48/*--------------------------------------------------------------------------*/
49
50/* Not all hardware capabilities are exposed through these calls; they
51 * only encapsulate the most common features and modes. (So if you
52 * want to change signals in groups, do it directly.)
53 *
54 * Bootloaders will usually handle some of the pin multiplexing setup.
55 * The intent is certainly that by the time Linux is fully booted, all
56 * pins should have been fully initialized. These setup calls should
57 * only be used by board setup routines, or possibly in driver probe().
58 *
59 * For bootloaders doing all that setup, these calls could be inlined
60 * as NOPs so Linux won't duplicate any setup code
61 */
62
63
64/*
65 * mux the pin to the "A" internal peripheral role.
66 */
67int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
68{
69 void __iomem *pio = pin_to_controller(pin);
70 unsigned mask = pin_to_mask(pin);
71
72 if (!pio)
73 return -EINVAL;
74
75 __raw_writel(mask, pio + PIO_IDR);
76 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
77 __raw_writel(mask, pio + PIO_ASR);
78 __raw_writel(mask, pio + PIO_PDR);
79 return 0;
80}
81EXPORT_SYMBOL(at91_set_A_periph);
82
83
84/*
85 * mux the pin to the "B" internal peripheral role.
86 */
87int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
88{
89 void __iomem *pio = pin_to_controller(pin);
90 unsigned mask = pin_to_mask(pin);
91
92 if (!pio)
93 return -EINVAL;
94
95 __raw_writel(mask, pio + PIO_IDR);
96 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
97 __raw_writel(mask, pio + PIO_BSR);
98 __raw_writel(mask, pio + PIO_PDR);
99 return 0;
100}
101EXPORT_SYMBOL(at91_set_B_periph);
102
103
104/*
105 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
106 * configure it for an input.
107 */
108int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
109{
110 void __iomem *pio = pin_to_controller(pin);
111 unsigned mask = pin_to_mask(pin);
112
113 if (!pio)
114 return -EINVAL;
115
116 __raw_writel(mask, pio + PIO_IDR);
117 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
118 __raw_writel(mask, pio + PIO_ODR);
119 __raw_writel(mask, pio + PIO_PER);
120 return 0;
121}
122EXPORT_SYMBOL(at91_set_gpio_input);
123
124
125/*
126 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
127 * and configure it for an output.
128 */
129int __init_or_module at91_set_gpio_output(unsigned pin, int value)
130{
131 void __iomem *pio = pin_to_controller(pin);
132 unsigned mask = pin_to_mask(pin);
133
134 if (!pio)
135 return -EINVAL;
136
137 __raw_writel(mask, pio + PIO_IDR);
138 __raw_writel(mask, pio + PIO_PUDR);
139 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
140 __raw_writel(mask, pio + PIO_OER);
141 __raw_writel(mask, pio + PIO_PER);
142 return 0;
143}
144EXPORT_SYMBOL(at91_set_gpio_output);
145
146
147/*
148 * enable/disable the glitch filter; mostly used with IRQ handling.
149 */
150int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
151{
152 void __iomem *pio = pin_to_controller(pin);
153 unsigned mask = pin_to_mask(pin);
154
155 if (!pio)
156 return -EINVAL;
157 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
158 return 0;
159}
160EXPORT_SYMBOL(at91_set_deglitch);
161
162/*--------------------------------------------------------------------------*/
163
164
165/*
166 * assuming the pin is muxed as a gpio output, set its value.
167 */
168int at91_set_gpio_value(unsigned pin, int value)
169{
170 void __iomem *pio = pin_to_controller(pin);
171 unsigned mask = pin_to_mask(pin);
172
173 if (!pio)
174 return -EINVAL;
175 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
176 return 0;
177}
178EXPORT_SYMBOL(at91_set_gpio_value);
179
180
181/*
182 * read the pin's value (works even if it's not muxed as a gpio).
183 */
184int at91_get_gpio_value(unsigned pin)
185{
186 void __iomem *pio = pin_to_controller(pin);
187 unsigned mask = pin_to_mask(pin);
188 u32 pdsr;
189
190 if (!pio)
191 return -EINVAL;
192 pdsr = __raw_readl(pio + PIO_PDSR);
193 return (pdsr & mask) != 0;
194}
195EXPORT_SYMBOL(at91_get_gpio_value);
196
197/*--------------------------------------------------------------------------*/
198
199
200/* Several AIC controller irqs are dispatched through this GPIO handler.
201 * To use any AT91_PIN_* as an externally triggered IRQ, first call
202 * at91_set_gpio_input() then maybe enable its glitch filter.
203 * Then just request_irq() with the pin ID; it works like any ARM IRQ
204 * handler, though it always triggers on rising and falling edges.
205 *
206 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
207 * configuring them with at91_set_a_periph() or at91_set_b_periph().
208 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
209 */
210
211static void gpio_irq_mask(unsigned pin)
212{
213 void __iomem *pio = pin_to_controller(pin);
214 unsigned mask = pin_to_mask(pin);
215
216 if (pio)
217 __raw_writel(mask, pio + PIO_IDR);
218}
219
220static void gpio_irq_unmask(unsigned pin)
221{
222 void __iomem *pio = pin_to_controller(pin);
223 unsigned mask = pin_to_mask(pin);
224
225 if (pio)
226 __raw_writel(mask, pio + PIO_IER);
227}
228
229static int gpio_irq_type(unsigned pin, unsigned type)
230{
231 return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL;
232}
233
234static struct irqchip gpio_irqchip = {
235 .mask = gpio_irq_mask,
236 .unmask = gpio_irq_unmask,
237 .set_type = gpio_irq_type,
238};
239
240static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs *regs)
241{
242 unsigned pin;
243 struct irqdesc *gpio;
244 void __iomem *pio;
245 u32 isr;
246
247 pio = (void __force __iomem *) desc->chipdata;
248
249 /* temporarily mask (level sensitive) parent IRQ */
250 desc->chip->ack(irq);
251 for (;;) {
252 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
253 if (!isr)
254 break;
255
256 pin = (unsigned) desc->data;
257 gpio = &irq_desc[pin];
258
259 while (isr) {
260 if (isr & 1)
261 gpio->handle(pin, gpio, regs);
262 pin++;
263 gpio++;
264 isr >>= 1;
265 }
266 }
267 desc->chip->unmask(irq);
268 /* now it may re-trigger */
269}
270
271/* call this from board-specific init_irq */
272void __init at91_gpio_irq_setup(unsigned banks)
273{
274 unsigned pioc, pin, id;
275
276 if (banks > 4)
277 banks = 4;
278 for (pioc = 0, pin = PIN_BASE, id = AT91_ID_PIOA;
279 pioc < banks;
280 pioc++, id++) {
281 void __iomem *controller;
282 unsigned i;
283
284 controller = (void __iomem *) AT91_VA_BASE_SYS + pio_controller_offset[pioc];
285 __raw_writel(~0, controller + PIO_IDR);
286
287 set_irq_data(id, (void *) pin);
288 set_irq_chipdata(id, (void __force *) controller);
289
290 for (i = 0; i < 32; i++, pin++) {
291 set_irq_chip(pin, &gpio_irqchip);
292 set_irq_handler(pin, do_simple_IRQ);
293 set_irq_flags(pin, IRQF_VALID);
294 }
295
296 set_irq_chained_handler(id, gpio_irq_handler);
297
298 /* enable the PIO peripheral clock */
299 at91_sys_write(AT91_PMC_PCER, 1 << id);
300 }
301 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, banks);
302}