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authorAndrew Victor <andrew@sanpeople.com>2006-02-24 17:27:50 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-02-24 17:27:50 -0500
commitabbea7187296a7fb316a55f2319438c2bf881f0a (patch)
tree28e8988de3cc8e81691bfd0170b1d03032dc7da7 /arch/arm/mach-at91rm9200/gpio.c
parentf52ee1410d563cd409b08822492273a5bc235821 (diff)
[ARM] 3348/1: Disable GPIO interrupts
Patch from Andrew Victor disable_irq() lazily disables the interrupt, so the IRQ is only disabled once the interrupt occurs again. The GPIO interrupt handler therefore must first check disable_depth to see if the IRQ needs to be disabled. Orignal patch by Bill Gatliff. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-at91rm9200/gpio.c')
-rw-r--r--arch/arm/mach-at91rm9200/gpio.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/arm/mach-at91rm9200/gpio.c b/arch/arm/mach-at91rm9200/gpio.c
index a9f718bf8ba8..0e396feec468 100644
--- a/arch/arm/mach-at91rm9200/gpio.c
+++ b/arch/arm/mach-at91rm9200/gpio.c
@@ -274,8 +274,18 @@ static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs
274 gpio = &irq_desc[pin]; 274 gpio = &irq_desc[pin];
275 275
276 while (isr) { 276 while (isr) {
277 if (isr & 1) 277 if (isr & 1) {
278 gpio->handle(pin, gpio, regs); 278 if (unlikely(gpio->disable_depth)) {
279 /*
280 * The core ARM interrupt handler lazily disables IRQs so
281 * another IRQ must be generated before it actually gets
282 * here to be disabled on the GPIO controller.
283 */
284 gpio_irq_mask(pin);
285 }
286 else
287 gpio->handle(pin, gpio, regs);
288 }
279 pin++; 289 pin++;
280 gpio++; 290 gpio++;
281 isr >>= 1; 291 isr >>= 1;