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authorNicolas Ferre <nicolas.ferre@atmel.com>2009-07-22 14:04:45 -0400
committerDan Williams <dan.j.williams@intel.com>2009-07-23 02:15:33 -0400
commit808347f6a31792079e345ec865e9cfcb6e8ae6b2 (patch)
tree05fe2e32712d84ec5dc7553033432712313f6ba2 /arch/arm/mach-at91
parentdc78baa2b90b289590911b40b6800f77d0dc935a (diff)
dmaengine: at_hdmac: add DMA slave transfers
This patch for at_hdmac adds the slave transfers capability to the Atmel DMA controller available on some AT91 SOCs. This allow peripheral to memory and memory to peripheral transfers with hardware handshaking. Slave structure for controller specific information is passed through channel private data. This at_dma_slave structure is defined in at_hdmac.h header file and relative hardware definition are moved to this file from at_hdmac_regs.h. Doing this we allow the channel configuration from platform definition code. This work is intensively based on dw_dmac and several slave implementations. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/include/mach/at_hdmac.h76
1 files changed, 76 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/include/mach/at_hdmac.h b/arch/arm/mach-at91/include/mach/at_hdmac.h
index 21a5554f9cb8..187cb58345c0 100644
--- a/arch/arm/mach-at91/include/mach/at_hdmac.h
+++ b/arch/arm/mach-at91/include/mach/at_hdmac.h
@@ -23,4 +23,80 @@ struct at_dma_platform_data {
23 dma_cap_mask_t cap_mask; 23 dma_cap_mask_t cap_mask;
24}; 24};
25 25
26/**
27 * enum at_dma_slave_width - DMA slave register access width.
28 * @AT_DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
29 * @AT_DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
30 * @AT_DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
31 */
32enum at_dma_slave_width {
33 AT_DMA_SLAVE_WIDTH_8BIT = 0,
34 AT_DMA_SLAVE_WIDTH_16BIT,
35 AT_DMA_SLAVE_WIDTH_32BIT,
36};
37
38/**
39 * struct at_dma_slave - Controller-specific information about a slave
40 * @dma_dev: required DMA master device
41 * @tx_reg: physical address of data register used for
42 * memory-to-peripheral transfers
43 * @rx_reg: physical address of data register used for
44 * peripheral-to-memory transfers
45 * @reg_width: peripheral register width
46 * @cfg: Platform-specific initializer for the CFG register
47 * @ctrla: Platform-specific initializer for the CTRLA register
48 */
49struct at_dma_slave {
50 struct device *dma_dev;
51 dma_addr_t tx_reg;
52 dma_addr_t rx_reg;
53 enum at_dma_slave_width reg_width;
54 u32 cfg;
55 u32 ctrla;
56};
57
58
59/* Platform-configurable bits in CFG */
60#define ATC_SRC_PER(h) (0xFU & (h)) /* Channel src rq associated with periph handshaking ifc h */
61#define ATC_DST_PER(h) ((0xFU & (h)) << 4) /* Channel dst rq associated with periph handshaking ifc h */
62#define ATC_SRC_REP (0x1 << 8) /* Source Replay Mod */
63#define ATC_SRC_H2SEL (0x1 << 9) /* Source Handshaking Mod */
64#define ATC_SRC_H2SEL_SW (0x0 << 9)
65#define ATC_SRC_H2SEL_HW (0x1 << 9)
66#define ATC_DST_REP (0x1 << 12) /* Destination Replay Mod */
67#define ATC_DST_H2SEL (0x1 << 13) /* Destination Handshaking Mod */
68#define ATC_DST_H2SEL_SW (0x0 << 13)
69#define ATC_DST_H2SEL_HW (0x1 << 13)
70#define ATC_SOD (0x1 << 16) /* Stop On Done */
71#define ATC_LOCK_IF (0x1 << 20) /* Interface Lock */
72#define ATC_LOCK_B (0x1 << 21) /* AHB Bus Lock */
73#define ATC_LOCK_IF_L (0x1 << 22) /* Master Interface Arbiter Lock */
74#define ATC_LOCK_IF_L_CHUNK (0x0 << 22)
75#define ATC_LOCK_IF_L_BUFFER (0x1 << 22)
76#define ATC_AHB_PROT_MASK (0x7 << 24) /* AHB Protection */
77#define ATC_FIFOCFG_MASK (0x3 << 28) /* FIFO Request Configuration */
78#define ATC_FIFOCFG_LARGESTBURST (0x0 << 28)
79#define ATC_FIFOCFG_HALFFIFO (0x1 << 28)
80#define ATC_FIFOCFG_ENOUGHSPACE (0x2 << 28)
81
82/* Platform-configurable bits in CTRLA */
83#define ATC_SCSIZE_MASK (0x7 << 16) /* Source Chunk Transfer Size */
84#define ATC_SCSIZE_1 (0x0 << 16)
85#define ATC_SCSIZE_4 (0x1 << 16)
86#define ATC_SCSIZE_8 (0x2 << 16)
87#define ATC_SCSIZE_16 (0x3 << 16)
88#define ATC_SCSIZE_32 (0x4 << 16)
89#define ATC_SCSIZE_64 (0x5 << 16)
90#define ATC_SCSIZE_128 (0x6 << 16)
91#define ATC_SCSIZE_256 (0x7 << 16)
92#define ATC_DCSIZE_MASK (0x7 << 20) /* Destination Chunk Transfer Size */
93#define ATC_DCSIZE_1 (0x0 << 20)
94#define ATC_DCSIZE_4 (0x1 << 20)
95#define ATC_DCSIZE_8 (0x2 << 20)
96#define ATC_DCSIZE_16 (0x3 << 20)
97#define ATC_DCSIZE_32 (0x4 << 20)
98#define ATC_DCSIZE_64 (0x5 << 20)
99#define ATC_DCSIZE_128 (0x6 << 20)
100#define ATC_DCSIZE_256 (0x7 << 20)
101
26#endif /* AT_HDMAC_H */ 102#endif /* AT_HDMAC_H */