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authorNicolas Ferre <nicolas.ferre@atmel.com>2014-10-21 09:09:21 -0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2014-11-03 12:48:02 -0500
commitbcf8c7e7703bb2bbde66bec26a81fed4be9cd1d4 (patch)
treee03a1b5e562dfc2a936e903bc0cf197d3dafc37b /arch/arm/mach-at91
parent4bf7753b8ab7c704ca864b1653367ea9cfe68a25 (diff)
ARM: at91: remove at91sam9rl legacy board support
Remove legacy support for at91sam9rl boards. This include board files removal plus all legacy code for non DT boards support. Use the Device Tree for running this board with newer kernels. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> [nicolas.ferre@atmel.com: Add sentence about DT] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/Kconfig.non_dt19
-rw-r--r--arch/arm/mach-at91/Makefile4
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c371
-rw-r--r--arch/arm/mach-at91/at91sam9rl_devices.c1260
-rw-r--r--arch/arm/mach-at91/board-sam9rlek.c333
5 files changed, 0 insertions, 1987 deletions
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index b86dd9923d58..22963a829e5c 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -33,12 +33,6 @@ config ARCH_AT91SAM9263
33 select AT91_USE_OLD_CLK 33 select AT91_USE_OLD_CLK
34 select OLD_IRQ_AT91 34 select OLD_IRQ_AT91
35 35
36config ARCH_AT91SAM9RL
37 bool "AT91SAM9RL"
38 select SOC_AT91SAM9RL
39 select AT91_USE_OLD_CLK
40 select OLD_IRQ_AT91
41
42endchoice 36endchoice
43 37
44config ARCH_AT91SAM9G20 38config ARCH_AT91SAM9G20
@@ -281,19 +275,6 @@ endif
281 275
282# ---------------------------------------------------------- 276# ----------------------------------------------------------
283 277
284if ARCH_AT91SAM9RL
285
286comment "AT91SAM9RL Board Type"
287
288config MACH_AT91SAM9RLEK
289 bool "Atmel AT91SAM9RL-EK Evaluation Kit"
290 help
291 Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
292
293endif
294
295# ----------------------------------------------------------
296
297comment "AT91 Board Options" 278comment "AT91 Board Options"
298 279
299config MTD_AT91_DATAFLASH_CARD 280config MTD_AT91_DATAFLASH_CARD
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 37a35b048893..df48363d7384 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -24,7 +24,6 @@ obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o
24obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o 24obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o
25obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o 25obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o
26obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263_devices.o 26obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263_devices.o
27obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl_devices.o
28 27
29# AT91RM9200 board-specific support 28# AT91RM9200 board-specific support
30obj-$(CONFIG_MACH_ONEARM) += board-1arm.o 29obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
@@ -56,9 +55,6 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
56# AT91SAM9263 board-specific support 55# AT91SAM9263 board-specific support
57obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o 56obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
58 57
59# AT91SAM9RL board-specific support
60obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
61
62# AT91SAM9G20 board-specific support 58# AT91SAM9G20 board-specific support
63obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o 59obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
64obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o 60obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index f553e4ea034b..6ca7fc5ca812 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -9,284 +9,13 @@
9 * more details. 9 * more details.
10 */ 10 */
11 11
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/clk/at91_pmc.h>
15
16#include <asm/proc-fns.h>
17#include <asm/irq.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/map.h>
20#include <asm/system_misc.h> 12#include <asm/system_misc.h>
21#include <mach/cpu.h> 13#include <mach/cpu.h>
22#include <mach/at91_dbgu.h> 14#include <mach/at91_dbgu.h>
23#include <mach/at91sam9rl.h>
24#include <mach/hardware.h> 15#include <mach/hardware.h>
25 16
26#include "at91_aic.h"
27#include "soc.h" 17#include "soc.h"
28#include "generic.h" 18#include "generic.h"
29#include "sam9_smc.h"
30#include "pm.h"
31
32/* --------------------------------------------------------------------
33 * Clocks
34 * -------------------------------------------------------------------- */
35#if defined(CONFIG_OLD_CLK_AT91)
36#include "clock.h"
37
38/*
39 * The peripheral clocks.
40 */
41static struct clk pioA_clk = {
42 .name = "pioA_clk",
43 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
44 .type = CLK_TYPE_PERIPHERAL,
45};
46static struct clk pioB_clk = {
47 .name = "pioB_clk",
48 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
49 .type = CLK_TYPE_PERIPHERAL,
50};
51static struct clk pioC_clk = {
52 .name = "pioC_clk",
53 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
54 .type = CLK_TYPE_PERIPHERAL,
55};
56static struct clk pioD_clk = {
57 .name = "pioD_clk",
58 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
59 .type = CLK_TYPE_PERIPHERAL,
60};
61static struct clk usart0_clk = {
62 .name = "usart0_clk",
63 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
64 .type = CLK_TYPE_PERIPHERAL,
65};
66static struct clk usart1_clk = {
67 .name = "usart1_clk",
68 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
69 .type = CLK_TYPE_PERIPHERAL,
70};
71static struct clk usart2_clk = {
72 .name = "usart2_clk",
73 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
74 .type = CLK_TYPE_PERIPHERAL,
75};
76static struct clk usart3_clk = {
77 .name = "usart3_clk",
78 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
79 .type = CLK_TYPE_PERIPHERAL,
80};
81static struct clk mmc_clk = {
82 .name = "mci_clk",
83 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
84 .type = CLK_TYPE_PERIPHERAL,
85};
86static struct clk twi0_clk = {
87 .name = "twi0_clk",
88 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
89 .type = CLK_TYPE_PERIPHERAL,
90};
91static struct clk twi1_clk = {
92 .name = "twi1_clk",
93 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
94 .type = CLK_TYPE_PERIPHERAL,
95};
96static struct clk spi_clk = {
97 .name = "spi_clk",
98 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
99 .type = CLK_TYPE_PERIPHERAL,
100};
101static struct clk ssc0_clk = {
102 .name = "ssc0_clk",
103 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
104 .type = CLK_TYPE_PERIPHERAL,
105};
106static struct clk ssc1_clk = {
107 .name = "ssc1_clk",
108 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
109 .type = CLK_TYPE_PERIPHERAL,
110};
111static struct clk tc0_clk = {
112 .name = "tc0_clk",
113 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
114 .type = CLK_TYPE_PERIPHERAL,
115};
116static struct clk tc1_clk = {
117 .name = "tc1_clk",
118 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
119 .type = CLK_TYPE_PERIPHERAL,
120};
121static struct clk tc2_clk = {
122 .name = "tc2_clk",
123 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
124 .type = CLK_TYPE_PERIPHERAL,
125};
126static struct clk pwm_clk = {
127 .name = "pwm_clk",
128 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
129 .type = CLK_TYPE_PERIPHERAL,
130};
131static struct clk tsc_clk = {
132 .name = "tsc_clk",
133 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
134 .type = CLK_TYPE_PERIPHERAL,
135};
136static struct clk dma_clk = {
137 .name = "dma_clk",
138 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
139 .type = CLK_TYPE_PERIPHERAL,
140};
141static struct clk udphs_clk = {
142 .name = "udphs_clk",
143 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
144 .type = CLK_TYPE_PERIPHERAL,
145};
146static struct clk lcdc_clk = {
147 .name = "lcdc_clk",
148 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
149 .type = CLK_TYPE_PERIPHERAL,
150};
151static struct clk ac97_clk = {
152 .name = "ac97_clk",
153 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
154 .type = CLK_TYPE_PERIPHERAL,
155};
156static struct clk adc_op_clk = {
157 .name = "adc_op_clk",
158 .type = CLK_TYPE_PERIPHERAL,
159 .rate_hz = 1000000,
160};
161
162static struct clk *periph_clocks[] __initdata = {
163 &pioA_clk,
164 &pioB_clk,
165 &pioC_clk,
166 &pioD_clk,
167 &usart0_clk,
168 &usart1_clk,
169 &usart2_clk,
170 &usart3_clk,
171 &mmc_clk,
172 &twi0_clk,
173 &twi1_clk,
174 &spi_clk,
175 &ssc0_clk,
176 &ssc1_clk,
177 &tc0_clk,
178 &tc1_clk,
179 &tc2_clk,
180 &pwm_clk,
181 &tsc_clk,
182 &dma_clk,
183 &udphs_clk,
184 &lcdc_clk,
185 &ac97_clk,
186 &adc_op_clk,
187 // irq0
188};
189
190static struct clk_lookup periph_clocks_lookups[] = {
191 CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
192 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
193 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
194 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
195 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
196 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
197 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
198 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
199 CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
200 CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
201 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
202 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
203 CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
204 CLKDEV_CON_ID("pioA", &pioA_clk),
205 CLKDEV_CON_ID("pioB", &pioB_clk),
206 CLKDEV_CON_ID("pioC", &pioC_clk),
207 CLKDEV_CON_ID("pioD", &pioD_clk),
208 /* more lookup table for DT entries */
209 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
210 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
211 CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
212 CLKDEV_CON_DEV_ID("usart", "ffffb800.serial", &usart2_clk),
213 CLKDEV_CON_DEV_ID("usart", "ffffbc00.serial", &usart3_clk),
214 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
215 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
216 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
217 CLKDEV_CON_DEV_ID("mci_clk", "fffa4000.mmc", &mmc_clk),
218 CLKDEV_CON_DEV_ID(NULL, "fffa8000.i2c", &twi0_clk),
219 CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi1_clk),
220 CLKDEV_CON_DEV_ID(NULL, "fffc8000.pwm", &pwm_clk),
221 CLKDEV_CON_DEV_ID(NULL, "ffffc800.pwm", &pwm_clk),
222 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
223 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
224 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
225 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
226 CLKDEV_CON_ID("adc_clk", &tsc_clk),
227};
228
229static struct clk_lookup usart_clocks_lookups[] = {
230 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
232 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
233 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
234 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
235};
236
237/*
238 * The two programmable clocks.
239 * You must configure pin multiplexing to bring these signals out.
240 */
241static struct clk pck0 = {
242 .name = "pck0",
243 .pmc_mask = AT91_PMC_PCK0,
244 .type = CLK_TYPE_PROGRAMMABLE,
245 .id = 0,
246};
247static struct clk pck1 = {
248 .name = "pck1",
249 .pmc_mask = AT91_PMC_PCK1,
250 .type = CLK_TYPE_PROGRAMMABLE,
251 .id = 1,
252};
253
254static void __init at91sam9rl_register_clocks(void)
255{
256 int i;
257
258 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
259 clk_register(periph_clocks[i]);
260
261 clkdev_add_table(periph_clocks_lookups,
262 ARRAY_SIZE(periph_clocks_lookups));
263 clkdev_add_table(usart_clocks_lookups,
264 ARRAY_SIZE(usart_clocks_lookups));
265
266 clk_register(&pck0);
267 clk_register(&pck1);
268}
269#endif
270
271/* --------------------------------------------------------------------
272 * GPIO
273 * -------------------------------------------------------------------- */
274
275static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
276 {
277 .id = AT91SAM9RL_ID_PIOA,
278 .regbase = AT91SAM9RL_BASE_PIOA,
279 }, {
280 .id = AT91SAM9RL_ID_PIOB,
281 .regbase = AT91SAM9RL_BASE_PIOB,
282 }, {
283 .id = AT91SAM9RL_ID_PIOC,
284 .regbase = AT91SAM9RL_BASE_PIOC,
285 }, {
286 .id = AT91SAM9RL_ID_PIOD,
287 .regbase = AT91SAM9RL_BASE_PIOD,
288 }
289};
290 19
291/* -------------------------------------------------------------------- 20/* --------------------------------------------------------------------
292 * AT91SAM9RL processor initialization 21 * AT91SAM9RL processor initialization
@@ -309,107 +38,14 @@ static void __init at91sam9rl_map_io(void)
309 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size); 38 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
310} 39}
311 40
312static void __init at91sam9rl_ioremap_registers(void)
313{
314 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
315 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
316 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
317 at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
318 at91_pm_set_standby(at91sam9_sdram_standby);
319}
320
321static void __init at91sam9rl_initialize(void) 41static void __init at91sam9rl_initialize(void)
322{ 42{
323 arm_pm_idle = at91sam9_idle; 43 arm_pm_idle = at91sam9_idle;
324 44
325 at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC); 45 at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
326 at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT); 46 at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
327
328 /* Register GPIO subsystem */
329 at91_gpio_init(at91sam9rl_gpio, 4);
330}
331
332static struct resource rstc_resources[] = {
333 [0] = {
334 .start = AT91SAM9RL_BASE_RSTC,
335 .end = AT91SAM9RL_BASE_RSTC + SZ_16 - 1,
336 .flags = IORESOURCE_MEM,
337 },
338 [1] = {
339 .start = AT91SAM9RL_BASE_SDRAMC,
340 .end = AT91SAM9RL_BASE_SDRAMC + SZ_512 - 1,
341 .flags = IORESOURCE_MEM,
342 },
343};
344
345static struct platform_device rstc_device = {
346 .name = "at91-sam9260-reset",
347 .resource = rstc_resources,
348 .num_resources = ARRAY_SIZE(rstc_resources),
349};
350
351static struct resource shdwc_resources[] = {
352 [0] = {
353 .start = AT91SAM9RL_BASE_SHDWC,
354 .end = AT91SAM9RL_BASE_SHDWC + SZ_16 - 1,
355 .flags = IORESOURCE_MEM,
356 },
357};
358
359static struct platform_device shdwc_device = {
360 .name = "at91-poweroff",
361 .resource = shdwc_resources,
362 .num_resources = ARRAY_SIZE(shdwc_resources),
363};
364
365static void __init at91sam9rl_register_devices(void)
366{
367 platform_device_register(&rstc_device);
368 platform_device_register(&shdwc_device);
369} 47}
370 48
371/* --------------------------------------------------------------------
372 * Interrupt initialization
373 * -------------------------------------------------------------------- */
374
375/*
376 * The default interrupt priority levels (0 = lowest, 7 = highest).
377 */
378static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
379 7, /* Advanced Interrupt Controller */
380 7, /* System Peripherals */
381 1, /* Parallel IO Controller A */
382 1, /* Parallel IO Controller B */
383 1, /* Parallel IO Controller C */
384 1, /* Parallel IO Controller D */
385 5, /* USART 0 */
386 5, /* USART 1 */
387 5, /* USART 2 */
388 5, /* USART 3 */
389 0, /* Multimedia Card Interface */
390 6, /* Two-Wire Interface 0 */
391 6, /* Two-Wire Interface 1 */
392 5, /* Serial Peripheral Interface */
393 4, /* Serial Synchronous Controller 0 */
394 4, /* Serial Synchronous Controller 1 */
395 0, /* Timer Counter 0 */
396 0, /* Timer Counter 1 */
397 0, /* Timer Counter 2 */
398 0,
399 0, /* Touch Screen Controller */
400 0, /* DMA Controller */
401 2, /* USB Device High speed port */
402 2, /* LCD Controller */
403 6, /* AC97 Controller */
404 0,
405 0,
406 0,
407 0,
408 0,
409 0,
410 0, /* Advanced Interrupt Controller */
411};
412
413static void __init at91sam9rl_init_time(void) 49static void __init at91sam9rl_init_time(void)
414{ 50{
415 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS); 51 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
@@ -417,13 +53,6 @@ static void __init at91sam9rl_init_time(void)
417 53
418AT91_SOC_START(at91sam9rl) 54AT91_SOC_START(at91sam9rl)
419 .map_io = at91sam9rl_map_io, 55 .map_io = at91sam9rl_map_io,
420 .default_irq_priority = at91sam9rl_default_irq_priority,
421 .extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
422 .ioremap_registers = at91sam9rl_ioremap_registers,
423#if defined(CONFIG_OLD_CLK_AT91)
424 .register_clocks = at91sam9rl_register_clocks,
425#endif
426 .register_devices = at91sam9rl_register_devices,
427 .init = at91sam9rl_initialize, 56 .init = at91sam9rl_initialize,
428 .init_time = at91sam9rl_init_time, 57 .init_time = at91sam9rl_init_time,
429AT91_SOC_END 58AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
deleted file mode 100644
index 37d1c9ed4562..000000000000
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ /dev/null
@@ -1,1260 +0,0 @@
1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
6 * more details.
7 */
8
9#include <asm/mach/arch.h>
10#include <asm/mach/map.h>
11
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14#include <linux/platform_device.h>
15#include <linux/i2c-gpio.h>
16
17#include <linux/fb.h>
18#include <video/atmel_lcdc.h>
19
20#include <mach/at91sam9rl.h>
21#include <mach/at91sam9rl_matrix.h>
22#include <mach/at91_matrix.h>
23#include <mach/at91sam9_smc.h>
24#include <mach/hardware.h>
25#include <linux/platform_data/dma-atmel.h>
26#include <linux/platform_data/at91_adc.h>
27
28#include "board.h"
29#include "generic.h"
30#include "gpio.h"
31
32
33/* --------------------------------------------------------------------
34 * HDMAC - AHB DMA Controller
35 * -------------------------------------------------------------------- */
36
37#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
38static u64 hdmac_dmamask = DMA_BIT_MASK(32);
39
40static struct resource hdmac_resources[] = {
41 [0] = {
42 .start = AT91SAM9RL_BASE_DMA,
43 .end = AT91SAM9RL_BASE_DMA + SZ_512 - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [2] = {
47 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA,
48 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA,
49 .flags = IORESOURCE_IRQ,
50 },
51};
52
53static struct platform_device at_hdmac_device = {
54 .name = "at91sam9rl_dma",
55 .id = -1,
56 .dev = {
57 .dma_mask = &hdmac_dmamask,
58 .coherent_dma_mask = DMA_BIT_MASK(32),
59 },
60 .resource = hdmac_resources,
61 .num_resources = ARRAY_SIZE(hdmac_resources),
62};
63
64void __init at91_add_device_hdmac(void)
65{
66 platform_device_register(&at_hdmac_device);
67}
68#else
69void __init at91_add_device_hdmac(void) {}
70#endif
71
72/* --------------------------------------------------------------------
73 * USB HS Device (Gadget)
74 * -------------------------------------------------------------------- */
75
76#if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
77
78static struct resource usba_udc_resources[] = {
79 [0] = {
80 .start = AT91SAM9RL_UDPHS_FIFO,
81 .end = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
82 .flags = IORESOURCE_MEM,
83 },
84 [1] = {
85 .start = AT91SAM9RL_BASE_UDPHS,
86 .end = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
87 .flags = IORESOURCE_MEM,
88 },
89 [2] = {
90 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS,
91 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
97 [idx] = { \
98 .name = nam, \
99 .index = idx, \
100 .fifo_size = maxpkt, \
101 .nr_banks = maxbk, \
102 .can_dma = dma, \
103 .can_isoc = isoc, \
104 }
105
106static struct usba_ep_data usba_udc_ep[] __initdata = {
107 EP("ep0", 0, 64, 1, 0, 0),
108 EP("ep1", 1, 1024, 2, 1, 1),
109 EP("ep2", 2, 1024, 2, 1, 1),
110 EP("ep3", 3, 1024, 3, 1, 0),
111 EP("ep4", 4, 1024, 3, 1, 0),
112 EP("ep5", 5, 1024, 3, 1, 1),
113 EP("ep6", 6, 1024, 3, 1, 1),
114};
115
116#undef EP
117
118/*
119 * pdata doesn't have room for any endpoints, so we need to
120 * append room for the ones we need right after it.
121 */
122static struct {
123 struct usba_platform_data pdata;
124 struct usba_ep_data ep[7];
125} usba_udc_data;
126
127static struct platform_device at91_usba_udc_device = {
128 .name = "atmel_usba_udc",
129 .id = -1,
130 .dev = {
131 .platform_data = &usba_udc_data.pdata,
132 },
133 .resource = usba_udc_resources,
134 .num_resources = ARRAY_SIZE(usba_udc_resources),
135};
136
137void __init at91_add_device_usba(struct usba_platform_data *data)
138{
139 /*
140 * Invalid pins are 0 on AT91, but the usba driver is shared
141 * with AVR32, which use negative values instead. Once/if
142 * gpio_is_valid() is ported to AT91, revisit this code.
143 */
144 usba_udc_data.pdata.vbus_pin = -EINVAL;
145 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
146 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
147
148 if (data && gpio_is_valid(data->vbus_pin)) {
149 at91_set_gpio_input(data->vbus_pin, 0);
150 at91_set_deglitch(data->vbus_pin, 1);
151 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
152 }
153
154 /* Pullup pin is handled internally by USB device peripheral */
155
156 platform_device_register(&at91_usba_udc_device);
157}
158#else
159void __init at91_add_device_usba(struct usba_platform_data *data) {}
160#endif
161
162
163/* --------------------------------------------------------------------
164 * MMC / SD
165 * -------------------------------------------------------------------- */
166
167#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
168static u64 mmc_dmamask = DMA_BIT_MASK(32);
169static struct mci_platform_data mmc_data;
170
171static struct resource mmc_resources[] = {
172 [0] = {
173 .start = AT91SAM9RL_BASE_MCI,
174 .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
175 .flags = IORESOURCE_MEM,
176 },
177 [1] = {
178 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI,
179 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI,
180 .flags = IORESOURCE_IRQ,
181 },
182};
183
184static struct platform_device at91sam9rl_mmc_device = {
185 .name = "atmel_mci",
186 .id = -1,
187 .dev = {
188 .dma_mask = &mmc_dmamask,
189 .coherent_dma_mask = DMA_BIT_MASK(32),
190 .platform_data = &mmc_data,
191 },
192 .resource = mmc_resources,
193 .num_resources = ARRAY_SIZE(mmc_resources),
194};
195
196void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
197{
198 if (!data)
199 return;
200
201 if (data->slot[0].bus_width) {
202 /* input/irq */
203 if (gpio_is_valid(data->slot[0].detect_pin)) {
204 at91_set_gpio_input(data->slot[0].detect_pin, 1);
205 at91_set_deglitch(data->slot[0].detect_pin, 1);
206 }
207 if (gpio_is_valid(data->slot[0].wp_pin))
208 at91_set_gpio_input(data->slot[0].wp_pin, 1);
209
210 /* CLK */
211 at91_set_A_periph(AT91_PIN_PA2, 0);
212
213 /* CMD */
214 at91_set_A_periph(AT91_PIN_PA1, 1);
215
216 /* DAT0, maybe DAT1..DAT3 */
217 at91_set_A_periph(AT91_PIN_PA0, 1);
218 if (data->slot[0].bus_width == 4) {
219 at91_set_A_periph(AT91_PIN_PA3, 1);
220 at91_set_A_periph(AT91_PIN_PA4, 1);
221 at91_set_A_periph(AT91_PIN_PA5, 1);
222 }
223
224 mmc_data = *data;
225 platform_device_register(&at91sam9rl_mmc_device);
226 }
227}
228#else
229void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
230#endif
231
232
233/* --------------------------------------------------------------------
234 * NAND / SmartMedia
235 * -------------------------------------------------------------------- */
236
237#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
238static struct atmel_nand_data nand_data;
239
240#define NAND_BASE AT91_CHIPSELECT_3
241
242static struct resource nand_resources[] = {
243 [0] = {
244 .start = NAND_BASE,
245 .end = NAND_BASE + SZ_256M - 1,
246 .flags = IORESOURCE_MEM,
247 },
248 [1] = {
249 .start = AT91SAM9RL_BASE_ECC,
250 .end = AT91SAM9RL_BASE_ECC + SZ_512 - 1,
251 .flags = IORESOURCE_MEM,
252 }
253};
254
255static struct platform_device atmel_nand_device = {
256 .name = "atmel_nand",
257 .id = -1,
258 .dev = {
259 .platform_data = &nand_data,
260 },
261 .resource = nand_resources,
262 .num_resources = ARRAY_SIZE(nand_resources),
263};
264
265void __init at91_add_device_nand(struct atmel_nand_data *data)
266{
267 unsigned long csa;
268
269 if (!data)
270 return;
271
272 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
273 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
274
275 /* enable pin */
276 if (gpio_is_valid(data->enable_pin))
277 at91_set_gpio_output(data->enable_pin, 1);
278
279 /* ready/busy pin */
280 if (gpio_is_valid(data->rdy_pin))
281 at91_set_gpio_input(data->rdy_pin, 1);
282
283 /* card detect pin */
284 if (gpio_is_valid(data->det_pin))
285 at91_set_gpio_input(data->det_pin, 1);
286
287 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
288 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
289
290 nand_data = *data;
291 platform_device_register(&atmel_nand_device);
292}
293
294#else
295void __init at91_add_device_nand(struct atmel_nand_data *data) {}
296#endif
297
298
299/* --------------------------------------------------------------------
300 * TWI (i2c)
301 * -------------------------------------------------------------------- */
302
303/*
304 * Prefer the GPIO code since the TWI controller isn't robust
305 * (gets overruns and underruns under load) and can only issue
306 * repeated STARTs in one scenario (the driver doesn't yet handle them).
307 */
308#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
309
310static struct i2c_gpio_platform_data pdata = {
311 .sda_pin = AT91_PIN_PA23,
312 .sda_is_open_drain = 1,
313 .scl_pin = AT91_PIN_PA24,
314 .scl_is_open_drain = 1,
315 .udelay = 2, /* ~100 kHz */
316};
317
318static struct platform_device at91sam9rl_twi_device = {
319 .name = "i2c-gpio",
320 .id = 0,
321 .dev.platform_data = &pdata,
322};
323
324void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
325{
326 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
327 at91_set_multi_drive(AT91_PIN_PA23, 1);
328
329 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
330 at91_set_multi_drive(AT91_PIN_PA24, 1);
331
332 i2c_register_board_info(0, devices, nr_devices);
333 platform_device_register(&at91sam9rl_twi_device);
334}
335
336#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
337
338static struct resource twi_resources[] = {
339 [0] = {
340 .start = AT91SAM9RL_BASE_TWI0,
341 .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
342 .flags = IORESOURCE_MEM,
343 },
344 [1] = {
345 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0,
346 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0,
347 .flags = IORESOURCE_IRQ,
348 },
349};
350
351static struct platform_device at91sam9rl_twi_device = {
352 .name = "i2c-at91sam9g20",
353 .id = 0,
354 .resource = twi_resources,
355 .num_resources = ARRAY_SIZE(twi_resources),
356};
357
358void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
359{
360 /* pins used for TWI interface */
361 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
362 at91_set_multi_drive(AT91_PIN_PA23, 1);
363
364 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
365 at91_set_multi_drive(AT91_PIN_PA24, 1);
366
367 i2c_register_board_info(0, devices, nr_devices);
368 platform_device_register(&at91sam9rl_twi_device);
369}
370#else
371void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
372#endif
373
374
375/* --------------------------------------------------------------------
376 * SPI
377 * -------------------------------------------------------------------- */
378
379#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
380static u64 spi_dmamask = DMA_BIT_MASK(32);
381
382static struct resource spi_resources[] = {
383 [0] = {
384 .start = AT91SAM9RL_BASE_SPI,
385 .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
386 .flags = IORESOURCE_MEM,
387 },
388 [1] = {
389 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI,
390 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI,
391 .flags = IORESOURCE_IRQ,
392 },
393};
394
395static struct platform_device at91sam9rl_spi_device = {
396 .name = "atmel_spi",
397 .id = 0,
398 .dev = {
399 .dma_mask = &spi_dmamask,
400 .coherent_dma_mask = DMA_BIT_MASK(32),
401 },
402 .resource = spi_resources,
403 .num_resources = ARRAY_SIZE(spi_resources),
404};
405
406static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
407
408
409void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
410{
411 int i;
412 unsigned long cs_pin;
413
414 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
415 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
416 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
417
418 /* Enable SPI chip-selects */
419 for (i = 0; i < nr_devices; i++) {
420 if (devices[i].controller_data)
421 cs_pin = (unsigned long) devices[i].controller_data;
422 else
423 cs_pin = spi_standard_cs[devices[i].chip_select];
424
425 if (!gpio_is_valid(cs_pin))
426 continue;
427
428 /* enable chip-select pin */
429 at91_set_gpio_output(cs_pin, 1);
430
431 /* pass chip-select pin to driver */
432 devices[i].controller_data = (void *) cs_pin;
433 }
434
435 spi_register_board_info(devices, nr_devices);
436 platform_device_register(&at91sam9rl_spi_device);
437}
438#else
439void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
440#endif
441
442
443/* --------------------------------------------------------------------
444 * AC97
445 * -------------------------------------------------------------------- */
446
447#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
448static u64 ac97_dmamask = DMA_BIT_MASK(32);
449static struct ac97c_platform_data ac97_data;
450
451static struct resource ac97_resources[] = {
452 [0] = {
453 .start = AT91SAM9RL_BASE_AC97C,
454 .end = AT91SAM9RL_BASE_AC97C + SZ_16K - 1,
455 .flags = IORESOURCE_MEM,
456 },
457 [1] = {
458 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C,
459 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C,
460 .flags = IORESOURCE_IRQ,
461 },
462};
463
464static struct platform_device at91sam9rl_ac97_device = {
465 .name = "atmel_ac97c",
466 .id = 0,
467 .dev = {
468 .dma_mask = &ac97_dmamask,
469 .coherent_dma_mask = DMA_BIT_MASK(32),
470 .platform_data = &ac97_data,
471 },
472 .resource = ac97_resources,
473 .num_resources = ARRAY_SIZE(ac97_resources),
474};
475
476void __init at91_add_device_ac97(struct ac97c_platform_data *data)
477{
478 if (!data)
479 return;
480
481 at91_set_A_periph(AT91_PIN_PD1, 0); /* AC97FS */
482 at91_set_A_periph(AT91_PIN_PD2, 0); /* AC97CK */
483 at91_set_A_periph(AT91_PIN_PD3, 0); /* AC97TX */
484 at91_set_A_periph(AT91_PIN_PD4, 0); /* AC97RX */
485
486 /* reset */
487 if (gpio_is_valid(data->reset_pin))
488 at91_set_gpio_output(data->reset_pin, 0);
489
490 ac97_data = *data;
491 platform_device_register(&at91sam9rl_ac97_device);
492}
493#else
494void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
495#endif
496
497
498/* --------------------------------------------------------------------
499 * LCD Controller
500 * -------------------------------------------------------------------- */
501
502#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
503static u64 lcdc_dmamask = DMA_BIT_MASK(32);
504static struct atmel_lcdfb_pdata lcdc_data;
505
506static struct resource lcdc_resources[] = {
507 [0] = {
508 .start = AT91SAM9RL_LCDC_BASE,
509 .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
510 .flags = IORESOURCE_MEM,
511 },
512 [1] = {
513 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC,
514 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC,
515 .flags = IORESOURCE_IRQ,
516 },
517};
518
519static struct platform_device at91_lcdc_device = {
520 .name = "at91sam9rl-lcdfb",
521 .id = 0,
522 .dev = {
523 .dma_mask = &lcdc_dmamask,
524 .coherent_dma_mask = DMA_BIT_MASK(32),
525 .platform_data = &lcdc_data,
526 },
527 .resource = lcdc_resources,
528 .num_resources = ARRAY_SIZE(lcdc_resources),
529};
530
531void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data)
532{
533 if (!data) {
534 return;
535 }
536
537 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
538 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
539 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
540 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
541 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
542 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
543 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
544 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
545 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
546 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
547 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
548 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
549 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
550 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
551 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
552 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
553 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
554 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
555 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
556 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
557 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
558
559 lcdc_data = *data;
560 platform_device_register(&at91_lcdc_device);
561}
562#else
563void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {}
564#endif
565
566
567/* --------------------------------------------------------------------
568 * Timer/Counter block
569 * -------------------------------------------------------------------- */
570
571#ifdef CONFIG_ATMEL_TCLIB
572
573static struct resource tcb_resources[] = {
574 [0] = {
575 .start = AT91SAM9RL_BASE_TCB0,
576 .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
577 .flags = IORESOURCE_MEM,
578 },
579 [1] = {
580 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0,
581 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0,
582 .flags = IORESOURCE_IRQ,
583 },
584 [2] = {
585 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1,
586 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1,
587 .flags = IORESOURCE_IRQ,
588 },
589 [3] = {
590 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2,
591 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2,
592 .flags = IORESOURCE_IRQ,
593 },
594};
595
596static struct platform_device at91sam9rl_tcb_device = {
597 .name = "atmel_tcb",
598 .id = 0,
599 .resource = tcb_resources,
600 .num_resources = ARRAY_SIZE(tcb_resources),
601};
602
603static void __init at91_add_device_tc(void)
604{
605 platform_device_register(&at91sam9rl_tcb_device);
606}
607#else
608static void __init at91_add_device_tc(void) { }
609#endif
610
611
612/* --------------------------------------------------------------------
613 * ADC and Touchscreen
614 * -------------------------------------------------------------------- */
615
616#if IS_ENABLED(CONFIG_AT91_ADC)
617static struct at91_adc_data adc_data;
618
619static struct resource adc_resources[] = {
620 [0] = {
621 .start = AT91SAM9RL_BASE_TSC,
622 .end = AT91SAM9RL_BASE_TSC + SZ_16K - 1,
623 .flags = IORESOURCE_MEM,
624 },
625 [1] = {
626 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC,
627 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC,
628 .flags = IORESOURCE_IRQ,
629 }
630};
631
632static struct platform_device at91_adc_device = {
633 .name = "at91sam9rl-adc",
634 .id = -1,
635 .dev = {
636 .platform_data = &adc_data,
637 },
638 .resource = adc_resources,
639 .num_resources = ARRAY_SIZE(adc_resources),
640};
641
642static struct at91_adc_trigger at91_adc_triggers[] = {
643 [0] = {
644 .name = "external-rising",
645 .value = 1,
646 .is_external = true,
647 },
648 [1] = {
649 .name = "external-falling",
650 .value = 2,
651 .is_external = true,
652 },
653 [2] = {
654 .name = "external-any",
655 .value = 3,
656 .is_external = true,
657 },
658 [3] = {
659 .name = "continuous",
660 .value = 6,
661 .is_external = false,
662 },
663};
664
665void __init at91_add_device_adc(struct at91_adc_data *data)
666{
667 if (!data)
668 return;
669
670 if (test_bit(0, &data->channels_used))
671 at91_set_A_periph(AT91_PIN_PA17, 0);
672 if (test_bit(1, &data->channels_used))
673 at91_set_A_periph(AT91_PIN_PA18, 0);
674 if (test_bit(2, &data->channels_used))
675 at91_set_A_periph(AT91_PIN_PA19, 0);
676 if (test_bit(3, &data->channels_used))
677 at91_set_A_periph(AT91_PIN_PA20, 0);
678 if (test_bit(4, &data->channels_used))
679 at91_set_A_periph(AT91_PIN_PD6, 0);
680 if (test_bit(5, &data->channels_used))
681 at91_set_A_periph(AT91_PIN_PD7, 0);
682
683 if (data->use_external_triggers)
684 at91_set_A_periph(AT91_PIN_PB15, 0);
685
686 data->startup_time = 40;
687 data->trigger_number = 4;
688 data->trigger_list = at91_adc_triggers;
689
690 adc_data = *data;
691 platform_device_register(&at91_adc_device);
692}
693#else
694void __init at91_add_device_adc(struct at91_adc_data *data) {}
695#endif
696
697/* --------------------------------------------------------------------
698 * RTC
699 * -------------------------------------------------------------------- */
700
701#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
702static struct platform_device at91sam9rl_rtc_device = {
703 .name = "at91_rtc",
704 .id = -1,
705 .num_resources = 0,
706};
707
708static void __init at91_add_device_rtc(void)
709{
710 platform_device_register(&at91sam9rl_rtc_device);
711}
712#else
713static void __init at91_add_device_rtc(void) {}
714#endif
715
716
717/* --------------------------------------------------------------------
718 * RTT
719 * -------------------------------------------------------------------- */
720
721static struct resource rtt_resources[] = {
722 {
723 .start = AT91SAM9RL_BASE_RTT,
724 .end = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
725 .flags = IORESOURCE_MEM,
726 }, {
727 .flags = IORESOURCE_MEM,
728 }, {
729 .flags = IORESOURCE_IRQ,
730 }
731};
732
733static struct platform_device at91sam9rl_rtt_device = {
734 .name = "at91_rtt",
735 .id = 0,
736 .resource = rtt_resources,
737};
738
739#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
740static void __init at91_add_device_rtt_rtc(void)
741{
742 at91sam9rl_rtt_device.name = "rtc-at91sam9";
743 /*
744 * The second resource is needed:
745 * GPBR will serve as the storage for RTC time offset
746 */
747 at91sam9rl_rtt_device.num_resources = 3;
748 rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
749 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
750 rtt_resources[1].end = rtt_resources[1].start + 3;
751 rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
752 rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
753}
754#else
755static void __init at91_add_device_rtt_rtc(void)
756{
757 /* Only one resource is needed: RTT not used as RTC */
758 at91sam9rl_rtt_device.num_resources = 1;
759}
760#endif
761
762static void __init at91_add_device_rtt(void)
763{
764 at91_add_device_rtt_rtc();
765 platform_device_register(&at91sam9rl_rtt_device);
766}
767
768
769/* --------------------------------------------------------------------
770 * Watchdog
771 * -------------------------------------------------------------------- */
772
773#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
774static struct resource wdt_resources[] = {
775 {
776 .start = AT91SAM9RL_BASE_WDT,
777 .end = AT91SAM9RL_BASE_WDT + SZ_16 - 1,
778 .flags = IORESOURCE_MEM,
779 }
780};
781
782static struct platform_device at91sam9rl_wdt_device = {
783 .name = "at91_wdt",
784 .id = -1,
785 .resource = wdt_resources,
786 .num_resources = ARRAY_SIZE(wdt_resources),
787};
788
789static void __init at91_add_device_watchdog(void)
790{
791 platform_device_register(&at91sam9rl_wdt_device);
792}
793#else
794static void __init at91_add_device_watchdog(void) {}
795#endif
796
797
798/* --------------------------------------------------------------------
799 * PWM
800 * --------------------------------------------------------------------*/
801
802#if IS_ENABLED(CONFIG_PWM_ATMEL)
803static struct resource pwm_resources[] = {
804 [0] = {
805 .start = AT91SAM9RL_BASE_PWMC,
806 .end = AT91SAM9RL_BASE_PWMC + SZ_16K - 1,
807 .flags = IORESOURCE_MEM,
808 },
809 [1] = {
810 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC,
811 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC,
812 .flags = IORESOURCE_IRQ,
813 },
814};
815
816static struct platform_device at91sam9rl_pwm0_device = {
817 .name = "at91sam9rl-pwm",
818 .id = -1,
819 .resource = pwm_resources,
820 .num_resources = ARRAY_SIZE(pwm_resources),
821};
822
823void __init at91_add_device_pwm(u32 mask)
824{
825 if (mask & (1 << AT91_PWM0))
826 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM0 */
827
828 if (mask & (1 << AT91_PWM1))
829 at91_set_B_periph(AT91_PIN_PB9, 1); /* enable PWM1 */
830
831 if (mask & (1 << AT91_PWM2))
832 at91_set_B_periph(AT91_PIN_PD5, 1); /* enable PWM2 */
833
834 if (mask & (1 << AT91_PWM3))
835 at91_set_B_periph(AT91_PIN_PD8, 1); /* enable PWM3 */
836
837 platform_device_register(&at91sam9rl_pwm0_device);
838}
839#else
840void __init at91_add_device_pwm(u32 mask) {}
841#endif
842
843
844/* --------------------------------------------------------------------
845 * SSC -- Synchronous Serial Controller
846 * -------------------------------------------------------------------- */
847
848#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
849static u64 ssc0_dmamask = DMA_BIT_MASK(32);
850
851static struct resource ssc0_resources[] = {
852 [0] = {
853 .start = AT91SAM9RL_BASE_SSC0,
854 .end = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1,
855 .flags = IORESOURCE_MEM,
856 },
857 [1] = {
858 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0,
859 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0,
860 .flags = IORESOURCE_IRQ,
861 },
862};
863
864static struct platform_device at91sam9rl_ssc0_device = {
865 .name = "at91rm9200_ssc",
866 .id = 0,
867 .dev = {
868 .dma_mask = &ssc0_dmamask,
869 .coherent_dma_mask = DMA_BIT_MASK(32),
870 },
871 .resource = ssc0_resources,
872 .num_resources = ARRAY_SIZE(ssc0_resources),
873};
874
875static inline void configure_ssc0_pins(unsigned pins)
876{
877 if (pins & ATMEL_SSC_TF)
878 at91_set_A_periph(AT91_PIN_PC0, 1);
879 if (pins & ATMEL_SSC_TK)
880 at91_set_A_periph(AT91_PIN_PC1, 1);
881 if (pins & ATMEL_SSC_TD)
882 at91_set_A_periph(AT91_PIN_PA15, 1);
883 if (pins & ATMEL_SSC_RD)
884 at91_set_A_periph(AT91_PIN_PA16, 1);
885 if (pins & ATMEL_SSC_RK)
886 at91_set_B_periph(AT91_PIN_PA10, 1);
887 if (pins & ATMEL_SSC_RF)
888 at91_set_B_periph(AT91_PIN_PA22, 1);
889}
890
891static u64 ssc1_dmamask = DMA_BIT_MASK(32);
892
893static struct resource ssc1_resources[] = {
894 [0] = {
895 .start = AT91SAM9RL_BASE_SSC1,
896 .end = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1,
897 .flags = IORESOURCE_MEM,
898 },
899 [1] = {
900 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1,
901 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1,
902 .flags = IORESOURCE_IRQ,
903 },
904};
905
906static struct platform_device at91sam9rl_ssc1_device = {
907 .name = "at91rm9200_ssc",
908 .id = 1,
909 .dev = {
910 .dma_mask = &ssc1_dmamask,
911 .coherent_dma_mask = DMA_BIT_MASK(32),
912 },
913 .resource = ssc1_resources,
914 .num_resources = ARRAY_SIZE(ssc1_resources),
915};
916
917static inline void configure_ssc1_pins(unsigned pins)
918{
919 if (pins & ATMEL_SSC_TF)
920 at91_set_B_periph(AT91_PIN_PA29, 1);
921 if (pins & ATMEL_SSC_TK)
922 at91_set_B_periph(AT91_PIN_PA30, 1);
923 if (pins & ATMEL_SSC_TD)
924 at91_set_B_periph(AT91_PIN_PA13, 1);
925 if (pins & ATMEL_SSC_RD)
926 at91_set_B_periph(AT91_PIN_PA14, 1);
927 if (pins & ATMEL_SSC_RK)
928 at91_set_B_periph(AT91_PIN_PA9, 1);
929 if (pins & ATMEL_SSC_RF)
930 at91_set_B_periph(AT91_PIN_PA8, 1);
931}
932
933/*
934 * SSC controllers are accessed through library code, instead of any
935 * kind of all-singing/all-dancing driver. For example one could be
936 * used by a particular I2S audio codec's driver, while another one
937 * on the same system might be used by a custom data capture driver.
938 */
939void __init at91_add_device_ssc(unsigned id, unsigned pins)
940{
941 struct platform_device *pdev;
942
943 /*
944 * NOTE: caller is responsible for passing information matching
945 * "pins" to whatever will be using each particular controller.
946 */
947 switch (id) {
948 case AT91SAM9RL_ID_SSC0:
949 pdev = &at91sam9rl_ssc0_device;
950 configure_ssc0_pins(pins);
951 break;
952 case AT91SAM9RL_ID_SSC1:
953 pdev = &at91sam9rl_ssc1_device;
954 configure_ssc1_pins(pins);
955 break;
956 default:
957 return;
958 }
959
960 platform_device_register(pdev);
961}
962
963#else
964void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
965#endif
966
967
968/* --------------------------------------------------------------------
969 * UART
970 * -------------------------------------------------------------------- */
971
972#if defined(CONFIG_SERIAL_ATMEL)
973static struct resource dbgu_resources[] = {
974 [0] = {
975 .start = AT91SAM9RL_BASE_DBGU,
976 .end = AT91SAM9RL_BASE_DBGU + SZ_512 - 1,
977 .flags = IORESOURCE_MEM,
978 },
979 [1] = {
980 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
981 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
982 .flags = IORESOURCE_IRQ,
983 },
984};
985
986static struct atmel_uart_data dbgu_data = {
987 .use_dma_tx = 0,
988 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
989};
990
991static u64 dbgu_dmamask = DMA_BIT_MASK(32);
992
993static struct platform_device at91sam9rl_dbgu_device = {
994 .name = "atmel_usart",
995 .id = 0,
996 .dev = {
997 .dma_mask = &dbgu_dmamask,
998 .coherent_dma_mask = DMA_BIT_MASK(32),
999 .platform_data = &dbgu_data,
1000 },
1001 .resource = dbgu_resources,
1002 .num_resources = ARRAY_SIZE(dbgu_resources),
1003};
1004
1005static inline void configure_dbgu_pins(void)
1006{
1007 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
1008 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
1009}
1010
1011static struct resource uart0_resources[] = {
1012 [0] = {
1013 .start = AT91SAM9RL_BASE_US0,
1014 .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
1015 .flags = IORESOURCE_MEM,
1016 },
1017 [1] = {
1018 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0,
1019 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0,
1020 .flags = IORESOURCE_IRQ,
1021 },
1022};
1023
1024static struct atmel_uart_data uart0_data = {
1025 .use_dma_tx = 1,
1026 .use_dma_rx = 1,
1027};
1028
1029static u64 uart0_dmamask = DMA_BIT_MASK(32);
1030
1031static struct platform_device at91sam9rl_uart0_device = {
1032 .name = "atmel_usart",
1033 .id = 1,
1034 .dev = {
1035 .dma_mask = &uart0_dmamask,
1036 .coherent_dma_mask = DMA_BIT_MASK(32),
1037 .platform_data = &uart0_data,
1038 },
1039 .resource = uart0_resources,
1040 .num_resources = ARRAY_SIZE(uart0_resources),
1041};
1042
1043static inline void configure_usart0_pins(unsigned pins)
1044{
1045 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
1046 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
1047
1048 if (pins & ATMEL_UART_RTS)
1049 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
1050 if (pins & ATMEL_UART_CTS)
1051 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
1052 if (pins & ATMEL_UART_DSR)
1053 at91_set_A_periph(AT91_PIN_PD14, 0); /* DSR0 */
1054 if (pins & ATMEL_UART_DTR)
1055 at91_set_A_periph(AT91_PIN_PD15, 0); /* DTR0 */
1056 if (pins & ATMEL_UART_DCD)
1057 at91_set_A_periph(AT91_PIN_PD16, 0); /* DCD0 */
1058 if (pins & ATMEL_UART_RI)
1059 at91_set_A_periph(AT91_PIN_PD17, 0); /* RI0 */
1060}
1061
1062static struct resource uart1_resources[] = {
1063 [0] = {
1064 .start = AT91SAM9RL_BASE_US1,
1065 .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
1066 .flags = IORESOURCE_MEM,
1067 },
1068 [1] = {
1069 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1,
1070 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1,
1071 .flags = IORESOURCE_IRQ,
1072 },
1073};
1074
1075static struct atmel_uart_data uart1_data = {
1076 .use_dma_tx = 1,
1077 .use_dma_rx = 1,
1078};
1079
1080static u64 uart1_dmamask = DMA_BIT_MASK(32);
1081
1082static struct platform_device at91sam9rl_uart1_device = {
1083 .name = "atmel_usart",
1084 .id = 2,
1085 .dev = {
1086 .dma_mask = &uart1_dmamask,
1087 .coherent_dma_mask = DMA_BIT_MASK(32),
1088 .platform_data = &uart1_data,
1089 },
1090 .resource = uart1_resources,
1091 .num_resources = ARRAY_SIZE(uart1_resources),
1092};
1093
1094static inline void configure_usart1_pins(unsigned pins)
1095{
1096 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
1097 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
1098
1099 if (pins & ATMEL_UART_RTS)
1100 at91_set_B_periph(AT91_PIN_PA18, 0); /* RTS1 */
1101 if (pins & ATMEL_UART_CTS)
1102 at91_set_B_periph(AT91_PIN_PA19, 0); /* CTS1 */
1103}
1104
1105static struct resource uart2_resources[] = {
1106 [0] = {
1107 .start = AT91SAM9RL_BASE_US2,
1108 .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
1109 .flags = IORESOURCE_MEM,
1110 },
1111 [1] = {
1112 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2,
1113 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2,
1114 .flags = IORESOURCE_IRQ,
1115 },
1116};
1117
1118static struct atmel_uart_data uart2_data = {
1119 .use_dma_tx = 1,
1120 .use_dma_rx = 1,
1121};
1122
1123static u64 uart2_dmamask = DMA_BIT_MASK(32);
1124
1125static struct platform_device at91sam9rl_uart2_device = {
1126 .name = "atmel_usart",
1127 .id = 3,
1128 .dev = {
1129 .dma_mask = &uart2_dmamask,
1130 .coherent_dma_mask = DMA_BIT_MASK(32),
1131 .platform_data = &uart2_data,
1132 },
1133 .resource = uart2_resources,
1134 .num_resources = ARRAY_SIZE(uart2_resources),
1135};
1136
1137static inline void configure_usart2_pins(unsigned pins)
1138{
1139 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
1140 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
1141
1142 if (pins & ATMEL_UART_RTS)
1143 at91_set_A_periph(AT91_PIN_PA29, 0); /* RTS2 */
1144 if (pins & ATMEL_UART_CTS)
1145 at91_set_A_periph(AT91_PIN_PA30, 0); /* CTS2 */
1146}
1147
1148static struct resource uart3_resources[] = {
1149 [0] = {
1150 .start = AT91SAM9RL_BASE_US3,
1151 .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
1152 .flags = IORESOURCE_MEM,
1153 },
1154 [1] = {
1155 .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3,
1156 .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3,
1157 .flags = IORESOURCE_IRQ,
1158 },
1159};
1160
1161static struct atmel_uart_data uart3_data = {
1162 .use_dma_tx = 1,
1163 .use_dma_rx = 1,
1164};
1165
1166static u64 uart3_dmamask = DMA_BIT_MASK(32);
1167
1168static struct platform_device at91sam9rl_uart3_device = {
1169 .name = "atmel_usart",
1170 .id = 4,
1171 .dev = {
1172 .dma_mask = &uart3_dmamask,
1173 .coherent_dma_mask = DMA_BIT_MASK(32),
1174 .platform_data = &uart3_data,
1175 },
1176 .resource = uart3_resources,
1177 .num_resources = ARRAY_SIZE(uart3_resources),
1178};
1179
1180static inline void configure_usart3_pins(unsigned pins)
1181{
1182 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
1183 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
1184
1185 if (pins & ATMEL_UART_RTS)
1186 at91_set_B_periph(AT91_PIN_PD4, 0); /* RTS3 */
1187 if (pins & ATMEL_UART_CTS)
1188 at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */
1189}
1190
1191static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1192
1193void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1194{
1195 struct platform_device *pdev;
1196 struct atmel_uart_data *pdata;
1197
1198 switch (id) {
1199 case 0: /* DBGU */
1200 pdev = &at91sam9rl_dbgu_device;
1201 configure_dbgu_pins();
1202 break;
1203 case AT91SAM9RL_ID_US0:
1204 pdev = &at91sam9rl_uart0_device;
1205 configure_usart0_pins(pins);
1206 break;
1207 case AT91SAM9RL_ID_US1:
1208 pdev = &at91sam9rl_uart1_device;
1209 configure_usart1_pins(pins);
1210 break;
1211 case AT91SAM9RL_ID_US2:
1212 pdev = &at91sam9rl_uart2_device;
1213 configure_usart2_pins(pins);
1214 break;
1215 case AT91SAM9RL_ID_US3:
1216 pdev = &at91sam9rl_uart3_device;
1217 configure_usart3_pins(pins);
1218 break;
1219 default:
1220 return;
1221 }
1222 pdata = pdev->dev.platform_data;
1223 pdata->num = portnr; /* update to mapped ID */
1224
1225 if (portnr < ATMEL_MAX_UART)
1226 at91_uarts[portnr] = pdev;
1227}
1228
1229void __init at91_add_device_serial(void)
1230{
1231 int i;
1232
1233 for (i = 0; i < ATMEL_MAX_UART; i++) {
1234 if (at91_uarts[i])
1235 platform_device_register(at91_uarts[i]);
1236 }
1237}
1238#else
1239void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1240void __init at91_add_device_serial(void) {}
1241#endif
1242
1243
1244/* -------------------------------------------------------------------- */
1245
1246/*
1247 * These devices are always present and don't need any board-specific
1248 * setup.
1249 */
1250static int __init at91_add_standard_devices(void)
1251{
1252 at91_add_device_hdmac();
1253 at91_add_device_rtc();
1254 at91_add_device_rtt();
1255 at91_add_device_watchdog();
1256 at91_add_device_tc();
1257 return 0;
1258}
1259
1260arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
deleted file mode 100644
index 8bca329b0293..000000000000
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ /dev/null
@@ -1,333 +0,0 @@
1/*
2 * Copyright (C) 2005 SAN People
3 * Copyright (C) 2007 Atmel Corporation
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file COPYING in the main directory of this archive for
7 * more details.
8 */
9
10#include <linux/types.h>
11#include <linux/gpio.h>
12#include <linux/init.h>
13#include <linux/mm.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/spi/spi.h>
17#include <linux/fb.h>
18#include <linux/clk.h>
19#include <linux/input.h>
20#include <linux/gpio_keys.h>
21#include <linux/platform_data/at91_adc.h>
22
23#include <video/atmel_lcdc.h>
24
25#include <asm/setup.h>
26#include <asm/mach-types.h>
27#include <asm/irq.h>
28
29#include <asm/mach/arch.h>
30#include <asm/mach/map.h>
31#include <asm/mach/irq.h>
32
33#include <mach/hardware.h>
34#include <mach/at91sam9_smc.h>
35
36
37#include "at91_aic.h"
38#include "board.h"
39#include "sam9_smc.h"
40#include "generic.h"
41#include "gpio.h"
42
43
44static void __init ek_init_early(void)
45{
46 /* Initialize processor: 12.000 MHz crystal */
47 at91_initialize(12000000);
48}
49
50/*
51 * USB HS Device port
52 */
53static struct usba_platform_data __initdata ek_usba_udc_data = {
54 .vbus_pin = AT91_PIN_PA8,
55};
56
57
58/*
59 * MCI (SD/MMC)
60 */
61static struct mci_platform_data __initdata mci0_data = {
62 .slot[0] = {
63 .bus_width = 4,
64 .detect_pin = AT91_PIN_PA15,
65 .wp_pin = -EINVAL,
66 },
67};
68
69
70/*
71 * NAND flash
72 */
73static struct mtd_partition __initdata ek_nand_partition[] = {
74 {
75 .name = "Partition 1",
76 .offset = 0,
77 .size = SZ_256K,
78 },
79 {
80 .name = "Partition 2",
81 .offset = MTDPART_OFS_NXTBLK,
82 .size = MTDPART_SIZ_FULL,
83 },
84};
85
86static struct atmel_nand_data __initdata ek_nand_data = {
87 .ale = 21,
88 .cle = 22,
89 .det_pin = -EINVAL,
90 .rdy_pin = AT91_PIN_PD17,
91 .enable_pin = AT91_PIN_PB6,
92 .ecc_mode = NAND_ECC_SOFT,
93 .on_flash_bbt = 1,
94 .parts = ek_nand_partition,
95 .num_parts = ARRAY_SIZE(ek_nand_partition),
96};
97
98static struct sam9_smc_config __initdata ek_nand_smc_config = {
99 .ncs_read_setup = 0,
100 .nrd_setup = 1,
101 .ncs_write_setup = 0,
102 .nwe_setup = 1,
103
104 .ncs_read_pulse = 3,
105 .nrd_pulse = 3,
106 .ncs_write_pulse = 3,
107 .nwe_pulse = 3,
108
109 .read_cycle = 5,
110 .write_cycle = 5,
111
112 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
113 .tdf_cycles = 2,
114};
115
116static void __init ek_add_device_nand(void)
117{
118 /* configure chip-select 3 (NAND) */
119 sam9_smc_configure(0, 3, &ek_nand_smc_config);
120
121 at91_add_device_nand(&ek_nand_data);
122}
123
124
125/*
126 * SPI devices
127 */
128static struct spi_board_info ek_spi_devices[] = {
129 { /* DataFlash chip */
130 .modalias = "mtd_dataflash",
131 .chip_select = 0,
132 .max_speed_hz = 15 * 1000 * 1000,
133 .bus_num = 0,
134 },
135};
136
137
138/*
139 * LCD Controller
140 */
141#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
142static struct fb_videomode at91_tft_vga_modes[] = {
143 {
144 .name = "TX09D50VM1CCA @ 60",
145 .refresh = 60,
146 .xres = 240, .yres = 320,
147 .pixclock = KHZ2PICOS(4965),
148
149 .left_margin = 1, .right_margin = 33,
150 .upper_margin = 1, .lower_margin = 0,
151 .hsync_len = 5, .vsync_len = 1,
152
153 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
154 .vmode = FB_VMODE_NONINTERLACED,
155 },
156};
157
158static struct fb_monspecs at91fb_default_monspecs = {
159 .manufacturer = "HIT",
160 .monitor = "TX09D50VM1CCA",
161
162 .modedb = at91_tft_vga_modes,
163 .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
164 .hfmin = 15000,
165 .hfmax = 64000,
166 .vfmin = 50,
167 .vfmax = 150,
168};
169
170#define AT91SAM9RL_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
171 | ATMEL_LCDC_DISTYPE_TFT \
172 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
173
174static void at91_lcdc_power_control(struct atmel_lcdfb_pdata *pdata, int on)
175{
176 if (on)
177 at91_set_gpio_value(AT91_PIN_PC1, 0); /* power up */
178 else
179 at91_set_gpio_value(AT91_PIN_PC1, 1); /* power down */
180}
181
182/* Driver datas */
183static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
184 .lcdcon_is_backlight = true,
185 .default_bpp = 16,
186 .default_dmacon = ATMEL_LCDC_DMAEN,
187 .default_lcdcon2 = AT91SAM9RL_DEFAULT_LCDCON2,
188 .default_monspecs = &at91fb_default_monspecs,
189 .atmel_lcdfb_power_control = at91_lcdc_power_control,
190 .guard_time = 1,
191 .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
192};
193
194#else
195static struct atmel_lcdfb_pdata __initdata ek_lcdc_data;
196#endif
197
198
199/*
200 * AC97
201 * reset_pin is not connected: NRST
202 */
203static struct ac97c_platform_data ek_ac97_data = {
204 .reset_pin = -EINVAL,
205};
206
207
208/*
209 * LEDs
210 */
211static struct gpio_led ek_leds[] = {
212 { /* "bottom" led, green, userled1 to be defined */
213 .name = "ds1",
214 .gpio = AT91_PIN_PD15,
215 .active_low = 1,
216 .default_trigger = "none",
217 },
218 { /* "bottom" led, green, userled2 to be defined */
219 .name = "ds2",
220 .gpio = AT91_PIN_PD16,
221 .active_low = 1,
222 .default_trigger = "none",
223 },
224 { /* "power" led, yellow */
225 .name = "ds3",
226 .gpio = AT91_PIN_PD14,
227 .default_trigger = "heartbeat",
228 }
229};
230
231
232/*
233 * ADC + Touchscreen
234 */
235static struct at91_adc_data ek_adc_data = {
236 .channels_used = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5),
237 .use_external_triggers = true,
238 .vref = 3300,
239 .touchscreen_type = ATMEL_ADC_TOUCHSCREEN_4WIRE,
240};
241
242
243/*
244 * GPIO Buttons
245 */
246#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
247static struct gpio_keys_button ek_buttons[] = {
248 {
249 .gpio = AT91_PIN_PB0,
250 .code = BTN_2,
251 .desc = "Right Click",
252 .active_low = 1,
253 .wakeup = 1,
254 },
255 {
256 .gpio = AT91_PIN_PB1,
257 .code = BTN_1,
258 .desc = "Left Click",
259 .active_low = 1,
260 .wakeup = 1,
261 }
262};
263
264static struct gpio_keys_platform_data ek_button_data = {
265 .buttons = ek_buttons,
266 .nbuttons = ARRAY_SIZE(ek_buttons),
267};
268
269static struct platform_device ek_button_device = {
270 .name = "gpio-keys",
271 .id = -1,
272 .num_resources = 0,
273 .dev = {
274 .platform_data = &ek_button_data,
275 }
276};
277
278static void __init ek_add_device_buttons(void)
279{
280 at91_set_gpio_input(AT91_PIN_PB1, 1); /* btn1 */
281 at91_set_deglitch(AT91_PIN_PB1, 1);
282 at91_set_gpio_input(AT91_PIN_PB0, 1); /* btn2 */
283 at91_set_deglitch(AT91_PIN_PB0, 1);
284
285 platform_device_register(&ek_button_device);
286}
287#else
288static void __init ek_add_device_buttons(void) {}
289#endif
290
291
292static void __init ek_board_init(void)
293{
294 at91_register_devices();
295
296 /* Serial */
297 /* DBGU on ttyS0. (Rx & Tx only) */
298 at91_register_uart(0, 0, 0);
299
300 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
301 at91_register_uart(AT91SAM9RL_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
302 at91_add_device_serial();
303 /* USB HS */
304 at91_add_device_usba(&ek_usba_udc_data);
305 /* I2C */
306 at91_add_device_i2c(NULL, 0);
307 /* NAND */
308 ek_add_device_nand();
309 /* SPI */
310 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
311 /* MMC */
312 at91_add_device_mci(0, &mci0_data);
313 /* LCD Controller */
314 at91_add_device_lcdc(&ek_lcdc_data);
315 /* AC97 */
316 at91_add_device_ac97(&ek_ac97_data);
317 /* Touch Screen Controller + ADC */
318 at91_add_device_adc(&ek_adc_data);
319 /* LEDs */
320 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
321 /* Push Buttons */
322 ek_add_device_buttons();
323}
324
325MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
326 /* Maintainer: Atmel */
327 .init_time = at91_init_time,
328 .map_io = at91_map_io,
329 .handle_irq = at91_aic_handle_irq,
330 .init_early = ek_init_early,
331 .init_irq = at91_init_irq_default,
332 .init_machine = ek_board_init,
333MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 07:32:27 -0500