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authorNicolas Ferre <nicolas.ferre@atmel.com>2014-11-21 06:09:27 -0500
committerNicolas Ferre <nicolas.ferre@atmel.com>2014-11-21 06:09:27 -0500
commit2e591e7b3ac20c8f686a6099d236d09964d08406 (patch)
tree9e170f72a29c38b74bdd4cee990520fecab03a93 /arch/arm/mach-at91
parent9373090d9f00b5006ec30c49c45f237787081094 (diff)
ARM: at91: remove at91sam9261/at91sam9g10 legacy board support
Remove legacy support for at91sam9261/at91sam9g10 boards. This include board files removal plus all legacy code for non DT boards support. Use the Device Tree for running this board with newer kernels. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/Kconfig.non_dt34
-rw-r--r--arch/arm/mach-at91/Makefile5
-rw-r--r--arch/arm/mach-at91/at91sam9261.c375
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c1098
-rw-r--r--arch/arm/mach-at91/board-sam9261ek.c623
5 files changed, 0 insertions, 2135 deletions
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index 079772047541..5fc138da89fb 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -15,18 +15,8 @@ config ARCH_AT91RM9200
15 select AT91_USE_OLD_CLK 15 select AT91_USE_OLD_CLK
16 select OLD_IRQ_AT91 16 select OLD_IRQ_AT91
17 17
18config ARCH_AT91SAM9261
19 bool "AT91SAM9261 or AT91SAM9G10"
20 select SOC_AT91SAM9261
21 select AT91_USE_OLD_CLK
22 select OLD_IRQ_AT91
23
24endchoice 18endchoice
25 19
26config ARCH_AT91SAM9G10
27 bool
28 select ARCH_AT91SAM9261
29
30# ---------------------------------------------------------- 20# ----------------------------------------------------------
31 21
32if ARCH_AT91RM9200 22if ARCH_AT91RM9200
@@ -113,30 +103,6 @@ endif
113 103
114# ---------------------------------------------------------- 104# ----------------------------------------------------------
115 105
116if ARCH_AT91SAM9261
117
118comment "AT91SAM9261 Board Type"
119
120config MACH_AT91SAM9261EK
121 bool "Atmel AT91SAM9261-EK Evaluation Kit"
122 select HAVE_AT91_DATAFLASH_CARD
123 help
124 Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
125 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
126
127comment "AT91SAM9G10 Board Type"
128
129config MACH_AT91SAM9G10EK
130 bool "Atmel AT91SAM9G10-EK Evaluation Kit"
131 select HAVE_AT91_DATAFLASH_CARD
132 help
133 Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
134 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
135
136endif
137
138# ----------------------------------------------------------
139
140comment "AT91 Board Options" 106comment "AT91 Board Options"
141 107
142config MTD_AT91_DATAFLASH_CARD 108config MTD_AT91_DATAFLASH_CARD
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index bfe918b5fbc5..b2495d71f7ac 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o
21obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o 21obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
22 22
23obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o 23obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o
24obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261_devices.o
25 24
26# AT91RM9200 board-specific support 25# AT91RM9200 board-specific support
27obj-$(CONFIG_MACH_ONEARM) += board-1arm.o 26obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
@@ -38,10 +37,6 @@ obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o
38obj-$(CONFIG_MACH_CPUAT91) += board-cpuat91.o 37obj-$(CONFIG_MACH_CPUAT91) += board-cpuat91.o
39obj-$(CONFIG_MACH_ECO920) += board-eco920.o 38obj-$(CONFIG_MACH_ECO920) += board-eco920.o
40 39
41# AT91SAM9261 board-specific support
42obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
43obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
44
45# AT91SAM board with device-tree 40# AT91SAM board with device-tree
46obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o 41obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o
47obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o 42obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index a8bd35963332..d29953ecb0c4 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -10,282 +10,12 @@
10 * 10 *
11 */ 11 */
12 12
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/clk/at91_pmc.h>
16
17#include <asm/proc-fns.h>
18#include <asm/irq.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21#include <asm/system_misc.h> 13#include <asm/system_misc.h>
22#include <mach/cpu.h> 14#include <mach/cpu.h>
23#include <mach/at91sam9261.h>
24#include <mach/hardware.h> 15#include <mach/hardware.h>
25 16
26#include "at91_aic.h"
27#include "soc.h" 17#include "soc.h"
28#include "generic.h" 18#include "generic.h"
29#include "sam9_smc.h"
30#include "pm.h"
31
32#if defined(CONFIG_OLD_CLK_AT91)
33#include "clock.h"
34
35/* --------------------------------------------------------------------
36 * Clocks
37 * -------------------------------------------------------------------- */
38
39/*
40 * The peripheral clocks.
41 */
42static struct clk pioA_clk = {
43 .name = "pioA_clk",
44 .pmc_mask = 1 << AT91SAM9261_ID_PIOA,
45 .type = CLK_TYPE_PERIPHERAL,
46};
47static struct clk pioB_clk = {
48 .name = "pioB_clk",
49 .pmc_mask = 1 << AT91SAM9261_ID_PIOB,
50 .type = CLK_TYPE_PERIPHERAL,
51};
52static struct clk pioC_clk = {
53 .name = "pioC_clk",
54 .pmc_mask = 1 << AT91SAM9261_ID_PIOC,
55 .type = CLK_TYPE_PERIPHERAL,
56};
57static struct clk usart0_clk = {
58 .name = "usart0_clk",
59 .pmc_mask = 1 << AT91SAM9261_ID_US0,
60 .type = CLK_TYPE_PERIPHERAL,
61};
62static struct clk usart1_clk = {
63 .name = "usart1_clk",
64 .pmc_mask = 1 << AT91SAM9261_ID_US1,
65 .type = CLK_TYPE_PERIPHERAL,
66};
67static struct clk usart2_clk = {
68 .name = "usart2_clk",
69 .pmc_mask = 1 << AT91SAM9261_ID_US2,
70 .type = CLK_TYPE_PERIPHERAL,
71};
72static struct clk mmc_clk = {
73 .name = "mci_clk",
74 .pmc_mask = 1 << AT91SAM9261_ID_MCI,
75 .type = CLK_TYPE_PERIPHERAL,
76};
77static struct clk udc_clk = {
78 .name = "udc_clk",
79 .pmc_mask = 1 << AT91SAM9261_ID_UDP,
80 .type = CLK_TYPE_PERIPHERAL,
81};
82static struct clk twi_clk = {
83 .name = "twi_clk",
84 .pmc_mask = 1 << AT91SAM9261_ID_TWI,
85 .type = CLK_TYPE_PERIPHERAL,
86};
87static struct clk spi0_clk = {
88 .name = "spi0_clk",
89 .pmc_mask = 1 << AT91SAM9261_ID_SPI0,
90 .type = CLK_TYPE_PERIPHERAL,
91};
92static struct clk spi1_clk = {
93 .name = "spi1_clk",
94 .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
95 .type = CLK_TYPE_PERIPHERAL,
96};
97static struct clk ssc0_clk = {
98 .name = "ssc0_clk",
99 .pmc_mask = 1 << AT91SAM9261_ID_SSC0,
100 .type = CLK_TYPE_PERIPHERAL,
101};
102static struct clk ssc1_clk = {
103 .name = "ssc1_clk",
104 .pmc_mask = 1 << AT91SAM9261_ID_SSC1,
105 .type = CLK_TYPE_PERIPHERAL,
106};
107static struct clk ssc2_clk = {
108 .name = "ssc2_clk",
109 .pmc_mask = 1 << AT91SAM9261_ID_SSC2,
110 .type = CLK_TYPE_PERIPHERAL,
111};
112static struct clk tc0_clk = {
113 .name = "tc0_clk",
114 .pmc_mask = 1 << AT91SAM9261_ID_TC0,
115 .type = CLK_TYPE_PERIPHERAL,
116};
117static struct clk tc1_clk = {
118 .name = "tc1_clk",
119 .pmc_mask = 1 << AT91SAM9261_ID_TC1,
120 .type = CLK_TYPE_PERIPHERAL,
121};
122static struct clk tc2_clk = {
123 .name = "tc2_clk",
124 .pmc_mask = 1 << AT91SAM9261_ID_TC2,
125 .type = CLK_TYPE_PERIPHERAL,
126};
127static struct clk ohci_clk = {
128 .name = "ohci_clk",
129 .pmc_mask = 1 << AT91SAM9261_ID_UHP,
130 .type = CLK_TYPE_PERIPHERAL,
131};
132static struct clk lcdc_clk = {
133 .name = "lcdc_clk",
134 .pmc_mask = 1 << AT91SAM9261_ID_LCDC,
135 .type = CLK_TYPE_PERIPHERAL,
136};
137
138/* HClocks */
139static struct clk hck0 = {
140 .name = "hck0",
141 .pmc_mask = AT91_PMC_HCK0,
142 .type = CLK_TYPE_SYSTEM,
143 .id = 0,
144};
145static struct clk hck1 = {
146 .name = "hck1",
147 .pmc_mask = AT91_PMC_HCK1,
148 .type = CLK_TYPE_SYSTEM,
149 .id = 1,
150};
151
152static struct clk *periph_clocks[] __initdata = {
153 &pioA_clk,
154 &pioB_clk,
155 &pioC_clk,
156 &usart0_clk,
157 &usart1_clk,
158 &usart2_clk,
159 &mmc_clk,
160 &udc_clk,
161 &twi_clk,
162 &spi0_clk,
163 &spi1_clk,
164 &ssc0_clk,
165 &ssc1_clk,
166 &ssc2_clk,
167 &tc0_clk,
168 &tc1_clk,
169 &tc2_clk,
170 &ohci_clk,
171 &lcdc_clk,
172 // irq0 .. irq2
173};
174
175static struct clk_lookup periph_clocks_lookups[] = {
176 CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
177 CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
178 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
179 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
180 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
181 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
182 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
183 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
184 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
185 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
186 CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk),
187 CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk),
188 CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk),
189 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
190 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
191 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
192 CLKDEV_CON_ID("pioA", &pioA_clk),
193 CLKDEV_CON_ID("pioB", &pioB_clk),
194 CLKDEV_CON_ID("pioC", &pioC_clk),
195 /* more lookup table for DT entries */
196 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
197 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
198 CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
199 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
200 CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
201 CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
202 CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
203 CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &hck0),
204 CLKDEV_CON_DEV_ID("hclk", "600000.fb", &hck1),
205 CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
206 CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
207 CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
208 CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk),
209 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
210 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
211 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
212};
213
214static struct clk_lookup usart_clocks_lookups[] = {
215 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
216 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
217 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
218 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
219};
220
221/*
222 * The four programmable clocks.
223 * You must configure pin multiplexing to bring these signals out.
224 */
225static struct clk pck0 = {
226 .name = "pck0",
227 .pmc_mask = AT91_PMC_PCK0,
228 .type = CLK_TYPE_PROGRAMMABLE,
229 .id = 0,
230};
231static struct clk pck1 = {
232 .name = "pck1",
233 .pmc_mask = AT91_PMC_PCK1,
234 .type = CLK_TYPE_PROGRAMMABLE,
235 .id = 1,
236};
237static struct clk pck2 = {
238 .name = "pck2",
239 .pmc_mask = AT91_PMC_PCK2,
240 .type = CLK_TYPE_PROGRAMMABLE,
241 .id = 2,
242};
243static struct clk pck3 = {
244 .name = "pck3",
245 .pmc_mask = AT91_PMC_PCK3,
246 .type = CLK_TYPE_PROGRAMMABLE,
247 .id = 3,
248};
249
250static void __init at91sam9261_register_clocks(void)
251{
252 int i;
253
254 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
255 clk_register(periph_clocks[i]);
256
257 clkdev_add_table(periph_clocks_lookups,
258 ARRAY_SIZE(periph_clocks_lookups));
259 clkdev_add_table(usart_clocks_lookups,
260 ARRAY_SIZE(usart_clocks_lookups));
261
262 clk_register(&pck0);
263 clk_register(&pck1);
264 clk_register(&pck2);
265 clk_register(&pck3);
266
267 clk_register(&hck0);
268 clk_register(&hck1);
269}
270#else
271#define at91sam9261_register_clocks NULL
272#endif
273/* --------------------------------------------------------------------
274 * GPIO
275 * -------------------------------------------------------------------- */
276
277static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
278 {
279 .id = AT91SAM9261_ID_PIOA,
280 .regbase = AT91SAM9261_BASE_PIOA,
281 }, {
282 .id = AT91SAM9261_ID_PIOB,
283 .regbase = AT91SAM9261_BASE_PIOB,
284 }, {
285 .id = AT91SAM9261_ID_PIOC,
286 .regbase = AT91SAM9261_BASE_PIOC,
287 }
288};
289 19
290/* -------------------------------------------------------------------- 20/* --------------------------------------------------------------------
291 * AT91SAM9261 processor initialization 21 * AT91SAM9261 processor initialization
@@ -299,119 +29,14 @@ static void __init at91sam9261_map_io(void)
299 at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE); 29 at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
300} 30}
301 31
302static void __init at91sam9261_ioremap_registers(void)
303{
304 at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
305 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
306 at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
307 at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
308 at91_pm_set_standby(at91sam9_sdram_standby);
309}
310
311static void __init at91sam9261_initialize(void) 32static void __init at91sam9261_initialize(void)
312{ 33{
313 arm_pm_idle = at91sam9_idle; 34 arm_pm_idle = at91sam9_idle;
314 35
315 at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT); 36 at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT);
316
317 /* Register GPIO subsystem */
318 at91_gpio_init(at91sam9261_gpio, 3);
319}
320
321static struct resource rstc_resources[] = {
322 [0] = {
323 .start = AT91SAM9261_BASE_RSTC,
324 .end = AT91SAM9261_BASE_RSTC + SZ_16 - 1,
325 .flags = IORESOURCE_MEM,
326 },
327 [1] = {
328 .start = AT91SAM9261_BASE_SDRAMC,
329 .end = AT91SAM9261_BASE_SDRAMC + SZ_512 - 1,
330 .flags = IORESOURCE_MEM,
331 },
332};
333
334static struct platform_device rstc_device = {
335 .name = "at91-sam9260-reset",
336 .resource = rstc_resources,
337 .num_resources = ARRAY_SIZE(rstc_resources),
338};
339
340static struct resource shdwc_resources[] = {
341 [0] = {
342 .start = AT91SAM9261_BASE_SHDWC,
343 .end = AT91SAM9261_BASE_SHDWC + SZ_16 - 1,
344 .flags = IORESOURCE_MEM,
345 },
346};
347
348static struct platform_device shdwc_device = {
349 .name = "at91-poweroff",
350 .resource = shdwc_resources,
351 .num_resources = ARRAY_SIZE(shdwc_resources),
352};
353
354static void __init at91sam9261_register_devices(void)
355{
356 platform_device_register(&rstc_device);
357 platform_device_register(&shdwc_device);
358}
359
360/* --------------------------------------------------------------------
361 * Interrupt initialization
362 * -------------------------------------------------------------------- */
363
364/*
365 * The default interrupt priority levels (0 = lowest, 7 = highest).
366 */
367static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
368 7, /* Advanced Interrupt Controller */
369 7, /* System Peripherals */
370 1, /* Parallel IO Controller A */
371 1, /* Parallel IO Controller B */
372 1, /* Parallel IO Controller C */
373 0,
374 5, /* USART 0 */
375 5, /* USART 1 */
376 5, /* USART 2 */
377 0, /* Multimedia Card Interface */
378 2, /* USB Device Port */
379 6, /* Two-Wire Interface */
380 5, /* Serial Peripheral Interface 0 */
381 5, /* Serial Peripheral Interface 1 */
382 4, /* Serial Synchronous Controller 0 */
383 4, /* Serial Synchronous Controller 1 */
384 4, /* Serial Synchronous Controller 2 */
385 0, /* Timer Counter 0 */
386 0, /* Timer Counter 1 */
387 0, /* Timer Counter 2 */
388 2, /* USB Host port */
389 3, /* LCD Controller */
390 0,
391 0,
392 0,
393 0,
394 0,
395 0,
396 0,
397 0, /* Advanced Interrupt Controller */
398 0, /* Advanced Interrupt Controller */
399 0, /* Advanced Interrupt Controller */
400};
401
402static void __init at91sam9261_init_time(void)
403{
404 at91sam926x_pit_init(NR_IRQS_LEGACY + AT91_ID_SYS);
405} 37}
406 38
407AT91_SOC_START(at91sam9261) 39AT91_SOC_START(at91sam9261)
408 .map_io = at91sam9261_map_io, 40 .map_io = at91sam9261_map_io,
409 .default_irq_priority = at91sam9261_default_irq_priority,
410 .extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
411 | (1 << AT91SAM9261_ID_IRQ2),
412 .ioremap_registers = at91sam9261_ioremap_registers,
413 .register_clocks = at91sam9261_register_clocks,
414 .register_devices = at91sam9261_register_devices,
415 .init = at91sam9261_initialize, 41 .init = at91sam9261_initialize,
416 .init_time = at91sam9261_init_time,
417AT91_SOC_END 42AT91_SOC_END
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
deleted file mode 100644
index 29baacb5c359..000000000000
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ /dev/null
@@ -1,1098 +0,0 @@
1/*
2 * arch/arm/mach-at91/at91sam9261_devices.c
3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#include <asm/mach/arch.h>
14#include <asm/mach/map.h>
15
16#include <linux/dma-mapping.h>
17#include <linux/gpio.h>
18#include <linux/platform_device.h>
19#include <linux/i2c-gpio.h>
20
21#include <linux/fb.h>
22#include <video/atmel_lcdc.h>
23
24#include <mach/at91sam9261.h>
25#include <mach/at91sam9261_matrix.h>
26#include <mach/at91_matrix.h>
27#include <mach/at91sam9_smc.h>
28#include <mach/hardware.h>
29
30#include "board.h"
31#include "generic.h"
32#include "gpio.h"
33
34/* --------------------------------------------------------------------
35 * USB Host
36 * -------------------------------------------------------------------- */
37
38#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
39static u64 ohci_dmamask = DMA_BIT_MASK(32);
40static struct at91_usbh_data usbh_data;
41
42static struct resource usbh_resources[] = {
43 [0] = {
44 .start = AT91SAM9261_UHP_BASE,
45 .end = AT91SAM9261_UHP_BASE + SZ_1M - 1,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
49 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP,
50 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP,
51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55static struct platform_device at91sam9261_usbh_device = {
56 .name = "at91_ohci",
57 .id = -1,
58 .dev = {
59 .dma_mask = &ohci_dmamask,
60 .coherent_dma_mask = DMA_BIT_MASK(32),
61 .platform_data = &usbh_data,
62 },
63 .resource = usbh_resources,
64 .num_resources = ARRAY_SIZE(usbh_resources),
65};
66
67void __init at91_add_device_usbh(struct at91_usbh_data *data)
68{
69 int i;
70
71 if (!data)
72 return;
73
74 /* Enable overcurrent notification */
75 for (i = 0; i < data->ports; i++) {
76 if (gpio_is_valid(data->overcurrent_pin[i]))
77 at91_set_gpio_input(data->overcurrent_pin[i], 1);
78 }
79
80 usbh_data = *data;
81 platform_device_register(&at91sam9261_usbh_device);
82}
83#else
84void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
85#endif
86
87
88/* --------------------------------------------------------------------
89 * USB Device (Gadget)
90 * -------------------------------------------------------------------- */
91
92#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
93static struct at91_udc_data udc_data;
94
95static struct resource udc_resources[] = {
96 [0] = {
97 .start = AT91SAM9261_BASE_UDP,
98 .end = AT91SAM9261_BASE_UDP + SZ_16K - 1,
99 .flags = IORESOURCE_MEM,
100 },
101 [1] = {
102 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP,
103 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP,
104 .flags = IORESOURCE_IRQ,
105 },
106};
107
108static struct platform_device at91sam9261_udc_device = {
109 .name = "at91_udc",
110 .id = -1,
111 .dev = {
112 .platform_data = &udc_data,
113 },
114 .resource = udc_resources,
115 .num_resources = ARRAY_SIZE(udc_resources),
116};
117
118void __init at91_add_device_udc(struct at91_udc_data *data)
119{
120 if (!data)
121 return;
122
123 if (gpio_is_valid(data->vbus_pin)) {
124 at91_set_gpio_input(data->vbus_pin, 0);
125 at91_set_deglitch(data->vbus_pin, 1);
126 }
127
128 /* Pullup pin is handled internally by USB device peripheral */
129
130 udc_data = *data;
131 platform_device_register(&at91sam9261_udc_device);
132}
133#else
134void __init at91_add_device_udc(struct at91_udc_data *data) {}
135#endif
136
137/* --------------------------------------------------------------------
138 * MMC / SD
139 * -------------------------------------------------------------------- */
140
141#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
142static u64 mmc_dmamask = DMA_BIT_MASK(32);
143static struct mci_platform_data mmc_data;
144
145static struct resource mmc_resources[] = {
146 [0] = {
147 .start = AT91SAM9261_BASE_MCI,
148 .end = AT91SAM9261_BASE_MCI + SZ_16K - 1,
149 .flags = IORESOURCE_MEM,
150 },
151 [1] = {
152 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI,
153 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI,
154 .flags = IORESOURCE_IRQ,
155 },
156};
157
158static struct platform_device at91sam9261_mmc_device = {
159 .name = "atmel_mci",
160 .id = -1,
161 .dev = {
162 .dma_mask = &mmc_dmamask,
163 .coherent_dma_mask = DMA_BIT_MASK(32),
164 .platform_data = &mmc_data,
165 },
166 .resource = mmc_resources,
167 .num_resources = ARRAY_SIZE(mmc_resources),
168};
169
170void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
171{
172 if (!data)
173 return;
174
175 if (data->slot[0].bus_width) {
176 /* input/irq */
177 if (gpio_is_valid(data->slot[0].detect_pin)) {
178 at91_set_gpio_input(data->slot[0].detect_pin, 1);
179 at91_set_deglitch(data->slot[0].detect_pin, 1);
180 }
181 if (gpio_is_valid(data->slot[0].wp_pin))
182 at91_set_gpio_input(data->slot[0].wp_pin, 1);
183
184 /* CLK */
185 at91_set_B_periph(AT91_PIN_PA2, 0);
186
187 /* CMD */
188 at91_set_B_periph(AT91_PIN_PA1, 1);
189
190 /* DAT0, maybe DAT1..DAT3 */
191 at91_set_B_periph(AT91_PIN_PA0, 1);
192 if (data->slot[0].bus_width == 4) {
193 at91_set_B_periph(AT91_PIN_PA4, 1);
194 at91_set_B_periph(AT91_PIN_PA5, 1);
195 at91_set_B_periph(AT91_PIN_PA6, 1);
196 }
197
198 mmc_data = *data;
199 platform_device_register(&at91sam9261_mmc_device);
200 }
201}
202#else
203void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
204#endif
205
206
207/* --------------------------------------------------------------------
208 * NAND / SmartMedia
209 * -------------------------------------------------------------------- */
210
211#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
212static struct atmel_nand_data nand_data;
213
214#define NAND_BASE AT91_CHIPSELECT_3
215
216static struct resource nand_resources[] = {
217 {
218 .start = NAND_BASE,
219 .end = NAND_BASE + SZ_256M - 1,
220 .flags = IORESOURCE_MEM,
221 }
222};
223
224static struct platform_device atmel_nand_device = {
225 .name = "atmel_nand",
226 .id = -1,
227 .dev = {
228 .platform_data = &nand_data,
229 },
230 .resource = nand_resources,
231 .num_resources = ARRAY_SIZE(nand_resources),
232};
233
234void __init at91_add_device_nand(struct atmel_nand_data *data)
235{
236 unsigned long csa;
237
238 if (!data)
239 return;
240
241 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
242 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
243
244 /* enable pin */
245 if (gpio_is_valid(data->enable_pin))
246 at91_set_gpio_output(data->enable_pin, 1);
247
248 /* ready/busy pin */
249 if (gpio_is_valid(data->rdy_pin))
250 at91_set_gpio_input(data->rdy_pin, 1);
251
252 /* card detect pin */
253 if (gpio_is_valid(data->det_pin))
254 at91_set_gpio_input(data->det_pin, 1);
255
256 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
257 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
258
259 nand_data = *data;
260 platform_device_register(&atmel_nand_device);
261}
262
263#else
264void __init at91_add_device_nand(struct atmel_nand_data *data) {}
265#endif
266
267
268/* --------------------------------------------------------------------
269 * TWI (i2c)
270 * -------------------------------------------------------------------- */
271
272/*
273 * Prefer the GPIO code since the TWI controller isn't robust
274 * (gets overruns and underruns under load) and can only issue
275 * repeated STARTs in one scenario (the driver doesn't yet handle them).
276 */
277#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
278
279static struct i2c_gpio_platform_data pdata = {
280 .sda_pin = AT91_PIN_PA7,
281 .sda_is_open_drain = 1,
282 .scl_pin = AT91_PIN_PA8,
283 .scl_is_open_drain = 1,
284 .udelay = 2, /* ~100 kHz */
285};
286
287static struct platform_device at91sam9261_twi_device = {
288 .name = "i2c-gpio",
289 .id = 0,
290 .dev.platform_data = &pdata,
291};
292
293void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
294{
295 at91_set_GPIO_periph(AT91_PIN_PA7, 1); /* TWD (SDA) */
296 at91_set_multi_drive(AT91_PIN_PA7, 1);
297
298 at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */
299 at91_set_multi_drive(AT91_PIN_PA8, 1);
300
301 i2c_register_board_info(0, devices, nr_devices);
302 platform_device_register(&at91sam9261_twi_device);
303}
304
305#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
306
307static struct resource twi_resources[] = {
308 [0] = {
309 .start = AT91SAM9261_BASE_TWI,
310 .end = AT91SAM9261_BASE_TWI + SZ_16K - 1,
311 .flags = IORESOURCE_MEM,
312 },
313 [1] = {
314 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI,
315 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI,
316 .flags = IORESOURCE_IRQ,
317 },
318};
319
320static struct platform_device at91sam9261_twi_device = {
321 .id = 0,
322 .resource = twi_resources,
323 .num_resources = ARRAY_SIZE(twi_resources),
324};
325
326void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
327{
328 /* IP version is not the same on 9261 and g10 */
329 if (cpu_is_at91sam9g10()) {
330 at91sam9261_twi_device.name = "i2c-at91sam9g10";
331 /* I2C PIO must not be configured as open-drain on this chip */
332 } else {
333 at91sam9261_twi_device.name = "i2c-at91sam9261";
334 at91_set_multi_drive(AT91_PIN_PA7, 1);
335 at91_set_multi_drive(AT91_PIN_PA8, 1);
336 }
337
338 /* pins used for TWI interface */
339 at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */
340 at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */
341
342 i2c_register_board_info(0, devices, nr_devices);
343 platform_device_register(&at91sam9261_twi_device);
344}
345#else
346void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
347#endif
348
349
350/* --------------------------------------------------------------------
351 * SPI
352 * -------------------------------------------------------------------- */
353
354#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
355static u64 spi_dmamask = DMA_BIT_MASK(32);
356
357static struct resource spi0_resources[] = {
358 [0] = {
359 .start = AT91SAM9261_BASE_SPI0,
360 .end = AT91SAM9261_BASE_SPI0 + SZ_16K - 1,
361 .flags = IORESOURCE_MEM,
362 },
363 [1] = {
364 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0,
365 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0,
366 .flags = IORESOURCE_IRQ,
367 },
368};
369
370static struct platform_device at91sam9261_spi0_device = {
371 .name = "atmel_spi",
372 .id = 0,
373 .dev = {
374 .dma_mask = &spi_dmamask,
375 .coherent_dma_mask = DMA_BIT_MASK(32),
376 },
377 .resource = spi0_resources,
378 .num_resources = ARRAY_SIZE(spi0_resources),
379};
380
381static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
382
383static struct resource spi1_resources[] = {
384 [0] = {
385 .start = AT91SAM9261_BASE_SPI1,
386 .end = AT91SAM9261_BASE_SPI1 + SZ_16K - 1,
387 .flags = IORESOURCE_MEM,
388 },
389 [1] = {
390 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1,
391 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1,
392 .flags = IORESOURCE_IRQ,
393 },
394};
395
396static struct platform_device at91sam9261_spi1_device = {
397 .name = "atmel_spi",
398 .id = 1,
399 .dev = {
400 .dma_mask = &spi_dmamask,
401 .coherent_dma_mask = DMA_BIT_MASK(32),
402 },
403 .resource = spi1_resources,
404 .num_resources = ARRAY_SIZE(spi1_resources),
405};
406
407static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 };
408
409void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
410{
411 int i;
412 unsigned long cs_pin;
413 short enable_spi0 = 0;
414 short enable_spi1 = 0;
415
416 /* Choose SPI chip-selects */
417 for (i = 0; i < nr_devices; i++) {
418 if (devices[i].controller_data)
419 cs_pin = (unsigned long) devices[i].controller_data;
420 else if (devices[i].bus_num == 0)
421 cs_pin = spi0_standard_cs[devices[i].chip_select];
422 else
423 cs_pin = spi1_standard_cs[devices[i].chip_select];
424
425 if (!gpio_is_valid(cs_pin))
426 continue;
427
428 if (devices[i].bus_num == 0)
429 enable_spi0 = 1;
430 else
431 enable_spi1 = 1;
432
433 /* enable chip-select pin */
434 at91_set_gpio_output(cs_pin, 1);
435
436 /* pass chip-select pin to driver */
437 devices[i].controller_data = (void *) cs_pin;
438 }
439
440 spi_register_board_info(devices, nr_devices);
441
442 /* Configure SPI bus(es) */
443 if (enable_spi0) {
444 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
445 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
446 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
447
448 platform_device_register(&at91sam9261_spi0_device);
449 }
450 if (enable_spi1) {
451 at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */
452 at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */
453 at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */
454
455 platform_device_register(&at91sam9261_spi1_device);
456 }
457}
458#else
459void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
460#endif
461
462
463/* --------------------------------------------------------------------
464 * LCD Controller
465 * -------------------------------------------------------------------- */
466
467#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
468static u64 lcdc_dmamask = DMA_BIT_MASK(32);
469static struct atmel_lcdfb_pdata lcdc_data;
470
471static struct resource lcdc_resources[] = {
472 [0] = {
473 .start = AT91SAM9261_LCDC_BASE,
474 .end = AT91SAM9261_LCDC_BASE + SZ_4K - 1,
475 .flags = IORESOURCE_MEM,
476 },
477 [1] = {
478 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC,
479 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC,
480 .flags = IORESOURCE_IRQ,
481 },
482#if defined(CONFIG_FB_INTSRAM)
483 [2] = {
484 .start = AT91SAM9261_SRAM_BASE,
485 .end = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1,
486 .flags = IORESOURCE_MEM,
487 },
488#endif
489};
490
491static struct platform_device at91_lcdc_device = {
492 .id = 0,
493 .dev = {
494 .dma_mask = &lcdc_dmamask,
495 .coherent_dma_mask = DMA_BIT_MASK(32),
496 .platform_data = &lcdc_data,
497 },
498 .resource = lcdc_resources,
499 .num_resources = ARRAY_SIZE(lcdc_resources),
500};
501
502void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data)
503{
504 if (!data) {
505 return;
506 }
507
508 if (cpu_is_at91sam9g10())
509 at91_lcdc_device.name = "at91sam9g10-lcdfb";
510 else
511 at91_lcdc_device.name = "at91sam9261-lcdfb";
512
513#if defined(CONFIG_FB_ATMEL_STN)
514 at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */
515 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
516 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
517 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
518 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
519 at91_set_A_periph(AT91_PIN_PB5, 0); /* LCDD0 */
520 at91_set_A_periph(AT91_PIN_PB6, 0); /* LCDD1 */
521 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
522 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
523#else
524 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
525 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
526 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
527 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
528 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
529 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
530 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
531 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
532 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
533 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
534 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
535 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
536 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
537 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
538 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
539 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
540 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
541 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
542 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
543 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
544 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
545 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
546#endif
547
548 if (ARRAY_SIZE(lcdc_resources) > 2) {
549 void __iomem *fb;
550 struct resource *fb_res = &lcdc_resources[2];
551 size_t fb_len = resource_size(fb_res);
552
553 fb = ioremap(fb_res->start, fb_len);
554 if (fb) {
555 memset(fb, 0, fb_len);
556 iounmap(fb);
557 }
558 }
559 lcdc_data = *data;
560 platform_device_register(&at91_lcdc_device);
561}
562#else
563void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data) {}
564#endif
565
566
567/* --------------------------------------------------------------------
568 * Timer/Counter block
569 * -------------------------------------------------------------------- */
570
571#ifdef CONFIG_ATMEL_TCLIB
572
573static struct resource tcb_resources[] = {
574 [0] = {
575 .start = AT91SAM9261_BASE_TCB0,
576 .end = AT91SAM9261_BASE_TCB0 + SZ_16K - 1,
577 .flags = IORESOURCE_MEM,
578 },
579 [1] = {
580 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0,
581 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0,
582 .flags = IORESOURCE_IRQ,
583 },
584 [2] = {
585 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1,
586 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1,
587 .flags = IORESOURCE_IRQ,
588 },
589 [3] = {
590 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2,
591 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2,
592 .flags = IORESOURCE_IRQ,
593 },
594};
595
596static struct platform_device at91sam9261_tcb_device = {
597 .name = "atmel_tcb",
598 .id = 0,
599 .resource = tcb_resources,
600 .num_resources = ARRAY_SIZE(tcb_resources),
601};
602
603static void __init at91_add_device_tc(void)
604{
605 platform_device_register(&at91sam9261_tcb_device);
606}
607#else
608static void __init at91_add_device_tc(void) { }
609#endif
610
611
612/* --------------------------------------------------------------------
613 * RTT
614 * -------------------------------------------------------------------- */
615
616static struct resource rtt_resources[] = {
617 {
618 .start = AT91SAM9261_BASE_RTT,
619 .end = AT91SAM9261_BASE_RTT + SZ_16 - 1,
620 .flags = IORESOURCE_MEM,
621 }, {
622 .flags = IORESOURCE_MEM,
623 }, {
624 .flags = IORESOURCE_IRQ,
625 }
626};
627
628static struct platform_device at91sam9261_rtt_device = {
629 .name = "at91_rtt",
630 .id = 0,
631 .resource = rtt_resources,
632};
633
634#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
635static void __init at91_add_device_rtt_rtc(void)
636{
637 at91sam9261_rtt_device.name = "rtc-at91sam9";
638 /*
639 * The second resource is needed:
640 * GPBR will serve as the storage for RTC time offset
641 */
642 at91sam9261_rtt_device.num_resources = 3;
643 rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
644 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
645 rtt_resources[1].end = rtt_resources[1].start + 3;
646 rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
647 rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
648}
649#else
650static void __init at91_add_device_rtt_rtc(void)
651{
652 /* Only one resource is needed: RTT not used as RTC */
653 at91sam9261_rtt_device.num_resources = 1;
654}
655#endif
656
657static void __init at91_add_device_rtt(void)
658{
659 at91_add_device_rtt_rtc();
660 platform_device_register(&at91sam9261_rtt_device);
661}
662
663
664/* --------------------------------------------------------------------
665 * Watchdog
666 * -------------------------------------------------------------------- */
667
668#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
669static struct resource wdt_resources[] = {
670 {
671 .start = AT91SAM9261_BASE_WDT,
672 .end = AT91SAM9261_BASE_WDT + SZ_16 - 1,
673 .flags = IORESOURCE_MEM,
674 }
675};
676
677static struct platform_device at91sam9261_wdt_device = {
678 .name = "at91_wdt",
679 .id = -1,
680 .resource = wdt_resources,
681 .num_resources = ARRAY_SIZE(wdt_resources),
682};
683
684static void __init at91_add_device_watchdog(void)
685{
686 platform_device_register(&at91sam9261_wdt_device);
687}
688#else
689static void __init at91_add_device_watchdog(void) {}
690#endif
691
692
693/* --------------------------------------------------------------------
694 * SSC -- Synchronous Serial Controller
695 * -------------------------------------------------------------------- */
696
697#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
698static u64 ssc0_dmamask = DMA_BIT_MASK(32);
699
700static struct resource ssc0_resources[] = {
701 [0] = {
702 .start = AT91SAM9261_BASE_SSC0,
703 .end = AT91SAM9261_BASE_SSC0 + SZ_16K - 1,
704 .flags = IORESOURCE_MEM,
705 },
706 [1] = {
707 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0,
708 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0,
709 .flags = IORESOURCE_IRQ,
710 },
711};
712
713static struct platform_device at91sam9261_ssc0_device = {
714 .name = "at91rm9200_ssc",
715 .id = 0,
716 .dev = {
717 .dma_mask = &ssc0_dmamask,
718 .coherent_dma_mask = DMA_BIT_MASK(32),
719 },
720 .resource = ssc0_resources,
721 .num_resources = ARRAY_SIZE(ssc0_resources),
722};
723
724static inline void configure_ssc0_pins(unsigned pins)
725{
726 if (pins & ATMEL_SSC_TF)
727 at91_set_A_periph(AT91_PIN_PB21, 1);
728 if (pins & ATMEL_SSC_TK)
729 at91_set_A_periph(AT91_PIN_PB22, 1);
730 if (pins & ATMEL_SSC_TD)
731 at91_set_A_periph(AT91_PIN_PB23, 1);
732 if (pins & ATMEL_SSC_RD)
733 at91_set_A_periph(AT91_PIN_PB24, 1);
734 if (pins & ATMEL_SSC_RK)
735 at91_set_A_periph(AT91_PIN_PB25, 1);
736 if (pins & ATMEL_SSC_RF)
737 at91_set_A_periph(AT91_PIN_PB26, 1);
738}
739
740static u64 ssc1_dmamask = DMA_BIT_MASK(32);
741
742static struct resource ssc1_resources[] = {
743 [0] = {
744 .start = AT91SAM9261_BASE_SSC1,
745 .end = AT91SAM9261_BASE_SSC1 + SZ_16K - 1,
746 .flags = IORESOURCE_MEM,
747 },
748 [1] = {
749 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1,
750 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1,
751 .flags = IORESOURCE_IRQ,
752 },
753};
754
755static struct platform_device at91sam9261_ssc1_device = {
756 .name = "at91rm9200_ssc",
757 .id = 1,
758 .dev = {
759 .dma_mask = &ssc1_dmamask,
760 .coherent_dma_mask = DMA_BIT_MASK(32),
761 },
762 .resource = ssc1_resources,
763 .num_resources = ARRAY_SIZE(ssc1_resources),
764};
765
766static inline void configure_ssc1_pins(unsigned pins)
767{
768 if (pins & ATMEL_SSC_TF)
769 at91_set_B_periph(AT91_PIN_PA17, 1);
770 if (pins & ATMEL_SSC_TK)
771 at91_set_B_periph(AT91_PIN_PA18, 1);
772 if (pins & ATMEL_SSC_TD)
773 at91_set_B_periph(AT91_PIN_PA19, 1);
774 if (pins & ATMEL_SSC_RD)
775 at91_set_B_periph(AT91_PIN_PA20, 1);
776 if (pins & ATMEL_SSC_RK)
777 at91_set_B_periph(AT91_PIN_PA21, 1);
778 if (pins & ATMEL_SSC_RF)
779 at91_set_B_periph(AT91_PIN_PA22, 1);
780}
781
782static u64 ssc2_dmamask = DMA_BIT_MASK(32);
783
784static struct resource ssc2_resources[] = {
785 [0] = {
786 .start = AT91SAM9261_BASE_SSC2,
787 .end = AT91SAM9261_BASE_SSC2 + SZ_16K - 1,
788 .flags = IORESOURCE_MEM,
789 },
790 [1] = {
791 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2,
792 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2,
793 .flags = IORESOURCE_IRQ,
794 },
795};
796
797static struct platform_device at91sam9261_ssc2_device = {
798 .name = "at91rm9200_ssc",
799 .id = 2,
800 .dev = {
801 .dma_mask = &ssc2_dmamask,
802 .coherent_dma_mask = DMA_BIT_MASK(32),
803 },
804 .resource = ssc2_resources,
805 .num_resources = ARRAY_SIZE(ssc2_resources),
806};
807
808static inline void configure_ssc2_pins(unsigned pins)
809{
810 if (pins & ATMEL_SSC_TF)
811 at91_set_B_periph(AT91_PIN_PC25, 1);
812 if (pins & ATMEL_SSC_TK)
813 at91_set_B_periph(AT91_PIN_PC26, 1);
814 if (pins & ATMEL_SSC_TD)
815 at91_set_B_periph(AT91_PIN_PC27, 1);
816 if (pins & ATMEL_SSC_RD)
817 at91_set_B_periph(AT91_PIN_PC28, 1);
818 if (pins & ATMEL_SSC_RK)
819 at91_set_B_periph(AT91_PIN_PC29, 1);
820 if (pins & ATMEL_SSC_RF)
821 at91_set_B_periph(AT91_PIN_PC30, 1);
822}
823
824/*
825 * SSC controllers are accessed through library code, instead of any
826 * kind of all-singing/all-dancing driver. For example one could be
827 * used by a particular I2S audio codec's driver, while another one
828 * on the same system might be used by a custom data capture driver.
829 */
830void __init at91_add_device_ssc(unsigned id, unsigned pins)
831{
832 struct platform_device *pdev;
833
834 /*
835 * NOTE: caller is responsible for passing information matching
836 * "pins" to whatever will be using each particular controller.
837 */
838 switch (id) {
839 case AT91SAM9261_ID_SSC0:
840 pdev = &at91sam9261_ssc0_device;
841 configure_ssc0_pins(pins);
842 break;
843 case AT91SAM9261_ID_SSC1:
844 pdev = &at91sam9261_ssc1_device;
845 configure_ssc1_pins(pins);
846 break;
847 case AT91SAM9261_ID_SSC2:
848 pdev = &at91sam9261_ssc2_device;
849 configure_ssc2_pins(pins);
850 break;
851 default:
852 return;
853 }
854
855 platform_device_register(pdev);
856}
857
858#else
859void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
860#endif
861
862
863/* --------------------------------------------------------------------
864 * UART
865 * -------------------------------------------------------------------- */
866
867#if defined(CONFIG_SERIAL_ATMEL)
868static struct resource dbgu_resources[] = {
869 [0] = {
870 .start = AT91SAM9261_BASE_DBGU,
871 .end = AT91SAM9261_BASE_DBGU + SZ_512 - 1,
872 .flags = IORESOURCE_MEM,
873 },
874 [1] = {
875 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
876 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
877 .flags = IORESOURCE_IRQ,
878 },
879};
880
881static struct atmel_uart_data dbgu_data = {
882 .use_dma_tx = 0,
883 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
884};
885
886static u64 dbgu_dmamask = DMA_BIT_MASK(32);
887
888static struct platform_device at91sam9261_dbgu_device = {
889 .name = "atmel_usart",
890 .id = 0,
891 .dev = {
892 .dma_mask = &dbgu_dmamask,
893 .coherent_dma_mask = DMA_BIT_MASK(32),
894 .platform_data = &dbgu_data,
895 },
896 .resource = dbgu_resources,
897 .num_resources = ARRAY_SIZE(dbgu_resources),
898};
899
900static inline void configure_dbgu_pins(void)
901{
902 at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
903 at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
904}
905
906static struct resource uart0_resources[] = {
907 [0] = {
908 .start = AT91SAM9261_BASE_US0,
909 .end = AT91SAM9261_BASE_US0 + SZ_16K - 1,
910 .flags = IORESOURCE_MEM,
911 },
912 [1] = {
913 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US0,
914 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US0,
915 .flags = IORESOURCE_IRQ,
916 },
917};
918
919static struct atmel_uart_data uart0_data = {
920 .use_dma_tx = 1,
921 .use_dma_rx = 1,
922};
923
924static u64 uart0_dmamask = DMA_BIT_MASK(32);
925
926static struct platform_device at91sam9261_uart0_device = {
927 .name = "atmel_usart",
928 .id = 1,
929 .dev = {
930 .dma_mask = &uart0_dmamask,
931 .coherent_dma_mask = DMA_BIT_MASK(32),
932 .platform_data = &uart0_data,
933 },
934 .resource = uart0_resources,
935 .num_resources = ARRAY_SIZE(uart0_resources),
936};
937
938static inline void configure_usart0_pins(unsigned pins)
939{
940 at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
941 at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
942
943 if (pins & ATMEL_UART_RTS)
944 at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */
945 if (pins & ATMEL_UART_CTS)
946 at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */
947}
948
949static struct resource uart1_resources[] = {
950 [0] = {
951 .start = AT91SAM9261_BASE_US1,
952 .end = AT91SAM9261_BASE_US1 + SZ_16K - 1,
953 .flags = IORESOURCE_MEM,
954 },
955 [1] = {
956 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
957 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
958 .flags = IORESOURCE_IRQ,
959 },
960};
961
962static struct atmel_uart_data uart1_data = {
963 .use_dma_tx = 1,
964 .use_dma_rx = 1,
965};
966
967static u64 uart1_dmamask = DMA_BIT_MASK(32);
968
969static struct platform_device at91sam9261_uart1_device = {
970 .name = "atmel_usart",
971 .id = 2,
972 .dev = {
973 .dma_mask = &uart1_dmamask,
974 .coherent_dma_mask = DMA_BIT_MASK(32),
975 .platform_data = &uart1_data,
976 },
977 .resource = uart1_resources,
978 .num_resources = ARRAY_SIZE(uart1_resources),
979};
980
981static inline void configure_usart1_pins(unsigned pins)
982{
983 at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
984 at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
985
986 if (pins & ATMEL_UART_RTS)
987 at91_set_B_periph(AT91_PIN_PA12, 0); /* RTS1 */
988 if (pins & ATMEL_UART_CTS)
989 at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */
990}
991
992static struct resource uart2_resources[] = {
993 [0] = {
994 .start = AT91SAM9261_BASE_US2,
995 .end = AT91SAM9261_BASE_US2 + SZ_16K - 1,
996 .flags = IORESOURCE_MEM,
997 },
998 [1] = {
999 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
1000 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
1001 .flags = IORESOURCE_IRQ,
1002 },
1003};
1004
1005static struct atmel_uart_data uart2_data = {
1006 .use_dma_tx = 1,
1007 .use_dma_rx = 1,
1008};
1009
1010static u64 uart2_dmamask = DMA_BIT_MASK(32);
1011
1012static struct platform_device at91sam9261_uart2_device = {
1013 .name = "atmel_usart",
1014 .id = 3,
1015 .dev = {
1016 .dma_mask = &uart2_dmamask,
1017 .coherent_dma_mask = DMA_BIT_MASK(32),
1018 .platform_data = &uart2_data,
1019 },
1020 .resource = uart2_resources,
1021 .num_resources = ARRAY_SIZE(uart2_resources),
1022};
1023
1024static inline void configure_usart2_pins(unsigned pins)
1025{
1026 at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
1027 at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
1028
1029 if (pins & ATMEL_UART_RTS)
1030 at91_set_B_periph(AT91_PIN_PA15, 0); /* RTS2*/
1031 if (pins & ATMEL_UART_CTS)
1032 at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */
1033}
1034
1035static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1036
1037void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1038{
1039 struct platform_device *pdev;
1040 struct atmel_uart_data *pdata;
1041
1042 switch (id) {
1043 case 0: /* DBGU */
1044 pdev = &at91sam9261_dbgu_device;
1045 configure_dbgu_pins();
1046 break;
1047 case AT91SAM9261_ID_US0:
1048 pdev = &at91sam9261_uart0_device;
1049 configure_usart0_pins(pins);
1050 break;
1051 case AT91SAM9261_ID_US1:
1052 pdev = &at91sam9261_uart1_device;
1053 configure_usart1_pins(pins);
1054 break;
1055 case AT91SAM9261_ID_US2:
1056 pdev = &at91sam9261_uart2_device;
1057 configure_usart2_pins(pins);
1058 break;
1059 default:
1060 return;
1061 }
1062 pdata = pdev->dev.platform_data;
1063 pdata->num = portnr; /* update to mapped ID */
1064
1065 if (portnr < ATMEL_MAX_UART)
1066 at91_uarts[portnr] = pdev;
1067}
1068
1069void __init at91_add_device_serial(void)
1070{
1071 int i;
1072
1073 for (i = 0; i < ATMEL_MAX_UART; i++) {
1074 if (at91_uarts[i])
1075 platform_device_register(at91_uarts[i]);
1076 }
1077}
1078#else
1079void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1080void __init at91_add_device_serial(void) {}
1081#endif
1082
1083
1084/* -------------------------------------------------------------------- */
1085
1086/*
1087 * These devices are always present and don't need any board-specific
1088 * setup.
1089 */
1090static int __init at91_add_standard_devices(void)
1091{
1092 at91_add_device_rtt();
1093 at91_add_device_watchdog();
1094 at91_add_device_tc();
1095 return 0;
1096}
1097
1098arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
deleted file mode 100644
index e85ada820bfb..000000000000
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ /dev/null
@@ -1,623 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/board-sam9261ek.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2006 Atmel
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29#include <linux/spi/ads7846.h>
30#include <linux/spi/at73c213.h>
31#include <linux/clk.h>
32#include <linux/dm9000.h>
33#include <linux/fb.h>
34#include <linux/gpio_keys.h>
35#include <linux/input.h>
36
37#include <video/atmel_lcdc.h>
38
39#include <asm/setup.h>
40#include <asm/mach-types.h>
41#include <asm/irq.h>
42
43#include <asm/mach/arch.h>
44#include <asm/mach/map.h>
45#include <asm/mach/irq.h>
46
47#include <mach/hardware.h>
48#include <mach/at91sam9_smc.h>
49#include <mach/system_rev.h>
50
51#include "at91_aic.h"
52#include "board.h"
53#include "sam9_smc.h"
54#include "generic.h"
55#include "gpio.h"
56
57
58static void __init ek_init_early(void)
59{
60 /* Initialize processor: 18.432 MHz crystal */
61 at91_initialize(18432000);
62}
63
64/*
65 * DM9000 ethernet device
66 */
67#if defined(CONFIG_DM9000)
68static struct resource dm9000_resource[] = {
69 [0] = {
70 .start = AT91_CHIPSELECT_2,
71 .end = AT91_CHIPSELECT_2 + 3,
72 .flags = IORESOURCE_MEM
73 },
74 [1] = {
75 .start = AT91_CHIPSELECT_2 + 0x44,
76 .end = AT91_CHIPSELECT_2 + 0xFF,
77 .flags = IORESOURCE_MEM
78 },
79 [2] = {
80 .flags = IORESOURCE_IRQ
81 | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE,
82 }
83};
84
85static struct dm9000_plat_data dm9000_platdata = {
86 .flags = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM,
87};
88
89static struct platform_device dm9000_device = {
90 .name = "dm9000",
91 .id = 0,
92 .num_resources = ARRAY_SIZE(dm9000_resource),
93 .resource = dm9000_resource,
94 .dev = {
95 .platform_data = &dm9000_platdata,
96 }
97};
98
99/*
100 * SMC timings for the DM9000.
101 * Note: These timings were calculated for MASTER_CLOCK = 100000000 according to the DM9000 timings.
102 */
103static struct sam9_smc_config __initdata dm9000_smc_config = {
104 .ncs_read_setup = 0,
105 .nrd_setup = 2,
106 .ncs_write_setup = 0,
107 .nwe_setup = 2,
108
109 .ncs_read_pulse = 8,
110 .nrd_pulse = 4,
111 .ncs_write_pulse = 8,
112 .nwe_pulse = 4,
113
114 .read_cycle = 16,
115 .write_cycle = 16,
116
117 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16,
118 .tdf_cycles = 1,
119};
120
121static void __init ek_add_device_dm9000(void)
122{
123 struct resource *r = &dm9000_resource[2];
124
125 /* Configure chip-select 2 (DM9000) */
126 sam9_smc_configure(0, 2, &dm9000_smc_config);
127
128 /* Configure Reset signal as output */
129 at91_set_gpio_output(AT91_PIN_PC10, 0);
130
131 /* Configure Interrupt pin as input, no pull-up */
132 at91_set_gpio_input(AT91_PIN_PC11, 0);
133
134 r->start = r->end = gpio_to_irq(AT91_PIN_PC11);
135 platform_device_register(&dm9000_device);
136}
137#else
138static void __init ek_add_device_dm9000(void) {}
139#endif /* CONFIG_DM9000 */
140
141
142/*
143 * USB Host Port
144 */
145static struct at91_usbh_data __initdata ek_usbh_data = {
146 .ports = 2,
147 .vbus_pin = {-EINVAL, -EINVAL},
148 .overcurrent_pin= {-EINVAL, -EINVAL},
149};
150
151
152/*
153 * USB Device Port
154 */
155static struct at91_udc_data __initdata ek_udc_data = {
156 .vbus_pin = AT91_PIN_PB29,
157 .pullup_pin = -EINVAL, /* pull-up driven by UDC */
158};
159
160
161/*
162 * NAND flash
163 */
164static struct mtd_partition __initdata ek_nand_partition[] = {
165 {
166 .name = "Partition 1",
167 .offset = 0,
168 .size = SZ_256K,
169 },
170 {
171 .name = "Partition 2",
172 .offset = MTDPART_OFS_NXTBLK,
173 .size = MTDPART_SIZ_FULL,
174 },
175};
176
177static struct atmel_nand_data __initdata ek_nand_data = {
178 .ale = 22,
179 .cle = 21,
180 .det_pin = -EINVAL,
181 .rdy_pin = AT91_PIN_PC15,
182 .enable_pin = AT91_PIN_PC14,
183 .ecc_mode = NAND_ECC_SOFT,
184 .on_flash_bbt = 1,
185 .parts = ek_nand_partition,
186 .num_parts = ARRAY_SIZE(ek_nand_partition),
187};
188
189static struct sam9_smc_config __initdata ek_nand_smc_config = {
190 .ncs_read_setup = 0,
191 .nrd_setup = 1,
192 .ncs_write_setup = 0,
193 .nwe_setup = 1,
194
195 .ncs_read_pulse = 3,
196 .nrd_pulse = 3,
197 .ncs_write_pulse = 3,
198 .nwe_pulse = 3,
199
200 .read_cycle = 5,
201 .write_cycle = 5,
202
203 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
204 .tdf_cycles = 2,
205};
206
207static void __init ek_add_device_nand(void)
208{
209 ek_nand_data.bus_width_16 = board_have_nand_16bit();
210 /* setup bus-width (8 or 16) */
211 if (ek_nand_data.bus_width_16)
212 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
213 else
214 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
215
216 /* configure chip-select 3 (NAND) */
217 sam9_smc_configure(0, 3, &ek_nand_smc_config);
218
219 at91_add_device_nand(&ek_nand_data);
220}
221
222/*
223 * SPI related devices
224 */
225#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
226
227/*
228 * ADS7846 Touchscreen
229 */
230#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
231
232static int ads7843_pendown_state(void)
233{
234 return !at91_get_gpio_value(AT91_PIN_PC2); /* Touchscreen PENIRQ */
235}
236
237static struct ads7846_platform_data ads_info = {
238 .model = 7843,
239 .x_min = 150,
240 .x_max = 3830,
241 .y_min = 190,
242 .y_max = 3830,
243 .vref_delay_usecs = 100,
244 .x_plate_ohms = 450,
245 .y_plate_ohms = 250,
246 .pressure_max = 15000,
247 .debounce_max = 1,
248 .debounce_rep = 0,
249 .debounce_tol = (~0),
250 .get_pendown_state = ads7843_pendown_state,
251};
252
253static void __init ek_add_device_ts(void)
254{
255 at91_set_B_periph(AT91_PIN_PC2, 1); /* External IRQ0, with pullup */
256 at91_set_gpio_input(AT91_PIN_PA11, 1); /* Touchscreen BUSY signal */
257}
258#else
259static void __init ek_add_device_ts(void) {}
260#endif
261
262/*
263 * Audio
264 */
265static struct at73c213_board_info at73c213_data = {
266 .ssc_id = 1,
267 .shortname = "AT91SAM9261/9G10-EK external DAC",
268};
269
270#if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
271static void __init at73c213_set_clk(struct at73c213_board_info *info)
272{
273 struct clk *pck2;
274 struct clk *plla;
275
276 pck2 = clk_get(NULL, "pck2");
277 plla = clk_get(NULL, "plla");
278
279 /* AT73C213 MCK Clock */
280 at91_set_B_periph(AT91_PIN_PB31, 0); /* PCK2 */
281
282 clk_set_parent(pck2, plla);
283 clk_put(plla);
284
285 info->dac_clk = pck2;
286}
287#else
288static void __init at73c213_set_clk(struct at73c213_board_info *info) {}
289#endif
290
291/*
292 * SPI devices
293 */
294static struct spi_board_info ek_spi_devices[] = {
295 { /* DataFlash chip */
296 .modalias = "mtd_dataflash",
297 .chip_select = 0,
298 .max_speed_hz = 15 * 1000 * 1000,
299 .bus_num = 0,
300 },
301#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
302 {
303 .modalias = "ads7846",
304 .chip_select = 2,
305 .max_speed_hz = 125000 * 26, /* (max sample rate @ 3V) * (cmd + data + overhead) */
306 .bus_num = 0,
307 .platform_data = &ads_info,
308 .irq = NR_IRQS_LEGACY + AT91SAM9261_ID_IRQ0,
309 .controller_data = (void *) AT91_PIN_PA28, /* CS pin */
310 },
311#endif
312#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
313 { /* DataFlash card - jumper (J12) configurable to CS3 or CS0 */
314 .modalias = "mtd_dataflash",
315 .chip_select = 3,
316 .max_speed_hz = 15 * 1000 * 1000,
317 .bus_num = 0,
318 },
319#elif defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
320 { /* AT73C213 DAC */
321 .modalias = "at73c213",
322 .chip_select = 3,
323 .max_speed_hz = 10 * 1000 * 1000,
324 .bus_num = 0,
325 .mode = SPI_MODE_1,
326 .platform_data = &at73c213_data,
327 .controller_data = (void*) AT91_PIN_PA29, /* default for CS3 is PA6, but it must be PA29 */
328 },
329#endif
330};
331
332#else /* CONFIG_SPI_ATMEL_* */
333/* spi0 and mmc/sd share the same PIO pins: cannot be used at the same time */
334
335/*
336 * MCI (SD/MMC)
337 * det_pin, wp_pin and vcc_pin are not connected
338 */
339static struct mci_platform_data __initdata mci0_data = {
340 .slot[0] = {
341 .bus_width = 4,
342 .detect_pin = -EINVAL,
343 .wp_pin = -EINVAL,
344 },
345};
346
347#endif /* CONFIG_SPI_ATMEL_* */
348
349
350/*
351 * LCD Controller
352 */
353#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
354
355#if defined(CONFIG_FB_ATMEL_STN)
356
357/* STN */
358static struct fb_videomode at91_stn_modes[] = {
359 {
360 .name = "SP06Q002 @ 75",
361 .refresh = 75,
362 .xres = 320, .yres = 240,
363 .pixclock = KHZ2PICOS(1440),
364
365 .left_margin = 1, .right_margin = 1,
366 .upper_margin = 0, .lower_margin = 0,
367 .hsync_len = 1, .vsync_len = 1,
368
369 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
370 .vmode = FB_VMODE_NONINTERLACED,
371 },
372};
373
374static struct fb_monspecs at91fb_default_stn_monspecs = {
375 .manufacturer = "HIT",
376 .monitor = "SP06Q002",
377
378 .modedb = at91_stn_modes,
379 .modedb_len = ARRAY_SIZE(at91_stn_modes),
380 .hfmin = 15000,
381 .hfmax = 64000,
382 .vfmin = 50,
383 .vfmax = 150,
384};
385
386#define AT91SAM9261_DEFAULT_STN_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
387 | ATMEL_LCDC_DISTYPE_STNMONO \
388 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE \
389 | ATMEL_LCDC_IFWIDTH_4 \
390 | ATMEL_LCDC_SCANMOD_SINGLE)
391
392static void at91_lcdc_stn_power_control(struct atmel_lcdfb_pdata *pdata, int on)
393{
394 /* backlight */
395 if (on) { /* power up */
396 at91_set_gpio_value(AT91_PIN_PC14, 0);
397 at91_set_gpio_value(AT91_PIN_PC15, 0);
398 } else { /* power down */
399 at91_set_gpio_value(AT91_PIN_PC14, 1);
400 at91_set_gpio_value(AT91_PIN_PC15, 1);
401 }
402}
403
404static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
405 .default_bpp = 1,
406 .default_dmacon = ATMEL_LCDC_DMAEN,
407 .default_lcdcon2 = AT91SAM9261_DEFAULT_STN_LCDCON2,
408 .default_monspecs = &at91fb_default_stn_monspecs,
409 .atmel_lcdfb_power_control = at91_lcdc_stn_power_control,
410 .guard_time = 1,
411};
412
413#else
414
415/* TFT */
416static struct fb_videomode at91_tft_vga_modes[] = {
417 {
418 .name = "TX09D50VM1CCA @ 60",
419 .refresh = 60,
420 .xres = 240, .yres = 320,
421 .pixclock = KHZ2PICOS(4965),
422
423 .left_margin = 1, .right_margin = 33,
424 .upper_margin = 1, .lower_margin = 0,
425 .hsync_len = 5, .vsync_len = 1,
426
427 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
428 .vmode = FB_VMODE_NONINTERLACED,
429 },
430};
431
432static struct fb_monspecs at91fb_default_tft_monspecs = {
433 .manufacturer = "HIT",
434 .monitor = "TX09D50VM1CCA",
435
436 .modedb = at91_tft_vga_modes,
437 .modedb_len = ARRAY_SIZE(at91_tft_vga_modes),
438 .hfmin = 15000,
439 .hfmax = 64000,
440 .vfmin = 50,
441 .vfmax = 150,
442};
443
444#define AT91SAM9261_DEFAULT_TFT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
445 | ATMEL_LCDC_DISTYPE_TFT \
446 | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
447
448static void at91_lcdc_tft_power_control(struct atmel_lcdfb_pdata *pdata, int on)
449{
450 if (on)
451 at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
452 else
453 at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
454}
455
456static struct atmel_lcdfb_pdata __initdata ek_lcdc_data = {
457 .lcdcon_is_backlight = true,
458 .default_bpp = 16,
459 .default_dmacon = ATMEL_LCDC_DMAEN,
460 .default_lcdcon2 = AT91SAM9261_DEFAULT_TFT_LCDCON2,
461 .default_monspecs = &at91fb_default_tft_monspecs,
462 .atmel_lcdfb_power_control = at91_lcdc_tft_power_control,
463 .guard_time = 1,
464};
465#endif
466
467#else
468static struct atmel_lcdfb_pdata __initdata ek_lcdc_data;
469#endif
470
471
472/*
473 * GPIO Buttons
474 */
475#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
476static struct gpio_keys_button ek_buttons[] = {
477 {
478 .gpio = AT91_PIN_PA27,
479 .code = BTN_0,
480 .desc = "Button 0",
481 .active_low = 1,
482 .wakeup = 1,
483 },
484 {
485 .gpio = AT91_PIN_PA26,
486 .code = BTN_1,
487 .desc = "Button 1",
488 .active_low = 1,
489 .wakeup = 1,
490 },
491 {
492 .gpio = AT91_PIN_PA25,
493 .code = BTN_2,
494 .desc = "Button 2",
495 .active_low = 1,
496 .wakeup = 1,
497 },
498 {
499 .gpio = AT91_PIN_PA24,
500 .code = BTN_3,
501 .desc = "Button 3",
502 .active_low = 1,
503 .wakeup = 1,
504 }
505};
506
507static struct gpio_keys_platform_data ek_button_data = {
508 .buttons = ek_buttons,
509 .nbuttons = ARRAY_SIZE(ek_buttons),
510};
511
512static struct platform_device ek_button_device = {
513 .name = "gpio-keys",
514 .id = -1,
515 .num_resources = 0,
516 .dev = {
517 .platform_data = &ek_button_data,
518 }
519};
520
521static void __init ek_add_device_buttons(void)
522{
523 at91_set_gpio_input(AT91_PIN_PA27, 1); /* btn0 */
524 at91_set_deglitch(AT91_PIN_PA27, 1);
525 at91_set_gpio_input(AT91_PIN_PA26, 1); /* btn1 */
526 at91_set_deglitch(AT91_PIN_PA26, 1);
527 at91_set_gpio_input(AT91_PIN_PA25, 1); /* btn2 */
528 at91_set_deglitch(AT91_PIN_PA25, 1);
529 at91_set_gpio_input(AT91_PIN_PA24, 1); /* btn3 */
530 at91_set_deglitch(AT91_PIN_PA24, 1);
531
532 platform_device_register(&ek_button_device);
533}
534#else
535static void __init ek_add_device_buttons(void) {}
536#endif
537
538/*
539 * LEDs
540 */
541static struct gpio_led ek_leds[] = {
542 { /* "bottom" led, green, userled1 to be defined */
543 .name = "ds7",
544 .gpio = AT91_PIN_PA14,
545 .active_low = 1,
546 .default_trigger = "none",
547 },
548 { /* "top" led, green, userled2 to be defined */
549 .name = "ds8",
550 .gpio = AT91_PIN_PA13,
551 .active_low = 1,
552 .default_trigger = "none",
553 },
554 { /* "power" led, yellow */
555 .name = "ds1",
556 .gpio = AT91_PIN_PA23,
557 .default_trigger = "heartbeat",
558 }
559};
560
561static void __init ek_board_init(void)
562{
563 at91_register_devices();
564
565 /* Serial */
566 /* DBGU on ttyS0. (Rx & Tx only) */
567 at91_register_uart(0, 0, 0);
568 at91_add_device_serial();
569
570 if (cpu_is_at91sam9g10())
571 ek_lcdc_data.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB;
572
573 /* USB Host */
574 at91_add_device_usbh(&ek_usbh_data);
575 /* USB Device */
576 at91_add_device_udc(&ek_udc_data);
577 /* I2C */
578 at91_add_device_i2c(NULL, 0);
579 /* NAND */
580 ek_add_device_nand();
581 /* DM9000 ethernet */
582 ek_add_device_dm9000();
583
584 /* spi0 and mmc/sd share the same PIO pins */
585#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
586 /* SPI */
587 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
588 /* Touchscreen */
589 ek_add_device_ts();
590 /* SSC (to AT73C213) */
591 at73c213_set_clk(&at73c213_data);
592 at91_add_device_ssc(AT91SAM9261_ID_SSC1, ATMEL_SSC_TX);
593#else
594 /* MMC */
595 at91_add_device_mci(0, &mci0_data);
596#endif
597 /* LCD Controller */
598 at91_add_device_lcdc(&ek_lcdc_data);
599 /* Push Buttons */
600 ek_add_device_buttons();
601 /* LEDs */
602 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
603}
604
605MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
606 /* Maintainer: Atmel */
607 .init_time = at91_init_time,
608 .map_io = at91_map_io,
609 .handle_irq = at91_aic_handle_irq,
610 .init_early = ek_init_early,
611 .init_irq = at91_init_irq_default,
612 .init_machine = ek_board_init,
613MACHINE_END
614
615MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
616 /* Maintainer: Atmel */
617 .init_time = at91_init_time,
618 .map_io = at91_map_io,
619 .handle_irq = at91_aic_handle_irq,
620 .init_early = ek_init_early,
621 .init_irq = at91_init_irq_default,
622 .init_machine = ek_board_init,
623MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 07:39:26 -0500