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authorNicolas Ferre <nicolas.ferre@atmel.com>2014-11-27 10:10:06 -0500
committerNicolas Ferre <nicolas.ferre@atmel.com>2014-11-27 10:18:00 -0500
commit1ccdde057b03a2446eeee7b7a63306c4d9c68d61 (patch)
treec437ea0fc1cfc5117f2400cb5bfa834561e70a85 /arch/arm/mach-at91
parentff78a189b0ae55f258f020a428c834250eb8f834 (diff)
ARM: at91: remove legacy IRQ driver and related code
Remove irc.c and associated header file. The related code was idendified by the CONFIG_OLD_IRQ_AT91 option that was removed previously. It has been spotted by following coccinelle semantic match: @rule1@ expression E; statement S; @@ ( - if (IS_ENABLED(CONFIG_OLD_IRQ_AT91)) S | - if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && E) S ) Cc: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/Makefile1
-rw-r--r--arch/arm/mach-at91/at91_aic.h99
-rw-r--r--arch/arm/mach-at91/board-dt-rm9200.c1
-rw-r--r--arch/arm/mach-at91/board-dt-sam9.c1
-rw-r--r--arch/arm/mach-at91/board-dt-sama5.c1
-rw-r--r--arch/arm/mach-at91/generic.h2
-rw-r--r--arch/arm/mach-at91/irq.c296
-rw-r--r--arch/arm/mach-at91/pm.c22
-rw-r--r--arch/arm/mach-at91/setup.c4
9 files changed, 0 insertions, 427 deletions
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index b486c7760ac4..2371b8845bf5 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -4,7 +4,6 @@
4 4
5obj-y := gpio.o setup.o sysirq_mask.o 5obj-y := gpio.o setup.o sysirq_mask.o
6 6
7obj-$(CONFIG_OLD_IRQ_AT91) += irq.o
8obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o 7obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
9 8
10# CPU-specific support 9# CPU-specific support
diff --git a/arch/arm/mach-at91/at91_aic.h b/arch/arm/mach-at91/at91_aic.h
deleted file mode 100644
index eaea66197fa1..000000000000
--- a/arch/arm/mach-at91/at91_aic.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_aic.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Advanced Interrupt Controller (AIC) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_AIC_H
17#define AT91_AIC_H
18
19#ifndef __ASSEMBLY__
20extern void __iomem *at91_aic_base;
21
22#define at91_aic_read(field) \
23 __raw_readl(at91_aic_base + field)
24
25#define at91_aic_write(field, value) \
26 __raw_writel(value, at91_aic_base + field)
27#else
28.extern at91_aic_base
29#endif
30
31/* Number of irq lines managed by AIC */
32#define NR_AIC_IRQS 32
33#define NR_AIC5_IRQS 128
34
35#define AT91_AIC5_SSR 0x0 /* Source Select Register [AIC5] */
36#define AT91_AIC5_INTSEL_MSK (0x7f << 0) /* Interrupt Line Selection Mask */
37
38#define AT91_AIC_IRQ_MIN_PRIORITY 0
39#define AT91_AIC_IRQ_MAX_PRIORITY 7
40
41#define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */
42#define AT91_AIC5_SMR 0x4 /* Source Mode Register [AIC5] */
43#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
44#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
45#define AT91_AIC_SRCTYPE_LOW (0 << 5)
46#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
47#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
48#define AT91_AIC_SRCTYPE_RISING (3 << 5)
49
50#define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
51#define AT91_AIC5_SVR 0x8 /* Source Vector Register [AIC5] */
52#define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */
53#define AT91_AIC5_IVR 0x10 /* Interrupt Vector Register [AIC5] */
54#define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */
55#define AT91_AIC5_FVR 0x14 /* Fast Interrupt Vector Register [AIC5] */
56#define AT91_AIC_ISR 0x108 /* Interrupt Status Register */
57#define AT91_AIC5_ISR 0x18 /* Interrupt Status Register [AIC5] */
58#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
59
60#define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */
61#define AT91_AIC5_IPR0 0x20 /* Interrupt Pending Register 0 [AIC5] */
62#define AT91_AIC5_IPR1 0x24 /* Interrupt Pending Register 1 [AIC5] */
63#define AT91_AIC5_IPR2 0x28 /* Interrupt Pending Register 2 [AIC5] */
64#define AT91_AIC5_IPR3 0x2c /* Interrupt Pending Register 3 [AIC5] */
65#define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */
66#define AT91_AIC5_IMR 0x30 /* Interrupt Mask Register [AIC5] */
67#define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */
68#define AT91_AIC5_CISR 0x34 /* Core Interrupt Status Register [AIC5] */
69#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
70#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
71
72#define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */
73#define AT91_AIC5_IECR 0x40 /* Interrupt Enable Command Register [AIC5] */
74#define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */
75#define AT91_AIC5_IDCR 0x44 /* Interrupt Disable Command Register [AIC5] */
76#define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */
77#define AT91_AIC5_ICCR 0x48 /* Interrupt Clear Command Register [AIC5] */
78#define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */
79#define AT91_AIC5_ISCR 0x4c /* Interrupt Set Command Register [AIC5] */
80#define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */
81#define AT91_AIC5_EOICR 0x38 /* End of Interrupt Command Register [AIC5] */
82#define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */
83#define AT91_AIC5_SPU 0x3c /* Spurious Interrupt Vector Register [AIC5] */
84#define AT91_AIC_DCR 0x138 /* Debug Control Register */
85#define AT91_AIC5_DCR 0x6c /* Debug Control Register [AIC5] */
86#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
87#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
88
89#define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */
90#define AT91_AIC5_FFER 0x50 /* Fast Forcing Enable Register [AIC5] */
91#define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */
92#define AT91_AIC5_FFDR 0x54 /* Fast Forcing Disable Register [AIC5] */
93#define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */
94#define AT91_AIC5_FFSR 0x58 /* Fast Forcing Status Register [AIC5] */
95
96void at91_aic_handle_irq(struct pt_regs *regs);
97void at91_aic5_handle_irq(struct pt_regs *regs);
98
99#endif
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 226563f850b8..feeb1a0f258e 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -22,7 +22,6 @@
22#include <asm/mach/map.h> 22#include <asm/mach/map.h>
23#include <asm/mach/irq.h> 23#include <asm/mach/irq.h>
24 24
25#include "at91_aic.h"
26#include "generic.h" 25#include "generic.h"
27 26
28static void __init at91rm9200_dt_timer_init(void) 27static void __init at91rm9200_dt_timer_init(void)
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index d3048ccdc41f..67c1bcbf0ed9 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -21,7 +21,6 @@
21#include <asm/mach/map.h> 21#include <asm/mach/map.h>
22#include <asm/mach/irq.h> 22#include <asm/mach/irq.h>
23 23
24#include "at91_aic.h"
25#include "board.h" 24#include "board.h"
26#include "generic.h" 25#include "generic.h"
27 26
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 129e2917506b..8fb9ef5333f1 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -24,7 +24,6 @@
24#include <asm/mach/map.h> 24#include <asm/mach/map.h>
25#include <asm/mach/irq.h> 25#include <asm/mach/irq.h>
26 26
27#include "at91_aic.h"
28#include "generic.h" 27#include "generic.h"
29 28
30static void __init sama5_dt_device_init(void) 29static void __init sama5_dt_device_init(void)
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 1ec9b011b6a9..713d1d9e50a1 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -29,8 +29,6 @@ extern void __init at91_dt_initialize(void);
29 /* Interrupts */ 29 /* Interrupts */
30extern void __init at91_init_irq_default(void); 30extern void __init at91_init_irq_default(void);
31extern void __init at91_init_interrupts(unsigned int priority[]); 31extern void __init at91_init_interrupts(unsigned int priority[]);
32extern void __init at91_aic_init(unsigned int priority[],
33 unsigned int ext_irq_mask);
34extern int __init at91_aic_of_init(struct device_node *node, 32extern int __init at91_aic_of_init(struct device_node *node,
35 struct device_node *parent); 33 struct device_node *parent);
36extern int __init at91_aic5_of_init(struct device_node *node, 34extern int __init at91_aic5_of_init(struct device_node *node,
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
deleted file mode 100644
index cdb3ec9efd2b..000000000000
--- a/arch/arm/mach-at91/irq.c
+++ /dev/null
@@ -1,296 +0,0 @@
1/*
2 * linux/arch/arm/mach-at91/irq.c
3 *
4 * Copyright (C) 2004 SAN People
5 * Copyright (C) 2004 ATMEL
6 * Copyright (C) Rick Bronson
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/init.h>
24#include <linux/module.h>
25#include <linux/mm.h>
26#include <linux/bitmap.h>
27#include <linux/types.h>
28#include <linux/irq.h>
29#include <linux/of.h>
30#include <linux/of_address.h>
31#include <linux/of_irq.h>
32#include <linux/irqdomain.h>
33#include <linux/err.h>
34#include <linux/slab.h>
35
36#include <mach/hardware.h>
37#include <asm/irq.h>
38#include <asm/setup.h>
39
40#include <asm/exception.h>
41#include <asm/mach/arch.h>
42#include <asm/mach/irq.h>
43#include <asm/mach/map.h>
44
45#include "at91_aic.h"
46
47void __iomem *at91_aic_base;
48static struct irq_domain *at91_aic_domain;
49static struct device_node *at91_aic_np;
50static unsigned int n_irqs = NR_AIC_IRQS;
51
52#ifdef CONFIG_PM
53
54static unsigned long *wakeups;
55static unsigned long *backups;
56
57#define set_backup(bit) set_bit(bit, backups)
58#define clear_backup(bit) clear_bit(bit, backups)
59
60static int at91_aic_pm_init(void)
61{
62 backups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
63 if (!backups)
64 return -ENOMEM;
65
66 wakeups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
67 if (!wakeups) {
68 kfree(backups);
69 return -ENOMEM;
70 }
71
72 return 0;
73}
74
75static int at91_aic_set_wake(struct irq_data *d, unsigned value)
76{
77 if (unlikely(d->hwirq >= n_irqs))
78 return -EINVAL;
79
80 if (value)
81 set_bit(d->hwirq, wakeups);
82 else
83 clear_bit(d->hwirq, wakeups);
84
85 return 0;
86}
87
88void at91_irq_suspend(void)
89{
90 at91_aic_write(AT91_AIC_IDCR, *backups);
91 at91_aic_write(AT91_AIC_IECR, *wakeups);
92}
93
94void at91_irq_resume(void)
95{
96 at91_aic_write(AT91_AIC_IDCR, *wakeups);
97 at91_aic_write(AT91_AIC_IECR, *backups);
98}
99
100#else
101static inline int at91_aic_pm_init(void)
102{
103 return 0;
104}
105
106#define set_backup(bit)
107#define clear_backup(bit)
108#define at91_aic_set_wake NULL
109
110#endif /* CONFIG_PM */
111
112asmlinkage void __exception_irq_entry
113at91_aic_handle_irq(struct pt_regs *regs)
114{
115 u32 irqnr;
116 u32 irqstat;
117
118 irqnr = at91_aic_read(AT91_AIC_IVR);
119 irqstat = at91_aic_read(AT91_AIC_ISR);
120
121 /*
122 * ISR value is 0 when there is no current interrupt or when there is
123 * a spurious interrupt
124 */
125 if (!irqstat)
126 at91_aic_write(AT91_AIC_EOICR, 0);
127 else
128 handle_IRQ(irqnr, regs);
129}
130
131static void at91_aic_mask_irq(struct irq_data *d)
132{
133 /* Disable interrupt on AIC */
134 at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
135 /* Update ISR cache */
136 clear_backup(d->hwirq);
137}
138
139static void at91_aic_unmask_irq(struct irq_data *d)
140{
141 /* Enable interrupt on AIC */
142 at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
143 /* Update ISR cache */
144 set_backup(d->hwirq);
145}
146
147static void at91_aic_eoi(struct irq_data *d)
148{
149 /*
150 * Mark end-of-interrupt on AIC, the controller doesn't care about
151 * the value written. Moreover it's a write-only register.
152 */
153 at91_aic_write(AT91_AIC_EOICR, 0);
154}
155
156static unsigned long *at91_extern_irq;
157
158u32 at91_get_extern_irq(void)
159{
160 if (!at91_extern_irq)
161 return 0;
162 return *at91_extern_irq;
163}
164
165#define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)
166
167static int at91_aic_compute_srctype(struct irq_data *d, unsigned type)
168{
169 int srctype;
170
171 switch (type) {
172 case IRQ_TYPE_LEVEL_HIGH:
173 srctype = AT91_AIC_SRCTYPE_HIGH;
174 break;
175 case IRQ_TYPE_EDGE_RISING:
176 srctype = AT91_AIC_SRCTYPE_RISING;
177 break;
178 case IRQ_TYPE_LEVEL_LOW:
179 if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
180 srctype = AT91_AIC_SRCTYPE_LOW;
181 else
182 srctype = -EINVAL;
183 break;
184 case IRQ_TYPE_EDGE_FALLING:
185 if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
186 srctype = AT91_AIC_SRCTYPE_FALLING;
187 else
188 srctype = -EINVAL;
189 break;
190 default:
191 srctype = -EINVAL;
192 }
193
194 return srctype;
195}
196
197static int at91_aic_set_type(struct irq_data *d, unsigned type)
198{
199 unsigned int smr;
200 int srctype;
201
202 srctype = at91_aic_compute_srctype(d, type);
203 if (srctype < 0)
204 return srctype;
205
206 smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
207 at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
208
209 return 0;
210}
211
212static struct irq_chip at91_aic_chip = {
213 .name = "AIC",
214 .irq_mask = at91_aic_mask_irq,
215 .irq_unmask = at91_aic_unmask_irq,
216 .irq_set_type = at91_aic_set_type,
217 .irq_set_wake = at91_aic_set_wake,
218 .irq_eoi = at91_aic_eoi,
219};
220
221static void __init at91_aic_hw_init(unsigned int spu_vector)
222{
223 int i;
224
225 /*
226 * Perform 8 End Of Interrupt Command to make sure AIC
227 * will not Lock out nIRQ
228 */
229 for (i = 0; i < 8; i++)
230 at91_aic_write(AT91_AIC_EOICR, 0);
231
232 /*
233 * Spurious Interrupt ID in Spurious Vector Register.
234 * When there is no current interrupt, the IRQ Vector Register
235 * reads the value stored in AIC_SPU
236 */
237 at91_aic_write(AT91_AIC_SPU, spu_vector);
238
239 /* No debugging in AIC: Debug (Protect) Control Register */
240 at91_aic_write(AT91_AIC_DCR, 0);
241
242 /* Disable and clear all interrupts initially */
243 at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
244 at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
245}
246
247/*
248 * Initialize the AIC interrupt controller.
249 */
250void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask)
251{
252 unsigned int i;
253 int irq_base;
254
255 at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
256 * sizeof(*at91_extern_irq), GFP_KERNEL);
257
258 if (at91_aic_pm_init() || at91_extern_irq == NULL)
259 panic("Unable to allocate bit maps\n");
260
261 *at91_extern_irq = ext_irq_mask;
262
263 at91_aic_base = ioremap(AT91_AIC, 512);
264 if (!at91_aic_base)
265 panic("Unable to ioremap AIC registers\n");
266
267 /* Add irq domain for AIC */
268 irq_base = irq_alloc_descs(-1, 0, n_irqs, 0);
269 if (irq_base < 0) {
270 WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
271 irq_base = 0;
272 }
273 at91_aic_domain = irq_domain_add_legacy(at91_aic_np, n_irqs,
274 irq_base, 0,
275 &irq_domain_simple_ops, NULL);
276
277 if (!at91_aic_domain)
278 panic("Unable to add AIC irq domain\n");
279
280 irq_set_default_host(at91_aic_domain);
281
282 /*
283 * The IVR is used by macro get_irqnr_and_base to read and verify.
284 * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
285 */
286 for (i = 0; i < n_irqs; i++) {
287 /* Put hardware irq number in Source Vector Register: */
288 at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i);
289 /* Active Low interrupt, with the specified priority */
290 at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
291 irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq);
292 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
293 }
294
295 at91_aic_hw_init(n_irqs);
296}
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 4073ab7f38f3..a42360f69127 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -29,7 +29,6 @@
29#include <mach/cpu.h> 29#include <mach/cpu.h>
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31 31
32#include "at91_aic.h"
33#include "generic.h" 32#include "generic.h"
34#include "pm.h" 33#include "pm.h"
35#include "gpio.h" 34#include "gpio.h"
@@ -136,19 +135,6 @@ static int at91_pm_enter(suspend_state_t state)
136 else 135 else
137 at91_gpio_suspend(); 136 at91_gpio_suspend();
138 137
139 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base) {
140 at91_irq_suspend();
141
142 pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
143 /* remember all the always-wake irqs */
144 (at91_pmc_read(AT91_PMC_PCSR)
145 | (1 << AT91_ID_FIQ)
146 | (1 << AT91_ID_SYS)
147 | (at91_get_extern_irq()))
148 & at91_aic_read(AT91_AIC_IMR),
149 state);
150 }
151
152 switch (state) { 138 switch (state) {
153 /* 139 /*
154 * Suspend-to-RAM is like STANDBY plus slow clock mode, so 140 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
@@ -212,17 +198,9 @@ static int at91_pm_enter(suspend_state_t state)
212 goto error; 198 goto error;
213 } 199 }
214 200
215 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
216 pr_debug("AT91: PM - wakeup %08x\n",
217 at91_aic_read(AT91_AIC_IPR) &
218 at91_aic_read(AT91_AIC_IMR));
219
220error: 201error:
221 target_state = PM_SUSPEND_ON; 202 target_state = PM_SUSPEND_ON;
222 203
223 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
224 at91_irq_resume();
225
226 if (of_have_populated_dt()) 204 if (of_have_populated_dt())
227 at91_pinctrl_gpio_resume(); 205 at91_pinctrl_gpio_resume();
228 else 206 else
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 98b0c1a62899..6c3013e3309b 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -49,10 +49,6 @@ void __init at91_init_irq_default(void)
49 49
50void __init at91_init_interrupts(unsigned int *priority) 50void __init at91_init_interrupts(unsigned int *priority)
51{ 51{
52 /* Initialize the AIC interrupt controller */
53 if (IS_ENABLED(CONFIG_OLD_IRQ_AT91))
54 at91_aic_init(priority, at91_boot_soc.extern_irq);
55
56 /* Enable GPIO interrupts */ 52 /* Enable GPIO interrupts */
57 at91_gpio_irq_setup(); 53 at91_gpio_irq_setup();
58} 54}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 07:30:45 -0500