Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull "ARM: device tree work" from Arnd Bergmann: "Most of these patches convert code from using static platform data to describing the hardware in the device tree. This is only the first half of the changes for v3.4 because a lot of patches for this topic came in the last week before the merge window. Signed-off-by: Arnd Bergmann <arnd@arndb.de>" Fix up trivial conflicts in arch/arm/mach-vexpress/{Kconfig,core.h} * tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (86 commits) Document: devicetree: add OF documents for arch-mmp ARM: dts: append DTS file of pxa168 ARM: mmp: append OF support on pxa168 ARM: mmp: enable rtc clk in pxa168 i2c: pxa: add OF support serial: pxa: add OF support arm/dts: mt_ventoux: very basic support for TeeJet Mt.Ventoux board ARM: OMAP2+: Remove extra ifdefs for board-generic ARM: OMAP2+: Fix build error when only ARCH_OMAP2/3 or 4 is selected ASoC: DT: Add digital microphone binding to PAZ00 board. ARM: dt: Add ARM PMU to tegra*.dtsi ARM: at91: at91sam9x5cm/dt: add leds support ARM: at91: usb_a9g20/dt: add gpio-keys support ARM: at91: at91sam9m10g45ek/dt: add gpio-keys support ARM: at91: at91sam9m10g45ek/dt: add leds support ARM: at91: usb_a9g20/dt: add leds support ARM: at91/pio: add new PIO3 features ARM: at91: add sam9_smc.o to at91sam9x5 build ARM: at91/tc/clocksource: Add 32 bit variant to Timer Counter ARM: at91/tc: add device tree support to atmel_tclib ...
author: Linus Torvalds <torvalds@linux-foundation.org> 2012-03-27 19:47:35 -0400
committer: Linus Torvalds <torvalds@linux-foundation.org> 2012-03-27 19:47:35 -0400
commit: 66f03c614c0902ccf7d6160459362a9352f33271 (patch)
tree: b9a8864efe5aa7fc5c96cc5ccbeca41f5cd6f6a7 /arch/arm/mach-at91
parent: 34800598b2eebe061445216473b1e4c2ff5cba99 (diff)
parent: cdc3df6f44f72c5924a16a47e1663c3fb0e57820 (diff)
64 files changed, 1675 insertions, 746 deletions
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 1b6518518d99..8512e53bed93 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -20,7 +20,7 @@ obj-$(CONFIG_ARCH_AT91SAM9263)	+= at91sam9263.o at91sam926x_time.o at91sam9263_d
 obj-$(CONFIG_ARCH_AT91SAM9RL)   += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9G45)  += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT91SAM9X5)   += at91sam9x5.o at91sam926x_time.o
+obj-$(CONFIG_ARCH_AT91SAM9X5)   += at91sam9x5.o at91sam926x_time.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91X40)      += at91x40.o at91x40_time.o
 # AT91RM9200 board-specific support
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 2fd051eb2449..0da66ca4a4f8 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -13,4 +13,10 @@ params_phys-y	:= 0x20000100
 initrd_phys-y   := 0x20410000
 endif
-dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb usb_a9g20.dtb
+# Keep dtb files sorted alphabetically for each SoC
+# sam9g20
+dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb
+# sam9g45
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb
+# sam9x5
+dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index dd6e2de13420..0df1045311e4 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -295,7 +295,7 @@ static void at91rm9200_idle(void)
         * Disable the processor clock.  The processor will be automatically
         * re-enabled by an interrupt or by a reset.
         */
-        at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+        at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
 }
 static void at91rm9200_restart(char mode, const char *cmd)
@@ -303,8 +303,8 @@ static void at91rm9200_restart(char mode, const char *cmd)
        /*
         * Perform a hardware reset with the use of the Watchdog timer.
         */
-        at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
+        at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
-        at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
+        at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
 }
 /* --------------------------------------------------------------------
@@ -319,6 +319,8 @@ static void __init at91rm9200_map_io(void)
 static void __init at91rm9200_ioremap_registers(void)
 {
+        at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
+        at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
 }
 static void __init at91rm9200_initialize(void)
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 97676bdae998..99ce5c955e39 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -21,6 +21,7 @@
 #include <mach/board.h>
 #include <mach/at91rm9200.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include "generic.h"
@@ -241,15 +242,15 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
        data->chipselect = 4;           /* can only use EBI ChipSelect 4 */
        /* CF takes over CS4, CS5, CS6 */
-        csa = at91_sys_read(AT91_EBI_CSA);
+        csa = at91_ramc_read(0, AT91_EBI_CSA);
-        at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
+        at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
        /*
         * Static memory controller timing adjustments.
         * REVISIT:  these timings are in terms of MCK cycles, so
         * when MCK changes (cpufreq etc) so must these values...
         */
-        at91_sys_write(AT91_SMC_CSR(4),
+        at91_ramc_write(0, AT91_SMC_CSR(4),
                                  AT91_SMC_ACSS_STD
                                | AT91_SMC_DBW_16
                                | AT91_SMC_BAT
@@ -407,11 +408,11 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
                return;
        /* enable the address range of CS3 */
-        csa = at91_sys_read(AT91_EBI_CSA);
+        csa = at91_ramc_read(0, AT91_EBI_CSA);
-        at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
+        at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
        /* set the bus interface characteristics */
-        at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
+        at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
                | AT91_SMC_NWS_(5)
                | AT91_SMC_TDF_(1)
                | AT91_SMC_RWSETUP_(0)  /* tDS Data Set up Time 30 - ns */
@@ -1114,7 +1115,6 @@ static inline void configure_usart3_pins(unsigned pins)
 }
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index a028cdf8f974..dd7f782b0b91 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -43,9 +43,9 @@ static inline unsigned long read_CRTR(void)
 {
        unsigned long x1, x2;
-        x1 = at91_sys_read(AT91_ST_CRTR);
+        x1 = at91_st_read(AT91_ST_CRTR);
        do {
-                x2 = at91_sys_read(AT91_ST_CRTR);
+                x2 = at91_st_read(AT91_ST_CRTR);
                if (x1 == x2)
                        break;
                x1 = x2;
@@ -58,7 +58,7 @@ static inline unsigned long read_CRTR(void)
 */
 static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
 {
-        u32     sr = at91_sys_read(AT91_ST_SR) & irqmask;
+        u32     sr = at91_st_read(AT91_ST_SR) & irqmask;
        /*
         * irqs should be disabled here, but as the irq is shared they are only
@@ -110,22 +110,22 @@ static void
 clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 {
        /* Disable and flush pending timer interrupts */
-        at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
+        at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
-        (void) at91_sys_read(AT91_ST_SR);
+        at91_st_read(AT91_ST_SR);
        last_crtr = read_CRTR();
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
                /* PIT for periodic irqs; fixed rate of 1/HZ */
                irqmask = AT91_ST_PITS;
-                at91_sys_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
+                at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
                break;
        case CLOCK_EVT_MODE_ONESHOT:
                /* ALM for oneshot irqs, set by next_event()
                 * before 32 seconds have passed
                 */
                irqmask = AT91_ST_ALMS;
-                at91_sys_write(AT91_ST_RTAR, last_crtr);
+                at91_st_write(AT91_ST_RTAR, last_crtr);
                break;
        case CLOCK_EVT_MODE_SHUTDOWN:
        case CLOCK_EVT_MODE_UNUSED:
@@ -133,7 +133,7 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
                irqmask = 0;
                break;
        }
-        at91_sys_write(AT91_ST_IER, irqmask);
+        at91_st_write(AT91_ST_IER, irqmask);
 }
 static int
@@ -156,12 +156,12 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
        alm = read_CRTR();
        /* Cancel any pending alarm; flush any pending IRQ */
-        at91_sys_write(AT91_ST_RTAR, alm);
+        at91_st_write(AT91_ST_RTAR, alm);
-        (void) at91_sys_read(AT91_ST_SR);
+        at91_st_read(AT91_ST_SR);
        /* Schedule alarm by writing RTAR. */
        alm += delta;
-        at91_sys_write(AT91_ST_RTAR, alm);
+        at91_st_write(AT91_ST_RTAR, alm);
        return status;
 }
@@ -175,15 +175,24 @@ static struct clock_event_device clkevt = {
        .set_mode       = clkevt32k_mode,
 };
+void __iomem *at91_st_base;
+void __init at91rm9200_ioremap_st(u32 addr)
+{
+        at91_st_base = ioremap(addr, 256);
+        if (!at91_st_base)
+                panic("Impossible to ioremap ST\n");
+}
 /*
 * ST (system timer) module supports both clockevents and clocksource.
 */
 void __init at91rm9200_timer_init(void)
 {
        /* Disable all timer interrupts, and clear any pending ones */
-        at91_sys_write(AT91_ST_IDR,
+        at91_st_write(AT91_ST_IDR,
                AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
-        (void) at91_sys_read(AT91_ST_SR);
+        at91_st_read(AT91_ST_SR);
        /* Make IRQs happen for the system timer */
        setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
@@ -192,7 +201,7 @@ void __init at91rm9200_timer_init(void)
         * directly for the clocksource and all clockevents, after adjusting
         * its prescaler from the 1 Hz default.
         */
-        at91_sys_write(AT91_ST_RTMR, 1);
+        at91_st_write(AT91_ST_RTMR, 1);
        /* Setup timer clockevent, with minimum of two ticks (important!!) */
        clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 9ac8c6fe3363..14b5a9c9a514 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -209,6 +209,13 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
        CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
        CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
+        /* more tc lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
+        CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
+        CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
+        CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
+        CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
        CLKDEV_CON_ID("pioA", &pioA_clk),
@@ -310,34 +317,27 @@ static void __init at91sam9xe_map_io(void)
 static void __init at91sam9260_map_io(void)
 {
-        if (cpu_is_at91sam9xe()) {
+        if (cpu_is_at91sam9xe())
                at91sam9xe_map_io();
-        } else if (cpu_is_at91sam9g20()) {
+        else if (cpu_is_at91sam9g20())
-                at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE);
+                at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
-                at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE);
+        else
-        } else {
+                at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
-                at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE);
-                at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE);
-        }
 }
 static void __init at91sam9260_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
        at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
+        at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
        at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
-}
+        at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
-static void at91sam9260_idle(void)
-{
-        at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-        cpu_do_idle();
 }
 static void __init at91sam9260_initialize(void)
 {
-        arm_pm_idle = at91sam9260_idle;
+        arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9_alt_restart;
        at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
                        | (1 << AT91SAM9260_ID_IRQ2);
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 5a24f0b4554d..7e5651ee9f85 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -21,6 +21,7 @@
 #include <mach/cpu.h>
 #include <mach/at91sam9260.h>
 #include <mach/at91sam9260_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include "generic.h"
@@ -422,8 +423,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        if (!data)
                return;
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
        /* enable pin */
        if (gpio_is_valid(data->enable_pin))
@@ -641,7 +642,7 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 static struct resource tcb0_resources[] = {
        [0] = {
                .start  = AT91SAM9260_BASE_TCB0,
-                .end    = AT91SAM9260_BASE_TCB0 + SZ_16K - 1,
+                .end    = AT91SAM9260_BASE_TCB0 + SZ_256 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -671,7 +672,7 @@ static struct platform_device at91sam9260_tcb0_device = {
 static struct resource tcb1_resources[] = {
        [0] = {
                .start  = AT91SAM9260_BASE_TCB1,
-                .end    = AT91SAM9260_BASE_TCB1 + SZ_16K - 1,
+                .end    = AT91SAM9260_BASE_TCB1 + SZ_256 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -698,8 +699,25 @@ static struct platform_device at91sam9260_tcb1_device = {
        .num_resources  = ARRAY_SIZE(tcb1_resources),
 };
+#if defined(CONFIG_OF)
+static struct of_device_id tcb_ids[] = {
+        { .compatible = "atmel,at91rm9200-tcb" },
+        { /*sentinel*/ }
+};
+#endif
 static void __init at91_add_device_tc(void)
 {
+#if defined(CONFIG_OF)
+        struct device_node *np;
+        np = of_find_matching_node(NULL, tcb_ids);
+        if (np) {
+                of_node_put(np);
+                return;
+        }
+#endif
        platform_device_register(&at91sam9260_tcb0_device);
        platform_device_register(&at91sam9260_tcb1_device);
 }
@@ -717,18 +735,42 @@ static struct resource rtt_resources[] = {
                .start  = AT91SAM9260_BASE_RTT,
                .end    = AT91SAM9260_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
-        }
+        }, {
+                .flags  = IORESOURCE_MEM,
+        },
 };
 static struct platform_device at91sam9260_rtt_device = {
        .name           = "at91_rtt",
        .id             = 0,
        .resource       = rtt_resources,
-        .num_resources  = ARRAY_SIZE(rtt_resources),
 };
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+        at91sam9260_rtt_device.name = "rtc-at91sam9";
+        /*
+         * The second resource is needed:
+         * GPBR will serve as the storage for RTC time offset
+         */
+        at91sam9260_rtt_device.num_resources = 2;
+        rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
+                                 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+        rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+        /* Only one resource is needed: RTT not used as RTC */
+        at91sam9260_rtt_device.num_resources = 1;
+}
+#endif
 static void __init at91_add_device_rtt(void)
 {
+        at91_add_device_rtt_rtc();
        platform_device_register(&at91sam9260_rtt_device);
 }
@@ -1139,7 +1181,6 @@ static inline void configure_usart5_pins(void)
 }
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
@@ -1264,7 +1305,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
        if (!data)
                return;
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
        switch (data->chipselect) {
        case 4:
@@ -1287,7 +1328,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
                return;
        }
-        at91_sys_write(AT91_MATRIX_EBICSA, csa);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa);
        if (gpio_is_valid(data->rst_pin)) {
                at91_set_multi_drive(data->rst_pin, 0);
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index ab76868f01f5..684c5dfd92ac 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -283,19 +283,15 @@ static void __init at91sam9261_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
        at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
+        at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
        at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
-}
+        at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
-static void at91sam9261_idle(void)
-{
-        at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-        cpu_do_idle();
 }
 static void __init at91sam9261_initialize(void)
 {
-        arm_pm_idle = at91sam9261_idle;
+        arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9_alt_restart;
        at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
                        | (1 << AT91SAM9261_ID_IRQ2);
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 1e28bed8f425..096da87dc00d 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -24,6 +24,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9261.h>
 #include <mach/at91sam9261_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include "generic.h"
@@ -236,8 +237,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        if (!data)
                return;
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
        /* enable pin */
        if (gpio_is_valid(data->enable_pin))
@@ -603,6 +604,8 @@ static struct resource rtt_resources[] = {
                .start  = AT91SAM9261_BASE_RTT,
                .end    = AT91SAM9261_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_MEM,
        }
 };
@@ -610,11 +613,32 @@ static struct platform_device at91sam9261_rtt_device = {
        .name           = "at91_rtt",
        .id             = 0,
        .resource       = rtt_resources,
-        .num_resources  = ARRAY_SIZE(rtt_resources),
 };
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+        at91sam9261_rtt_device.name = "rtc-at91sam9";
+        /*
+         * The second resource is needed:
+         * GPBR will serve as the storage for RTC time offset
+         */
+        at91sam9261_rtt_device.num_resources = 2;
+        rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
+                                 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+        rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+        /* Only one resource is needed: RTT not used as RTC */
+        at91sam9261_rtt_device.num_resources = 1;
+}
+#endif
 static void __init at91_add_device_rtt(void)
 {
+        at91_add_device_rtt_rtc();
        platform_device_register(&at91sam9261_rtt_device);
 }
@@ -991,7 +1015,6 @@ static inline void configure_usart2_pins(unsigned pins)
 }
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 247ab633abcc..0b4fa5a7f685 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -303,20 +303,17 @@ static void __init at91sam9263_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
        at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
+        at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
+        at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
        at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
        at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
-}
+        at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
-static void at91sam9263_idle(void)
-{
-        at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-        cpu_do_idle();
 }
 static void __init at91sam9263_initialize(void)
 {
-        arm_pm_idle = at91sam9263_idle;
+        arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9_alt_restart;
        at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 70709ab0102a..53688c46f956 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -23,6 +23,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9263.h>
 #include <mach/at91sam9263_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include "generic.h"
@@ -409,7 +410,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
         * we assume SMC timings are configured by board code,
         * except True IDE where timings are controlled by driver
         */
-        ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
+        ebi0_csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
        switch (data->chipselect) {
        case 4:
                at91_set_A_periph(AT91_PIN_PD6, 0);  /* EBI0_NCS4/CFCS0 */
@@ -428,7 +429,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
                       data->chipselect);
                return;
        }
-        at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
+        at91_matrix_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
        if (gpio_is_valid(data->det_pin)) {
                at91_set_gpio_input(data->det_pin, 1);
@@ -496,8 +497,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        if (!data)
                return;
-        csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
+        csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
-        at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+        at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
        /* enable pin */
        if (gpio_is_valid(data->enable_pin))
@@ -966,6 +967,8 @@ static struct resource rtt0_resources[] = {
                .start  = AT91SAM9263_BASE_RTT0,
                .end    = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_MEM,
        }
 };
@@ -973,7 +976,6 @@ static struct platform_device at91sam9263_rtt0_device = {
        .name           = "at91_rtt",
        .id             = 0,
        .resource       = rtt0_resources,
-        .num_resources  = ARRAY_SIZE(rtt0_resources),
 };
 static struct resource rtt1_resources[] = {
@@ -981,6 +983,8 @@ static struct resource rtt1_resources[] = {
                .start  = AT91SAM9263_BASE_RTT1,
                .end    = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_MEM,
        }
 };
@@ -988,11 +992,53 @@ static struct platform_device at91sam9263_rtt1_device = {
        .name           = "at91_rtt",
        .id             = 1,
        .resource       = rtt1_resources,
-        .num_resources  = ARRAY_SIZE(rtt1_resources),
 };
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+        struct platform_device *pdev;
+        struct resource *r;
+        switch (CONFIG_RTC_DRV_AT91SAM9_RTT) {
+        case 0:
+                /*
+                 * The second resource is needed only for the chosen RTT:
+                 * GPBR will serve as the storage for RTC time offset
+                 */
+                at91sam9263_rtt0_device.num_resources = 2;
+                at91sam9263_rtt1_device.num_resources = 1;
+                pdev = &at91sam9263_rtt0_device;
+                r = rtt0_resources;
+                break;
+        case 1:
+                at91sam9263_rtt0_device.num_resources = 1;
+                at91sam9263_rtt1_device.num_resources = 2;
+                pdev = &at91sam9263_rtt1_device;
+                r = rtt1_resources;
+                break;
+        default:
+                pr_err("at91sam9263: only supports 2 RTT (%d)\n",
+                       CONFIG_RTC_DRV_AT91SAM9_RTT);
+                return;
+        }
+        pdev->name = "rtc-at91sam9";
+        r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+        r[1].end = r[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+        /* Only one resource is needed: RTT not used as RTC */
+        at91sam9263_rtt0_device.num_resources = 1;
+        at91sam9263_rtt1_device.num_resources = 1;
+}
+#endif
 static void __init at91_add_device_rtt(void)
 {
+        at91_add_device_rtt_rtc();
        platform_device_register(&at91sam9263_rtt0_device);
        platform_device_register(&at91sam9263_rtt1_device);
 }
@@ -1378,7 +1424,6 @@ static inline void configure_usart2_pins(unsigned pins)
 }
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index d89ead740a99..a94758b42737 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -14,6 +14,9 @@
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/clockchips.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <asm/mach/time.h>
@@ -133,7 +136,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
 static struct irqaction at91sam926x_pit_irq = {
        .name           = "at91_tick",
        .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = at91sam926x_pit_interrupt
+        .handler        = at91sam926x_pit_interrupt,
+        .irq            = AT91_ID_SYS,
 };
 static void at91sam926x_pit_reset(void)
@@ -149,6 +153,51 @@ static void at91sam926x_pit_reset(void)
        pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 }
+#ifdef CONFIG_OF
+static struct of_device_id pit_timer_ids[] = {
+        { .compatible = "atmel,at91sam9260-pit" },
+        { /* sentinel */ }
+};
+static int __init of_at91sam926x_pit_init(void)
+{
+        struct device_node      *np;
+        int                     ret;
+        np = of_find_matching_node(NULL, pit_timer_ids);
+        if (!np)
+                goto err;
+        pit_base_addr = of_iomap(np, 0);
+        if (!pit_base_addr)
+                goto node_err;
+        /* Get the interrupts property */
+        ret = irq_of_parse_and_map(np, 0);
+        if (!ret) {
+                pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
+                goto ioremap_err;
+        }
+        at91sam926x_pit_irq.irq = ret;
+        of_node_put(np);
+        return 0;
+ioremap_err:
+        iounmap(pit_base_addr);
+node_err:
+        of_node_put(np);
+err:
+        return -EINVAL;
+}
+#else
+static int __init of_at91sam926x_pit_init(void)
+{
+        return -EINVAL;
+}
+#endif
 /*
 * Set up both clocksource and clockevent support.
 */
@@ -156,6 +205,10 @@ static void __init at91sam926x_pit_init(void)
 {
        unsigned long   pit_rate;
        unsigned        bits;
+        int             ret;
+        /* For device tree enabled device: initialize here */
+        of_at91sam926x_pit_init();
        /*
         * Use our actual MCK to figure out how many MCK/16 ticks per
@@ -177,7 +230,9 @@ static void __init at91sam926x_pit_init(void)
        clocksource_register_hz(&pit_clk, pit_rate);
        /* Set up irq handler */
-        setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq);
+        ret = setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq);
+        if (ret)
+                pr_crit("AT91: PIT: Unable to setup IRQ\n");
        /* Set up and register clockevents */
        pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift);
@@ -193,6 +248,15 @@ static void at91sam926x_pit_suspend(void)
 void __init at91sam926x_ioremap_pit(u32 addr)
 {
+#if defined(CONFIG_OF)
+        struct device_node *np =
+                of_find_matching_node(NULL, pit_timer_ids);
+        if (np) {
+                of_node_put(np);
+                return;
+        }
+#endif
        pit_base_addr = ioremap(addr, 16);
        if (!pit_base_addr)
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
index 518e42377171..7af2e108b8a0 100644
--- a/arch/arm/mach-at91/at91sam9_alt_reset.S
+++ b/arch/arm/mach-at91/at91sam9_alt_reset.S
@@ -15,16 +15,17 @@
 #include <linux/linkage.h>
 #include <mach/hardware.h>
-#include <mach/at91sam9_sdramc.h>
+#include <mach/at91_ramc.h>
 #include <mach/at91_rstc.h>
                        .arm
                        .globl  at91sam9_alt_restart
-at91sam9_alt_restart:   ldr     r0, .at91_va_base_sdramc        @ preload constants
+at91sam9_alt_restart:   ldr     r0, =at91_ramc_base             @ preload constants
-                        ldr     r1, =at91_rstc_base
+                        ldr     r0, [r0]
-                        ldr     r1, [r1]
+                        ldr     r4, =at91_rstc_base
+                        ldr     r1, [r4]
                        mov     r2, #1
                        mov     r3, #AT91_SDRAMC_LPCB_POWER_DOWN
@@ -37,6 +38,3 @@ at91sam9_alt_restart:	ldr	r0, .at91_va_base_sdramc	@ preload constants
                        str     r4, [r1, #AT91_RSTC_CR]         @ reset processor
                        b       .
-.at91_va_base_sdramc:
-        .word AT91_VA_BASE_SYS + AT91_SDRAMC0
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 5b12192e52ec..0014573dfe17 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -229,6 +229,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
        CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
        CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
+        /* more tc lookup table for DT entries */
+        CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
        CLKDEV_CON_ID("pioA", &pioA_clk),
@@ -317,12 +320,6 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
        }
 };
-static void at91sam9g45_idle(void)
-{
-        at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-        cpu_do_idle();
-}
 /* --------------------------------------------------------------------
 *  AT91SAM9G45 processor initialization
 * -------------------------------------------------------------------- */
@@ -337,13 +334,16 @@ static void __init at91sam9g45_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
        at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
+        at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
+        at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
        at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
+        at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
 }
 static void __init at91sam9g45_initialize(void)
 {
-        arm_pm_idle = at91sam9g45_idle;
+        arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9g45_restart;
        at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index bd4e68cd3e2f..4320b2096789 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -25,6 +25,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9g45.h>
 #include <mach/at91sam9g45_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at_hdmac.h>
 #include <mach/atmel-mci.h>
@@ -557,8 +558,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        if (!data)
                return;
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
        /* enable pin */
        if (gpio_is_valid(data->enable_pin))
@@ -1051,7 +1052,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 static struct resource tcb0_resources[] = {
        [0] = {
                .start  = AT91SAM9G45_BASE_TCB0,
-                .end    = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
+                .end    = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -1072,7 +1073,7 @@ static struct platform_device at91sam9g45_tcb0_device = {
 static struct resource tcb1_resources[] = {
        [0] = {
                .start  = AT91SAM9G45_BASE_TCB1,
-                .end    = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
+                .end    = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -1089,8 +1090,25 @@ static struct platform_device at91sam9g45_tcb1_device = {
        .num_resources  = ARRAY_SIZE(tcb1_resources),
 };
+#if defined(CONFIG_OF)
+static struct of_device_id tcb_ids[] = {
+        { .compatible = "atmel,at91rm9200-tcb" },
+        { /*sentinel*/ }
+};
+#endif
 static void __init at91_add_device_tc(void)
 {
+#if defined(CONFIG_OF)
+        struct device_node *np;
+        np = of_find_matching_node(NULL, tcb_ids);
+        if (np) {
+                of_node_put(np);
+                return;
+        }
+#endif
        platform_device_register(&at91sam9g45_tcb0_device);
        platform_device_register(&at91sam9g45_tcb1_device);
 }
@@ -1193,6 +1211,8 @@ static struct resource rtt_resources[] = {
                .start  = AT91SAM9G45_BASE_RTT,
                .end    = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_MEM,
        }
 };
@@ -1200,11 +1220,32 @@ static struct platform_device at91sam9g45_rtt_device = {
        .name           = "at91_rtt",
        .id             = 0,
        .resource       = rtt_resources,
-        .num_resources  = ARRAY_SIZE(rtt_resources),
 };
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+        at91sam9g45_rtt_device.name = "rtc-at91sam9";
+        /*
+         * The second resource is needed:
+         * GPBR will serve as the storage for RTC time offset
+         */
+        at91sam9g45_rtt_device.num_resources = 2;
+        rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
+                                 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+        rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+        /* Only one resource is needed: RTT not used as RTC */
+        at91sam9g45_rtt_device.num_resources = 1;
+}
+#endif
 static void __init at91_add_device_rtt(void)
 {
+        at91_add_device_rtt_rtc();
        platform_device_register(&at91sam9g45_rtt_device);
 }
@@ -1659,7 +1700,6 @@ static inline void configure_usart3_pins(unsigned pins)
 }
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 0468be10980b..9d457182c86c 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -12,7 +12,7 @@
 #include <linux/linkage.h>
 #include <mach/hardware.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ramc.h>
 #include <mach/at91_rstc.h>
                        .arm
@@ -20,9 +20,10 @@
                        .globl  at91sam9g45_restart
 at91sam9g45_restart:
-                        ldr     r0, .at91_va_base_sdramc0       @ preload constants
+                        ldr     r5, =at91_ramc_base             @ preload constants
-                        ldr     r1, =at91_rstc_base
+                        ldr     r0, [r5]
-                        ldr     r1, [r1]
+                        ldr     r4, =at91_rstc_base
+                        ldr     r1, [r4]
                        mov     r2, #1
                        mov     r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
@@ -35,6 +36,3 @@ at91sam9g45_restart:
                        str     r4, [r1, #AT91_RSTC_CR]         @ reset processor
                        b       .
-.at91_va_base_sdramc0:
-        .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index fd60e226a987..63d9372eb18e 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -288,19 +288,15 @@ static void __init at91sam9rl_ioremap_registers(void)
 {
        at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
        at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
+        at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
        at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
        at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
-}
+        at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
-static void at91sam9rl_idle(void)
-{
-        at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
-        cpu_do_idle();
 }
 static void __init at91sam9rl_initialize(void)
 {
-        arm_pm_idle = at91sam9rl_idle;
+        arm_pm_idle = at91sam9_idle;
        arm_pm_restart = at91sam9_alt_restart;
        at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 9be71c11d0f0..eda72e83037d 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -20,6 +20,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9rl.h>
 #include <mach/at91sam9rl_matrix.h>
+#include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at_hdmac.h>
@@ -265,8 +266,8 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        if (!data)
                return;
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
        /* enable pin */
        if (gpio_is_valid(data->enable_pin))
@@ -682,6 +683,8 @@ static struct resource rtt_resources[] = {
                .start  = AT91SAM9RL_BASE_RTT,
                .end    = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_MEM,
        }
 };
@@ -689,11 +692,32 @@ static struct platform_device at91sam9rl_rtt_device = {
        .name           = "at91_rtt",
        .id             = 0,
        .resource       = rtt_resources,
-        .num_resources  = ARRAY_SIZE(rtt_resources),
 };
+#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
+static void __init at91_add_device_rtt_rtc(void)
+{
+        at91sam9rl_rtt_device.name = "rtc-at91sam9";
+        /*
+         * The second resource is needed:
+         * GPBR will serve as the storage for RTC time offset
+         */
+        at91sam9rl_rtt_device.num_resources = 2;
+        rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
+                                 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
+        rtt_resources[1].end = rtt_resources[1].start + 3;
+}
+#else
+static void __init at91_add_device_rtt_rtc(void)
+{
+        /* Only one resource is needed: RTT not used as RTC */
+        at91sam9rl_rtt_device.num_resources = 1;
+}
+#endif
 static void __init at91_add_device_rtt(void)
 {
+        at91_add_device_rtt_rtc();
        platform_device_register(&at91sam9rl_rtt_device);
 }
@@ -1128,7 +1152,6 @@ static inline void configure_usart3_pins(unsigned pins)
 }
 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 1c3444d2ee0c..a34d96afa746 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -301,8 +301,7 @@ static void __init at91sam9x5_map_io(void)
 static void __init at91sam9x5_ioremap_registers(void)
 {
-        if (of_at91sam926x_pit_init() < 0)
+        at91_ioremap_ramc(0, AT91SAM9X5_BASE_DDRSDRC0, 512);
-                panic("Impossible to find PIT\n");
 }
 void __init at91sam9x5_initialize(void)
@@ -317,10 +316,6 @@ void __init at91sam9x5_initialize(void)
 /* --------------------------------------------------------------------
 *  AT91SAM9x5 devices (temporary before modification of code)
 * -------------------------------------------------------------------- */
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_set_serial_console(unsigned portnr) {}
-struct platform_device *atmel_default_console_device = NULL;
 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
 /* --------------------------------------------------------------------
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 0154b7f44ff1..5400a1d65035 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -44,7 +44,7 @@ static void at91x40_idle(void)
         * Disable the processor clock.  The processor will be automatically
         * re-enabled by an interrupt or by a reset.
         */
-        at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
+        __raw_writel(AT91_PS_CR_CPU, AT91_PS_CR);
        cpu_do_idle();
 }
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index dfff2895f4b2..6ca680a1d5d1 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -28,6 +28,12 @@
 #include <asm/mach/time.h>
 #include <mach/at91_tc.h>
+#define at91_tc_read(field) \
+        __raw_readl(AT91_TC + field)
+#define at91_tc_write(field, value) \
+        __raw_writel(value, AT91_TC + field);
 /*
 *      3 counter/timer units present.
 */
@@ -37,12 +43,12 @@
 static unsigned long at91x40_gettimeoffset(void)
 {
-        return (at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
+        return (at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
 }
 static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
 {
-        at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR);
+        at91_tc_read(AT91_TC_CLK1BASE + AT91_TC_SR);
        timer_tick();
        return IRQ_HANDLED;
 }
@@ -57,20 +63,20 @@ void __init at91x40_timer_init(void)
 {
        unsigned int v;
-        at91_sys_write(AT91_TC + AT91_TC_BCR, 0);
+        at91_tc_write(AT91_TC_BCR, 0);
-        v = at91_sys_read(AT91_TC + AT91_TC_BMR);
+        v = at91_tc_read(AT91_TC_BMR);
        v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
-        at91_sys_write(AT91_TC + AT91_TC_BMR, v);
+        at91_tc_write(AT91_TC_BMR, v);
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
        setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
-        at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
+        at91_tc_write(AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
 }
 struct sys_timer at91x40_timer = {
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 9ab3d1ea326d..989e1c5a9ca0 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -43,6 +43,7 @@
 #include <mach/board.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91sam9260_matrix.h>
+#include <mach/at91_matrix.h>
 #include "sam9_smc.h"
 #include "generic.h"
@@ -238,8 +239,8 @@ static __init void cpu9krea_add_device_nor(void)
 {
        unsigned long csa;
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        csa = at91_matrix_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
+        at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
        /* configure chip-select 0 (NOR) */
        sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 368e1427ad99..e094cc81fe25 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -38,6 +38,7 @@
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index 05793156d178..583b72472ad9 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -15,7 +15,7 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/gpio.h>
-#include <linux/irqdomain.h>
+#include <linux/of.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
@@ -38,12 +38,6 @@ static void __init ek_init_early(void)
 {
        /* Initialize processor: 12.000 MHz crystal */
        at91_initialize(12000000);
-        /* DGBU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
 }
 /* det_pin is not connected */
@@ -88,15 +82,17 @@ static void __init ek_add_device_nand(void)
        at91_add_device_nand(&ek_nand_data);
 }
-static const struct of_device_id aic_of_match[] __initconst = {
+static const struct of_device_id irq_of_match[] __initconst = {
-        { .compatible = "atmel,at91rm9200-aic", },
-        {},
+        { .compatible = "atmel,at91rm9200-aic", .data = at91_aic_of_init },
+        { .compatible = "atmel,at91rm9200-gpio", .data = at91_gpio_of_irq_setup },
+        { .compatible = "atmel,at91sam9x5-gpio", .data = at91_gpio_of_irq_setup },
+        { /*sentinel*/ }
 };
 static void __init at91_dt_init_irq(void)
 {
-        irq_domain_generate_simple(aic_of_match, 0xfffff000, 0);
+        of_irq_init(irq_of_match);
-        at91_init_irq_default();
 }
 static void __init at91_dt_device_init(void)
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 07ef35b0ec2c..f23aabef8551 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -26,6 +26,7 @@
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 #include "generic.h"
@@ -110,7 +111,7 @@ static void __init eco920_board_init(void)
        at91_add_device_mmc(0, &eco920_mmc_data);
        platform_device_register(&eco920_flash);
-        at91_sys_write(AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
+        at91_ramc_write(0, AT91_SMC_CSR(7),     AT91_SMC_RWHOLD_(1)
                                | AT91_SMC_RWSETUP_(1)
                                | AT91_SMC_DBW_8
                                | AT91_SMC_WSEN
@@ -122,7 +123,7 @@ static void __init eco920_board_init(void)
        at91_set_deglitch(AT91_PIN_PA23, 1);
 /* Initialization of the Static Memory Controller for Chip Select 3 */
-        at91_sys_write(AT91_SMC_CSR(3),
+        at91_ramc_write(0, AT91_SMC_CSR(3),
                AT91_SMC_DBW_16  |      /* 16 bit */
                AT91_SMC_WSEN    |
                AT91_SMC_NWS_(5) |      /* wait states */
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index d75a4a2ad9c2..bb9914582013 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -38,6 +38,7 @@
 #include <mach/board.h>
 #include <mach/cpu.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index ab024fa11d5c..59e35dd14863 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -39,6 +39,7 @@
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 782f37946af5..9083df04e7ed 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -41,6 +41,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index ef7c12a92246..11cbaa8946fe 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -41,6 +41,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 4770db08e5a6..3c2e3fcc310c 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -145,11 +145,11 @@ static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
                /* Audio codec */
                I2C_BOARD_INFO("tlv320aic23", 0x1a),
        },
-        {
+};
+static struct i2c_board_info __initdata snapper9260_i2c_isl1208 = {
                /* RTC */
                I2C_BOARD_INFO("isl1208", 0x6f),
-                .irq = gpio_to_irq(AT91_PIN_PA31),
-        },
 };
 static void __init snapper9260_add_device_nand(void)
@@ -163,6 +163,10 @@ static void __init snapper9260_board_init(void)
 {
        at91_add_device_i2c(snapper9260_i2c_devices,
                            ARRAY_SIZE(snapper9260_i2c_devices));
+        snapper9260_i2c_isl1208.irq = gpio_to_irq(AT91_PIN_PA31);
+        i2c_register_board_info(0, &snapper9260_i2c_isl1208, 1);
        at91_add_device_serial();
        at91_add_device_usbh(&snapper9260_usbh_data);
        at91_add_device_udc(&snapper9260_udc_data);
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index bbd553e1cd93..52f460768f71 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -45,6 +45,7 @@
 #include <mach/hardware.h>
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/at91_ramc.h>
 #include <mach/cpu.h>
 #include "generic.h"
@@ -393,7 +394,7 @@ static void yl9200_init_video(void)
        at91_set_A_periph(AT91_PIN_PC6, 0);
        /* Initialization of the Static Memory Controller for Chip Select 2 */
-        at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16         /* 16 bit */
+        at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16             /* 16 bit */
                        | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4)    /* wait states */
                        | AT91_SMC_TDF_(0x100)                  /* float time */
        );
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index a5291e0e7004..be51ca7f694d 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -28,9 +28,12 @@
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
+#include <asm/proc-fns.h>
 #include "clock.h"
 #include "generic.h"
+void __iomem *at91_pmc_base;
 /*
 * There's a lot more which can be done with clocks, including cpufreq
@@ -123,11 +126,11 @@ static void pllb_mode(struct clk *clk, int is_on)
                value = 0;
        // REVISIT: Add work-around for AT91RM9200 Errata #26 ?
-        at91_sys_write(AT91_CKGR_PLLBR, value);
+        at91_pmc_write(AT91_CKGR_PLLBR, value);
        do {
                cpu_relax();
-        } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
+        } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
 }
 static struct clk pllb = {
@@ -142,24 +145,24 @@ static struct clk pllb = {
 static void pmc_sys_mode(struct clk *clk, int is_on)
 {
        if (is_on)
-                at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
+                at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
        else
-                at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
+                at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
 }
 static void pmc_uckr_mode(struct clk *clk, int is_on)
 {
-        unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
+        unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
        if (is_on) {
                is_on = AT91_PMC_LOCKU;
-                at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
+                at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
        } else
-                at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
+                at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
        do {
                cpu_relax();
-        } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
+        } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
 }
 /* USB function clocks (PLLB must be 48 MHz) */
@@ -195,9 +198,9 @@ struct clk mck = {
 static void pmc_periph_mode(struct clk *clk, int is_on)
 {
        if (is_on)
-                at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
+                at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
        else
-                at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
+                at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
 }
 static struct clk __init *at91_css_to_clk(unsigned long css)
@@ -357,10 +360,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
                if (actual && actual <= rate) {
                        u32     pckr;
-                        pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
+                        pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
                        pckr &= css_mask;       /* keep clock selection */
                        pckr |= prescale << prescale_offset;
-                        at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
+                        at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
                        clk->rate_hz = actual;
                        break;
                }
@@ -394,7 +397,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
        clk->rate_hz = parent->rate_hz;
        clk->parent = parent;
-        at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
+        at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
        spin_unlock_irqrestore(&clk_lock, flags);
        return 0;
@@ -413,7 +416,7 @@ static void __init init_programmable_clock(struct clk *clk)
        else
                css_mask = AT91_PMC_CSS;
-        pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
+        pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
        parent = at91_css_to_clk(pckr & css_mask);
        clk->parent = parent;
        clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
@@ -430,19 +433,24 @@ static int at91_clk_show(struct seq_file *s, void *unused)
        u32             scsr, pcsr, uckr = 0, sr;
        struct clk      *clk;
-        seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
+        scsr = at91_pmc_read(AT91_PMC_SCSR);
-        seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
+        pcsr = at91_pmc_read(AT91_PMC_PCSR);
-        seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
+        sr = at91_pmc_read(AT91_PMC_SR);
-        seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
+        seq_printf(s, "SCSR = %8x\n", scsr);
-        seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
+        seq_printf(s, "PCSR = %8x\n", pcsr);
+        seq_printf(s, "MOR  = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
+        seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
+        seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
        if (cpu_has_pllb())
-                seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
+                seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
-        if (cpu_has_utmi())
+        if (cpu_has_utmi()) {
-                seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
+                uckr = at91_pmc_read(AT91_CKGR_UCKR);
-        seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
+                seq_printf(s, "UCKR = %8x\n", uckr);
+        }
+        seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
        if (cpu_has_upll())
-                seq_printf(s, "USB  = %8x\n", at91_sys_read(AT91_PMC_USB));
+                seq_printf(s, "USB  = %8x\n", at91_pmc_read(AT91_PMC_USB));
-        seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
+        seq_printf(s, "SR   = %8x\n", sr);
        seq_printf(s, "\n");
@@ -630,14 +638,14 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
        if (cpu_is_at91rm9200()) {
                uhpck.pmc_mask = AT91RM9200_PMC_UHP;
                udpck.pmc_mask = AT91RM9200_PMC_UDP;
-                at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
+                at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
                   cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
                   cpu_is_at91sam9g10()) {
                uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                udpck.pmc_mask = AT91SAM926x_PMC_UDP;
        }
-        at91_sys_write(AT91_CKGR_PLLBR, 0);
+        at91_pmc_write(AT91_CKGR_PLLBR, 0);
        udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
        uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
@@ -654,13 +662,13 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
        /* Setup divider by 10 to reach 48 MHz */
        usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
-        at91_sys_write(AT91_PMC_USB, usbr);
+        at91_pmc_write(AT91_PMC_USB, usbr);
        /* Now set uhpck values */
        uhpck.parent = &utmi_clk;
        uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
        uhpck.rate_hz = utmi_clk.rate_hz;
-        uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
+        uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
 }
 int __init at91_clock_init(unsigned long main_clock)
@@ -669,6 +677,10 @@ int __init at91_clock_init(unsigned long main_clock)
        int i;
        int pll_overclock = false;
+        at91_pmc_base = ioremap(AT91_PMC, 256);
+        if (!at91_pmc_base)
+                panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
        /*
         * When the bootloader initialized the main oscillator correctly,
         * there's no problem using the cycle counter.  But if it didn't,
@@ -677,14 +689,14 @@ int __init at91_clock_init(unsigned long main_clock)
         */
        if (!main_clock) {
                do {
-                        tmp = at91_sys_read(AT91_CKGR_MCFR);
+                        tmp = at91_pmc_read(AT91_CKGR_MCFR);
                } while (!(tmp & AT91_PMC_MAINRDY));
                main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
        }
        main_clk.rate_hz = main_clock;
        /* report if PLLA is more than mildly overclocked */
-        plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
+        plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
        if (cpu_has_300M_plla()) {
                if (plla.rate_hz > 300000000)
                        pll_overclock = true;
@@ -699,7 +711,7 @@ int __init at91_clock_init(unsigned long main_clock)
                pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
        if (cpu_has_plladiv2()) {
-                mckr = at91_sys_read(AT91_PMC_MCKR);
+                mckr = at91_pmc_read(AT91_PMC_MCKR);
                plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));      /* plla divisor by 2 */
        }
@@ -739,7 +751,7 @@ int __init at91_clock_init(unsigned long main_clock)
         * MCK and CPU derive from one of those primary clocks.
         * For now, assume this parentage won't change.
         */
-        mckr = at91_sys_read(AT91_PMC_MCKR);
+        mckr = at91_pmc_read(AT91_PMC_MCKR);
        mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
        freq = mck.parent->rate_hz;
        freq /= pmc_prescaler_divider(mckr);                                    /* prescale */
@@ -812,9 +824,15 @@ static int __init at91_clock_reset(void)
                pr_debug("Clocks: disable unused %s\n", clk->name);
        }
-        at91_sys_write(AT91_PMC_PCDR, pcdr);
+        at91_pmc_write(AT91_PMC_PCDR, pcdr);
-        at91_sys_write(AT91_PMC_SCDR, scdr);
+        at91_pmc_write(AT91_PMC_SCDR, scdr);
        return 0;
 }
 late_initcall(at91_clock_reset);
+void at91sam9_idle(void)
+{
+        at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
+        cpu_do_idle();
+}
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 7e8280e798c1..459f01a4a546 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -9,6 +9,7 @@
 */
 #include <linux/clkdev.h>
+#include <linux/of.h>
 /* Map io */
 extern void __init at91_map_io(void);
@@ -25,9 +26,13 @@ extern void __init at91_init_irq_default(void);
 extern void __init at91_init_interrupts(unsigned int priority[]);
 extern void __init at91x40_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[]);
+extern int  __init at91_aic_of_init(struct device_node *node,
+                                    struct device_node *parent);
 /* Timer */
 struct sys_timer;
+extern void at91rm9200_ioremap_st(u32 addr);
 extern struct sys_timer at91rm9200_timer;
 extern void at91sam926x_ioremap_pit(u32 addr);
 extern struct sys_timer at91sam926x_timer;
@@ -56,6 +61,9 @@ struct device;
 extern void at91_irq_suspend(void);
 extern void at91_irq_resume(void);
+/* idle */
+extern void at91sam9_idle(void);
 /* reset */
 extern void at91_ioremap_rstc(u32 base_addr);
 extern void at91sam9_alt_restart(char, const char *);
@@ -64,6 +72,12 @@ extern void at91sam9g45_restart(char, const char *);
 /* shutdown */
 extern void at91_ioremap_shdwc(u32 base_addr);
+/* Matrix */
+extern void at91_ioremap_matrix(u32 base_addr);
+/* Ram Controler */
+extern void at91_ioremap_ramc(int id, u32 addr, u32 size);
 /* GPIO */
 #define AT91RM9200_PQFP         3       /* AT91RM9200 PQFP package has 3 banks */
 #define AT91RM9200_BGA          4       /* AT91RM9200 BGA package has 4 banks */
@@ -74,5 +88,7 @@ struct at91_gpio_bank {
 };
 extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
 extern void __init at91_gpio_irq_setup(void);
+extern int  __init at91_gpio_of_irq_setup(struct device_node *node,
+                                          struct device_node *parent);
 extern int at91_extern_irq;
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 74d6783eeabb..325837a264c9 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -11,6 +11,7 @@
 #include <linux/clk.h>
 #include <linux/errno.h>
+#include <linux/device.h>
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
@@ -20,6 +21,10 @@
 #include <linux/list.h>
 #include <linux/module.h>
 #include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_gpio.h>
 #include <mach/hardware.h>
 #include <mach/at91_pio.h>
@@ -29,9 +34,12 @@
 struct at91_gpio_chip {
        struct gpio_chip        chip;
        struct at91_gpio_chip   *next;          /* Bank sharing same clock */
-        int                     id;             /* ID of register bank */
+        int                     pioc_hwirq;     /* PIO bank interrupt identifier on AIC */
-        void __iomem            *regbase;       /* Base of register bank */
+        int                     pioc_virq;      /* PIO bank Linux virtual interrupt */
+        int                     pioc_idx;       /* PIO bank index */
+        void __iomem            *regbase;       /* PIO bank virtual address */
        struct clk              *clock;         /* associated clock */
+        struct irq_domain       *domain;        /* associated irq domain */
 };
 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
@@ -43,8 +51,9 @@ static int at91_gpiolib_direction_output(struct gpio_chip *chip,
                                         unsigned offset, int val);
 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
                                        unsigned offset);
+static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
-#define AT91_GPIO_CHIP(name, base_gpio, nr_gpio)                        \
+#define AT91_GPIO_CHIP(name, nr_gpio)                                   \
        {                                                               \
                .chip = {                                               \
                        .label            = name,                       \
@@ -53,20 +62,28 @@ static int at91_gpiolib_direction_input(struct gpio_chip *chip,
                        .get              = at91_gpiolib_get,           \
                        .set              = at91_gpiolib_set,           \
                        .dbg_show         = at91_gpiolib_dbg_show,      \
-                        .base             = base_gpio,                  \
+                        .to_irq           = at91_gpiolib_to_irq,        \
                        .ngpio            = nr_gpio,                    \
                },                                                      \
        }
 static struct at91_gpio_chip gpio_chip[] = {
-        AT91_GPIO_CHIP("pioA", 0x00, 32),
+        AT91_GPIO_CHIP("pioA", 32),
-        AT91_GPIO_CHIP("pioB", 0x20, 32),
+        AT91_GPIO_CHIP("pioB", 32),
-        AT91_GPIO_CHIP("pioC", 0x40, 32),
+        AT91_GPIO_CHIP("pioC", 32),
-        AT91_GPIO_CHIP("pioD", 0x60, 32),
+        AT91_GPIO_CHIP("pioD", 32),
-        AT91_GPIO_CHIP("pioE", 0x80, 32),
+        AT91_GPIO_CHIP("pioE", 32),
 };
 static int gpio_banks;
+static unsigned long at91_gpio_caps;
+/* All PIO controllers support PIO3 features */
+#define AT91_GPIO_CAP_PIO3      (1 <<  0)
+#define has_pio3()      (at91_gpio_caps & AT91_GPIO_CAP_PIO3)
+/*--------------------------------------------------------------------------*/
 static inline void __iomem *pin_to_controller(unsigned pin)
 {
@@ -83,6 +100,25 @@ static inline unsigned pin_to_mask(unsigned pin)
 }
+static char peripheral_function(void __iomem *pio, unsigned mask)
+{
+        char    ret = 'X';
+        u8      select;
+        if (pio) {
+                if (has_pio3()) {
+                        select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
+                        select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);
+                        ret = 'A' + select;
+                } else {
+                        ret = __raw_readl(pio + PIO_ABSR) & mask ?
+                                                        'B' : 'A';
+                }
+        }
+        return ret;
+}
 /*--------------------------------------------------------------------------*/
 /* Not all hardware capabilities are exposed through these calls; they
@@ -130,7 +166,14 @@ int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
        __raw_writel(mask, pio + PIO_IDR);
        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-        __raw_writel(mask, pio + PIO_ASR);
+        if (has_pio3()) {
+                __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
+                                                        pio + PIO_ABCDSR1);
+                __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
+                                                        pio + PIO_ABCDSR2);
+        } else {
+                __raw_writel(mask, pio + PIO_ASR);
+        }
        __raw_writel(mask, pio + PIO_PDR);
        return 0;
 }
@@ -150,7 +193,14 @@ int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
        __raw_writel(mask, pio + PIO_IDR);
        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
-        __raw_writel(mask, pio + PIO_BSR);
+        if (has_pio3()) {
+                __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
+                                                        pio + PIO_ABCDSR1);
+                __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
+                                                        pio + PIO_ABCDSR2);
+        } else {
+                __raw_writel(mask, pio + PIO_BSR);
+        }
        __raw_writel(mask, pio + PIO_PDR);
        return 0;
 }
@@ -158,8 +208,50 @@ EXPORT_SYMBOL(at91_set_B_periph);
 /*
- * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
+ * mux the pin to the "C" internal peripheral role.
- * configure it for an input.
+ */
+int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+        if (!pio || !has_pio3())
+                return -EINVAL;
+        __raw_writel(mask, pio + PIO_IDR);
+        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+        __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
+        __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+        __raw_writel(mask, pio + PIO_PDR);
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_C_periph);
+/*
+ * mux the pin to the "D" internal peripheral role.
+ */
+int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+        if (!pio || !has_pio3())
+                return -EINVAL;
+        __raw_writel(mask, pio + PIO_IDR);
+        __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
+        __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
+        __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
+        __raw_writel(mask, pio + PIO_PDR);
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_D_periph);
+/*
+ * mux the pin to the gpio controller (instead of "A", "B", "C"
+ * or "D" peripheral), and configure it for an input.
 */
 int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
 {
@@ -179,8 +271,8 @@ EXPORT_SYMBOL(at91_set_gpio_input);
 /*
- * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
+ * mux the pin to the gpio controller (instead of "A", "B", "C"
- * and configure it for an output.
+ * or "D" peripheral), and configure it for an output.
 */
 int __init_or_module at91_set_gpio_output(unsigned pin, int value)
 {
@@ -210,12 +302,37 @@ int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
        if (!pio)
                return -EINVAL;
+        if (has_pio3() && is_on)
+                __raw_writel(mask, pio + PIO_IFSCDR);
        __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
        return 0;
 }
 EXPORT_SYMBOL(at91_set_deglitch);
 /*
+ * enable/disable the debounce filter;
+ */
+int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+        if (!pio || !has_pio3())
+                return -EINVAL;
+        if (is_on) {
+                __raw_writel(mask, pio + PIO_IFSCER);
+                __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
+                __raw_writel(mask, pio + PIO_IFER);
+        } else {
+                __raw_writel(mask, pio + PIO_IFDR);
+        }
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_debounce);
+/*
 * enable/disable the multi-driver; This is only valid for output and
 * allows the output pin to run as an open collector output.
 */
@@ -233,6 +350,41 @@ int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
 EXPORT_SYMBOL(at91_set_multi_drive);
 /*
+ * enable/disable the pull-down.
+ * If pull-up already enabled while calling the function, we disable it.
+ */
+int __init_or_module at91_set_pulldown(unsigned pin, int is_on)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+        if (!pio || !has_pio3())
+                return -EINVAL;
+        /* Disable pull-up anyway */
+        __raw_writel(mask, pio + PIO_PUDR);
+        __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
+        return 0;
+}
+EXPORT_SYMBOL(at91_set_pulldown);
+/*
+ * disable Schmitt trigger
+ */
+int __init_or_module at91_disable_schmitt_trig(unsigned pin)
+{
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
+        if (!pio || !has_pio3())
+                return -EINVAL;
+        __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
+        return 0;
+}
+EXPORT_SYMBOL(at91_disable_schmitt_trig);
+/*
 * assuming the pin is muxed as a gpio output, set its value.
 */
 int at91_set_gpio_value(unsigned pin, int value)
@@ -273,9 +425,9 @@ static u32 backups[MAX_GPIO_BANKS];
 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
 {
-        unsigned        pin = irq_to_gpio(d->irq);
+        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
-        unsigned        mask = pin_to_mask(pin);
+        unsigned        mask = 1 << d->hwirq;
-        unsigned        bank = pin / 32;
+        unsigned        bank = at91_gpio->pioc_idx;
        if (unlikely(bank >= MAX_GPIO_BANKS))
                return -EINVAL;
@@ -285,7 +437,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
        else
                wakeups[bank] &= ~mask;
-        irq_set_irq_wake(gpio_chip[bank].id, state);
+        irq_set_irq_wake(at91_gpio->pioc_virq, state);
        return 0;
 }
@@ -301,9 +453,10 @@ void at91_gpio_suspend(void)
                __raw_writel(backups[i], pio + PIO_IDR);
                __raw_writel(wakeups[i], pio + PIO_IER);
-                if (!wakeups[i])
+                if (!wakeups[i]) {
+                        clk_unprepare(gpio_chip[i].clock);
                        clk_disable(gpio_chip[i].clock);
-                else {
+                } else {
 #ifdef CONFIG_PM_DEBUG
                        printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
 #endif
@@ -318,8 +471,10 @@ void at91_gpio_resume(void)
        for (i = 0; i < gpio_banks; i++) {
                void __iomem    *pio = gpio_chip[i].regbase;
-                if (!wakeups[i])
+                if (!wakeups[i]) {
-                        clk_enable(gpio_chip[i].clock);
+                        if (clk_prepare(gpio_chip[i].clock) == 0)
+                                clk_enable(gpio_chip[i].clock);
+                }
                __raw_writel(wakeups[i], pio + PIO_IDR);
                __raw_writel(backups[i], pio + PIO_IER);
@@ -335,7 +490,10 @@ void at91_gpio_resume(void)
 * To use any AT91_PIN_* as an externally triggered IRQ, first call
 * at91_set_gpio_input() then maybe enable its glitch filter.
 * Then just request_irq() with the pin ID; it works like any ARM IRQ
- * handler, though it always triggers on rising and falling edges.
+ * handler.
+ * First implementation always triggers on rising and falling edges
+ * whereas the newer PIO3 can be additionally configured to trigger on
+ * level, edge with any polarity.
 *
 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
 * configuring them with at91_set_a_periph() or at91_set_b_periph().
@@ -344,9 +502,9 @@ void at91_gpio_resume(void)
 static void gpio_irq_mask(struct irq_data *d)
 {
-        unsigned        pin = irq_to_gpio(d->irq);
+        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
-        void __iomem    *pio = pin_to_controller(pin);
+        void __iomem    *pio = at91_gpio->regbase;
-        unsigned        mask = pin_to_mask(pin);
+        unsigned        mask = 1 << d->hwirq;
        if (pio)
                __raw_writel(mask, pio + PIO_IDR);
@@ -354,9 +512,9 @@ static void gpio_irq_mask(struct irq_data *d)
 static void gpio_irq_unmask(struct irq_data *d)
 {
-        unsigned        pin = irq_to_gpio(d->irq);
+        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
-        void __iomem    *pio = pin_to_controller(pin);
+        void __iomem    *pio = at91_gpio->regbase;
-        unsigned        mask = pin_to_mask(pin);
+        unsigned        mask = 1 << d->hwirq;
        if (pio)
                __raw_writel(mask, pio + PIO_IER);
@@ -373,23 +531,66 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
        }
 }
+/* Alternate irq type for PIO3 support */
+static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
+{
+        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
+        void __iomem    *pio = at91_gpio->regbase;
+        unsigned        mask = 1 << d->hwirq;
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                __raw_writel(mask, pio + PIO_ESR);
+                __raw_writel(mask, pio + PIO_REHLSR);
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                __raw_writel(mask, pio + PIO_ESR);
+                __raw_writel(mask, pio + PIO_FELLSR);
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                __raw_writel(mask, pio + PIO_LSR);
+                __raw_writel(mask, pio + PIO_FELLSR);
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                __raw_writel(mask, pio + PIO_LSR);
+                __raw_writel(mask, pio + PIO_REHLSR);
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                /*
+                 * disable additional interrupt modes:
+                 * fall back to default behavior
+                 */
+                __raw_writel(mask, pio + PIO_AIMDR);
+                return 0;
+        case IRQ_TYPE_NONE:
+        default:
+                pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
+                return -EINVAL;
+        }
+        /* enable additional interrupt modes */
+        __raw_writel(mask, pio + PIO_AIMER);
+        return 0;
+}
 static struct irq_chip gpio_irqchip = {
        .name           = "GPIO",
        .irq_disable    = gpio_irq_mask,
        .irq_mask       = gpio_irq_mask,
        .irq_unmask     = gpio_irq_unmask,
-        .irq_set_type   = gpio_irq_type,
+        /* .irq_set_type is set dynamically */
        .irq_set_wake   = gpio_irq_set_wake,
 };
 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-        unsigned        irq_pin;
        struct irq_data *idata = irq_desc_get_irq_data(desc);
        struct irq_chip *chip = irq_data_get_irq_chip(idata);
        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
        void __iomem    *pio = at91_gpio->regbase;
-        u32             isr;
+        unsigned long   isr;
+        int             n;
        /* temporarily mask (level sensitive) parent IRQ */
        chip->irq_ack(idata);
@@ -407,13 +608,10 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                        continue;
                }
-                irq_pin = gpio_to_irq(at91_gpio->chip.base);
+                n = find_first_bit(&isr, BITS_PER_LONG);
+                while (n < BITS_PER_LONG) {
-                while (isr) {
+                        generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
-                        if (isr & 1)
+                        n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
-                                generic_handle_irq(irq_pin);
-                        irq_pin++;
-                        isr >>= 1;
                }
        }
        chip->irq_unmask(idata);
@@ -424,6 +622,33 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 #ifdef CONFIG_DEBUG_FS
+static void gpio_printf(struct seq_file *s, void __iomem *pio, unsigned mask)
+{
+        char    *trigger = NULL;
+        char    *polarity = NULL;
+        if (__raw_readl(pio + PIO_IMR) & mask) {
+                if (!has_pio3() || !(__raw_readl(pio + PIO_AIMMR) & mask )) {
+                        trigger = "edge";
+                        polarity = "both";
+                } else {
+                        if (__raw_readl(pio + PIO_ELSR) & mask) {
+                                trigger = "level";
+                                polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
+                                        "high" : "low";
+                        } else {
+                                trigger = "edge";
+                                polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
+                                                "rising" : "falling";
+                        }
+                }
+                seq_printf(s, "IRQ:%s-%s\t", trigger, polarity);
+        } else {
+                seq_printf(s, "GPIO:%s\t\t",
+                                __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
+        }
+}
 static int at91_gpio_show(struct seq_file *s, void *unused)
 {
        int bank, j;
@@ -431,7 +656,7 @@ static int at91_gpio_show(struct seq_file *s, void *unused)
        /* print heading */
        seq_printf(s, "Pin\t");
        for (bank = 0; bank < gpio_banks; bank++) {
-                seq_printf(s, "PIO%c\t", 'A' + bank);
+                seq_printf(s, "PIO%c\t\t", 'A' + bank);
        };
        seq_printf(s, "\n\n");
@@ -445,11 +670,10 @@ static int at91_gpio_show(struct seq_file *s, void *unused)
                        unsigned        mask = pin_to_mask(pin);
                        if (__raw_readl(pio + PIO_PSR) & mask)
-                                seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
+                                gpio_printf(s, pio, mask);
                        else
-                                seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A");
+                                seq_printf(s, "%c\t\t",
+                                                peripheral_function(pio, mask));
-                        seq_printf(s, "\t");
                }
                seq_printf(s, "\n");
@@ -488,46 +712,152 @@ postcore_initcall(at91_gpio_debugfs_init);
 */
 static struct lock_class_key gpio_lock_class;
+#if defined(CONFIG_OF)
+static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
+                                                        irq_hw_number_t hw)
+{
+        struct at91_gpio_chip   *at91_gpio = h->host_data;
+        irq_set_lockdep_class(virq, &gpio_lock_class);
+        /*
+         * Can use the "simple" and not "edge" handler since it's
+         * shorter, and the AIC handles interrupts sanely.
+         */
+        irq_set_chip_and_handler(virq, &gpio_irqchip,
+                                 handle_simple_irq);
+        set_irq_flags(virq, IRQF_VALID);
+        irq_set_chip_data(virq, at91_gpio);
+        return 0;
+}
+static struct irq_domain_ops at91_gpio_ops = {
+        .map    = at91_gpio_irq_map,
+        .xlate  = irq_domain_xlate_twocell,
+};
+int __init at91_gpio_of_irq_setup(struct device_node *node,
+                                     struct device_node *parent)
+{
+        struct at91_gpio_chip   *prev = NULL;
+        int                     alias_idx = of_alias_get_id(node, "gpio");
+        struct at91_gpio_chip   *at91_gpio = &gpio_chip[alias_idx];
+        /* Setup proper .irq_set_type function */
+        if (has_pio3())
+                gpio_irqchip.irq_set_type = alt_gpio_irq_type;
+        else
+                gpio_irqchip.irq_set_type = gpio_irq_type;
+        /* Disable irqs of this PIO controller */
+        __raw_writel(~0, at91_gpio->regbase + PIO_IDR);
+        /* Setup irq domain */
+        at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
+                                                &at91_gpio_ops, at91_gpio);
+        if (!at91_gpio->domain)
+                panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
+                        at91_gpio->pioc_idx);
+        /* Setup chained handler */
+        if (at91_gpio->pioc_idx)
+                prev = &gpio_chip[at91_gpio->pioc_idx - 1];
+        /* The toplevel handler handles one bank of GPIOs, except
+         * on some SoC it can handles up to three...
+         * We only set up the handler for the first of the list.
+         */
+        if (prev && prev->next == at91_gpio)
+                return 0;
+        at91_gpio->pioc_virq = irq_create_mapping(irq_find_host(parent),
+                                                        at91_gpio->pioc_hwirq);
+        irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
+        irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
+        return 0;
+}
+#else
+int __init at91_gpio_of_irq_setup(struct device_node *node,
+                                     struct device_node *parent)
+{
+        return -EINVAL;
+}
+#endif
+/*
+ * irqdomain initialization: pile up irqdomains on top of AIC range
+ */
+static void __init at91_gpio_irqdomain(struct at91_gpio_chip *at91_gpio)
+{
+        int irq_base;
+        irq_base = irq_alloc_descs(-1, 0, at91_gpio->chip.ngpio, 0);
+        if (irq_base < 0)
+                panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n",
+                        at91_gpio->pioc_idx, irq_base);
+        at91_gpio->domain = irq_domain_add_legacy(NULL, at91_gpio->chip.ngpio,
+                                                  irq_base, 0,
+                                                  &irq_domain_simple_ops, NULL);
+        if (!at91_gpio->domain)
+                panic("at91_gpio.%d: couldn't allocate irq domain.\n",
+                        at91_gpio->pioc_idx);
+}
 /*
 * Called from the processor-specific init to enable GPIO interrupt support.
 */
 void __init at91_gpio_irq_setup(void)
 {
-        unsigned                pioc, irq = gpio_to_irq(0);
+        unsigned                pioc;
+        int                     gpio_irqnbr = 0;
        struct at91_gpio_chip   *this, *prev;
+        /* Setup proper .irq_set_type function */
+        if (has_pio3())
+                gpio_irqchip.irq_set_type = alt_gpio_irq_type;
+        else
+                gpio_irqchip.irq_set_type = gpio_irq_type;
        for (pioc = 0, this = gpio_chip, prev = NULL;
                        pioc++ < gpio_banks;
                        prev = this, this++) {
-                unsigned        id = this->id;
+                int offset;
-                unsigned        i;
                __raw_writel(~0, this->regbase + PIO_IDR);
-                for (i = 0, irq = gpio_to_irq(this->chip.base); i < 32;
+                /* setup irq domain for this GPIO controller */
-                     i++, irq++) {
+                at91_gpio_irqdomain(this);
-                        irq_set_lockdep_class(irq, &gpio_lock_class);
+                for (offset = 0; offset < this->chip.ngpio; offset++) {
+                        unsigned int virq = irq_find_mapping(this->domain, offset);
+                        irq_set_lockdep_class(virq, &gpio_lock_class);
                        /*
                         * Can use the "simple" and not "edge" handler since it's
                         * shorter, and the AIC handles interrupts sanely.
                         */
-                        irq_set_chip_and_handler(irq, &gpio_irqchip,
+                        irq_set_chip_and_handler(virq, &gpio_irqchip,
                                                 handle_simple_irq);
-                        set_irq_flags(irq, IRQF_VALID);
+                        set_irq_flags(virq, IRQF_VALID);
+                        irq_set_chip_data(virq, this);
+                        gpio_irqnbr++;
                }
                /* The toplevel handler handles one bank of GPIOs, except
-                 * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in
+                 * on some SoC it can handles up to three...
-                 * the list, so we only set up that handler.
+                 * We only set up the handler for the first of the list.
                 */
                if (prev && prev->next == this)
                        continue;
-                irq_set_chip_data(id, this);
+                this->pioc_virq = irq_create_mapping(NULL, this->pioc_hwirq);
-                irq_set_chained_handler(id, gpio_irq_handler);
+                irq_set_chip_data(this->pioc_virq, this);
+                irq_set_chained_handler(this->pioc_virq, gpio_irq_handler);
        }
-        pr_info("AT91: %d gpio irqs in %d banks\n", irq - gpio_to_irq(0), gpio_banks);
+        pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks);
 }
 /* gpiolib support */
@@ -593,48 +923,175 @@ static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
                                           at91_get_gpio_value(pin) ?
                                           "set" : "clear");
                        else
-                                seq_printf(s, "[periph %s]\n",
+                                seq_printf(s, "[periph %c]\n",
-                                           __raw_readl(pio + PIO_ABSR) &
+                                           peripheral_function(pio, mask));
-                                           mask ? "B" : "A");
                }
        }
 }
+static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+        int virq;
+        if (offset < chip->ngpio)
+                virq = irq_create_mapping(at91_gpio->domain, offset);
+        else
+                virq = -ENXIO;
+        dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
+                                chip->label, offset + chip->base, virq);
+        return virq;
+}
+static int __init at91_gpio_setup_clk(int idx)
+{
+        struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
+        /* retreive PIO controller's clock */
+        at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
+        if (IS_ERR(at91_gpio->clock)) {
+                pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx);
+                goto err;
+        }
+        if (clk_prepare(at91_gpio->clock))
+                goto clk_prep_err;
+        /* enable PIO controller's clock */
+        if (clk_enable(at91_gpio->clock)) {
+                pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx);
+                goto clk_err;
+        }
+        return 0;
+clk_err:
+        clk_unprepare(at91_gpio->clock);
+clk_prep_err:
+        clk_put(at91_gpio->clock);
+err:
+        return -EINVAL;
+}
+#ifdef CONFIG_OF_GPIO
+static void __init of_at91_gpio_init_one(struct device_node *np)
+{
+        int alias_idx;
+        struct at91_gpio_chip *at91_gpio;
+        if (!np)
+                return;
+        alias_idx = of_alias_get_id(np, "gpio");
+        if (alias_idx >= MAX_GPIO_BANKS) {
+                pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n",
+                                                alias_idx, MAX_GPIO_BANKS);
+                return;
+        }
+        at91_gpio = &gpio_chip[alias_idx];
+        at91_gpio->chip.base = alias_idx * at91_gpio->chip.ngpio;
+        at91_gpio->regbase = of_iomap(np, 0);
+        if (!at91_gpio->regbase) {
+                pr_err("at91_gpio.%d, failed to map registers, ignoring.\n",
+                                                                alias_idx);
+                return;
+        }
+        /* Get the interrupts property */
+        if (of_property_read_u32(np, "interrupts", &at91_gpio->pioc_hwirq)) {
+                pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n",
+                                                                alias_idx);
+                goto ioremap_err;
+        }
+        /* Get capabilities from compatibility property */
+        if (of_device_is_compatible(np, "atmel,at91sam9x5-gpio"))
+                at91_gpio_caps |= AT91_GPIO_CAP_PIO3;
+        /* Setup clock */
+        if (at91_gpio_setup_clk(alias_idx))
+                goto ioremap_err;
+        at91_gpio->chip.of_node = np;
+        gpio_banks = max(gpio_banks, alias_idx + 1);
+        at91_gpio->pioc_idx = alias_idx;
+        return;
+ioremap_err:
+        iounmap(at91_gpio->regbase);
+}
+static int __init of_at91_gpio_init(void)
+{
+        struct device_node *np = NULL;
+        /*
+         * This isn't ideal, but it gets things hooked up until this
+         * driver is converted into a platform_device
+         */
+        for_each_compatible_node(np, NULL, "atmel,at91rm9200-gpio")
+                of_at91_gpio_init_one(np);
+        return gpio_banks > 0 ? 0 : -EINVAL;
+}
+#else
+static int __init of_at91_gpio_init(void)
+{
+        return -EINVAL;
+}
+#endif
+static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
+{
+        struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
+        at91_gpio->chip.base = idx * at91_gpio->chip.ngpio;
+        at91_gpio->pioc_hwirq = pioc_hwirq;
+        at91_gpio->pioc_idx = idx;
+        at91_gpio->regbase = ioremap(regbase, 512);
+        if (!at91_gpio->regbase) {
+                pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx);
+                return;
+        }
+        if (at91_gpio_setup_clk(idx))
+                goto ioremap_err;
+        gpio_banks = max(gpio_banks, idx + 1);
+        return;
+ioremap_err:
+        iounmap(at91_gpio->regbase);
+}
 /*
 * Called from the processor-specific init to enable GPIO pin support.
 */
 void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
 {
-        unsigned                i;
+        unsigned i;
        struct at91_gpio_chip *at91_gpio, *last = NULL;
        BUG_ON(nr_banks > MAX_GPIO_BANKS);
-        gpio_banks = nr_banks;
+        if (of_at91_gpio_init() < 0) {
+                /* No GPIO controller found in device tree */
+                for (i = 0; i < nr_banks; i++)
+                        at91_gpio_init_one(i, data[i].regbase, data[i].id);
+        }
-        for (i = 0; i < nr_banks; i++) {
+        for (i = 0; i < gpio_banks; i++) {
                at91_gpio = &gpio_chip[i];
-                at91_gpio->id = data[i].id;
+                /*
-                at91_gpio->chip.base = i * 32;
+                 * GPIO controller are grouped on some SoC:
+                 * PIOC, PIOD and PIOE can share the same IRQ line
-                at91_gpio->regbase = ioremap(data[i].regbase, 512);
+                 */
-                if (!at91_gpio->regbase) {
+                if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq)
-                        pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", i);
-                        continue;
-                }
-                at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
-                if (!at91_gpio->clock) {
-                        pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", i);
-                        continue;
-                }
-                /* enable PIO controller's clock */
-                clk_enable(at91_gpio->clock);
-                /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
-                if (last && last->id == at91_gpio->id)
                        last->next = at91_gpio;
                last = at91_gpio;
diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h
new file mode 100644
index 000000000000..02fae9de746b
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_matrix.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2
+ */
+#ifndef __MACH_AT91_MATRIX_H__
+#define __MACH_AT91_MATRIX_H__
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_matrix_base;
+#define at91_matrix_read(field) \
+        __raw_readl(at91_matrix_base + field)
+#define at91_matrix_write(field, value) \
+        __raw_writel(value, at91_matrix_base + field);
+#else
+.extern at91_matrix_base
+#endif
+#endif /* __MACH_AT91_MATRIX_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h
index c6a31bf8a5c6..732b11c37f1a 100644
--- a/arch/arm/mach-at91/include/mach/at91_pio.h
+++ b/arch/arm/mach-at91/include/mach/at91_pio.h
@@ -40,10 +40,35 @@
 #define PIO_PUER        0x64    /* Pull-up Enable Register */
 #define PIO_PUSR        0x68    /* Pull-up Status Register */
 #define PIO_ASR         0x70    /* Peripheral A Select Register */
+#define PIO_ABCDSR1     0x70    /* Peripheral ABCD Select Register 1 [some sam9 only] */
 #define PIO_BSR         0x74    /* Peripheral B Select Register */
+#define PIO_ABCDSR2     0x74    /* Peripheral ABCD Select Register 2 [some sam9 only] */
 #define PIO_ABSR        0x78    /* AB Status Register */
+#define PIO_IFSCDR      0x80    /* Input Filter Slow Clock Disable Register */
+#define PIO_IFSCER      0x84    /* Input Filter Slow Clock Enable Register */
+#define PIO_IFSCSR      0x88    /* Input Filter Slow Clock Status Register */
+#define PIO_SCDR        0x8c    /* Slow Clock Divider Debouncing Register */
+#define         PIO_SCDR_DIV    (0x3fff <<  0)          /* Slow Clock Divider Mask */
+#define PIO_PPDDR       0x90    /* Pad Pull-down Disable Register */
+#define PIO_PPDER       0x94    /* Pad Pull-down Enable Register */
+#define PIO_PPDSR       0x98    /* Pad Pull-down Status Register */
 #define PIO_OWER        0xa0    /* Output Write Enable Register */
 #define PIO_OWDR        0xa4    /* Output Write Disable Register */
 #define PIO_OWSR        0xa8    /* Output Write Status Register */
+#define PIO_AIMER       0xb0    /* Additional Interrupt Modes Enable Register */
+#define PIO_AIMDR       0xb4    /* Additional Interrupt Modes Disable Register */
+#define PIO_AIMMR       0xb8    /* Additional Interrupt Modes Mask Register */
+#define PIO_ESR         0xc0    /* Edge Select Register */
+#define PIO_LSR         0xc4    /* Level Select Register */
+#define PIO_ELSR        0xc8    /* Edge/Level Status Register */
+#define PIO_FELLSR      0xd0    /* Falling Edge/Low Level Select Register */
+#define PIO_REHLSR      0xd4    /* Rising Edge/ High Level Select Register */
+#define PIO_FRLHSR      0xd8    /* Fall/Rise - Low/High Status Register */
+#define PIO_SCHMITT     0x100   /* Schmitt Trigger Register */
+#define ABCDSR_PERIPH_A 0x0
+#define ABCDSR_PERIPH_B 0x1
+#define ABCDSR_PERIPH_C 0x2
+#define ABCDSR_PERIPH_D 0x3
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index f9fdbbe0c53a..36604782a78f 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -16,10 +16,22 @@
 #ifndef AT91_PMC_H
 #define AT91_PMC_H
-#define AT91_PMC_SCER           (AT91_PMC + 0x00)       /* System Clock Enable Register */
+#ifndef __ASSEMBLY__
-#define AT91_PMC_SCDR           (AT91_PMC + 0x04)       /* System Clock Disable Register */
+extern void __iomem *at91_pmc_base;
-#define AT91_PMC_SCSR           (AT91_PMC + 0x08)       /* System Clock Status Register */
+#define at91_pmc_read(field) \
+        __raw_readl(at91_pmc_base + field)
+#define at91_pmc_write(field, value) \
+        __raw_writel(value, at91_pmc_base + field)
+#else
+.extern at91_aic_base
+#endif
+#define AT91_PMC_SCER           0x00                    /* System Clock Enable Register */
+#define AT91_PMC_SCDR           0x04                    /* System Clock Disable Register */
+#define AT91_PMC_SCSR           0x08                    /* System Clock Status Register */
 #define         AT91_PMC_PCK            (1 <<  0)               /* Processor Clock */
 #define         AT91RM9200_PMC_UDP      (1 <<  1)               /* USB Devcice Port Clock [AT91RM9200 only] */
 #define         AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
@@ -34,17 +46,17 @@
 #define         AT91_PMC_HCK0           (1 << 16)               /* AHB Clock (USB host) [AT91SAM9261 only] */
 #define         AT91_PMC_HCK1           (1 << 17)               /* AHB Clock (LCD) [AT91SAM9261 only] */
-#define AT91_PMC_PCER           (AT91_PMC + 0x10)       /* Peripheral Clock Enable Register */
+#define AT91_PMC_PCER           0x10                    /* Peripheral Clock Enable Register */
-#define AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
+#define AT91_PMC_PCDR           0x14                    /* Peripheral Clock Disable Register */
-#define AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
+#define AT91_PMC_PCSR           0x18                    /* Peripheral Clock Status Register */
-#define AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [some SAM9] */
+#define AT91_CKGR_UCKR          0x1C                    /* UTMI Clock Register [some SAM9] */
 #define         AT91_PMC_UPLLEN         (1   << 16)             /* UTMI PLL Enable */
 #define         AT91_PMC_UPLLCOUNT      (0xf << 20)             /* UTMI PLL Start-up Time */
 #define         AT91_PMC_BIASEN         (1   << 24)             /* UTMI BIAS Enable */
 #define         AT91_PMC_BIASCOUNT      (0xf << 28)             /* UTMI BIAS Start-up Time */
-#define AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register [not on SAM9RL] */
+#define AT91_CKGR_MOR           0x20                    /* Main Oscillator Register [not on SAM9RL] */
 #define         AT91_PMC_MOSCEN         (1    <<  0)            /* Main Oscillator Enable */
 #define         AT91_PMC_OSCBYPASS      (1    <<  1)            /* Oscillator Bypass */
 #define         AT91_PMC_MOSCRCEN       (1    <<  3)            /* Main On-Chip RC Oscillator Enable [some SAM9] */
@@ -53,12 +65,12 @@
 #define         AT91_PMC_MOSCSEL        (1    << 24)            /* Main Oscillator Selection [some SAM9] */
 #define         AT91_PMC_CFDEN          (1    << 25)            /* Clock Failure Detector Enable [some SAM9] */
-#define AT91_CKGR_MCFR          (AT91_PMC + 0x24)       /* Main Clock Frequency Register */
+#define AT91_CKGR_MCFR          0x24                    /* Main Clock Frequency Register */
 #define         AT91_PMC_MAINF          (0xffff <<  0)          /* Main Clock Frequency */
 #define         AT91_PMC_MAINRDY        (1      << 16)          /* Main Clock Ready */
-#define AT91_CKGR_PLLAR         (AT91_PMC + 0x28)       /* PLL A Register */
+#define AT91_CKGR_PLLAR         0x28                    /* PLL A Register */
-#define AT91_CKGR_PLLBR         (AT91_PMC + 0x2c)       /* PLL B Register */
+#define AT91_CKGR_PLLBR         0x2c                    /* PLL B Register */
 #define         AT91_PMC_DIV            (0xff  <<  0)           /* Divider */
 #define         AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
 #define         AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
@@ -69,7 +81,7 @@
 #define                 AT91_PMC_USBDIV_4               (2 << 28)
 #define         AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
-#define AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */
+#define AT91_PMC_MCKR           0x30                    /* Master Clock Register */
 #define         AT91_PMC_CSS            (3 <<  0)               /* Master Clock Selection */
 #define                 AT91_PMC_CSS_SLOW               (0 << 0)
 #define                 AT91_PMC_CSS_MAIN               (1 << 0)
@@ -111,27 +123,27 @@
 #define                 AT91_PMC_PLLADIV2_OFF           (0 << 12)
 #define                 AT91_PMC_PLLADIV2_ON            (1 << 12)
-#define AT91_PMC_USB            (AT91_PMC + 0x38)       /* USB Clock Register [some SAM9 only] */
+#define AT91_PMC_USB            0x38                    /* USB Clock Register [some SAM9 only] */
 #define         AT91_PMC_USBS           (0x1 <<  0)             /* USB OHCI Input clock selection */
 #define                 AT91_PMC_USBS_PLLA              (0 << 0)
 #define                 AT91_PMC_USBS_UPLL              (1 << 0)
 #define         AT91_PMC_OHCIUSBDIV     (0xF <<  8)             /* Divider for USB OHCI Clock */
-#define AT91_PMC_SMD            (AT91_PMC + 0x3c)       /* Soft Modem Clock Register [some SAM9 only] */
+#define AT91_PMC_SMD            0x3c                    /* Soft Modem Clock Register [some SAM9 only] */
 #define         AT91_PMC_SMDS           (0x1  <<  0)            /* SMD input clock selection */
 #define         AT91_PMC_SMD_DIV        (0x1f <<  8)            /* SMD input clock divider */
 #define         AT91_PMC_SMDDIV(n)      (((n) <<  8) & AT91_PMC_SMD_DIV)
-#define AT91_PMC_PCKR(n)        (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-N Registers */
+#define AT91_PMC_PCKR(n)        (0x40 + ((n) * 4))      /* Programmable Clock 0-N Registers */
 #define         AT91_PMC_ALT_PCKR_CSS   (0x7 <<  0)             /* Programmable Clock Source Selection [alternate length] */
 #define                 AT91_PMC_CSS_MASTER             (4 << 0)        /* [some SAM9 only] */
 #define         AT91_PMC_CSSMCK         (0x1 <<  8)             /* CSS or Master Clock Selection */
 #define                 AT91_PMC_CSSMCK_CSS             (0 << 8)
 #define                 AT91_PMC_CSSMCK_MCK             (1 << 8)
-#define AT91_PMC_IER            (AT91_PMC + 0x60)       /* Interrupt Enable Register */
+#define AT91_PMC_IER            0x60                    /* Interrupt Enable Register */
-#define AT91_PMC_IDR            (AT91_PMC + 0x64)       /* Interrupt Disable Register */
+#define AT91_PMC_IDR            0x64                    /* Interrupt Disable Register */
-#define AT91_PMC_SR             (AT91_PMC + 0x68)       /* Status Register */
+#define AT91_PMC_SR             0x68                    /* Status Register */
 #define         AT91_PMC_MOSCS          (1 <<  0)               /* MOSCS Flag */
 #define         AT91_PMC_LOCKA          (1 <<  1)               /* PLLA Lock */
 #define         AT91_PMC_LOCKB          (1 <<  2)               /* PLLB Lock */
@@ -144,18 +156,18 @@
 #define         AT91_PMC_MOSCSELS       (1 << 16)               /* Main Oscillator Selection [some SAM9] */
 #define         AT91_PMC_MOSCRCS        (1 << 17)               /* Main On-Chip RC [some SAM9] */
 #define         AT91_PMC_CFDEV          (1 << 18)               /* Clock Failure Detector Event [some SAM9] */
-#define AT91_PMC_IMR            (AT91_PMC + 0x6c)       /* Interrupt Mask Register */
+#define AT91_PMC_IMR            0x6c                    /* Interrupt Mask Register */
-#define AT91_PMC_PROT           (AT91_PMC + 0xe4)       /* Write Protect Mode Register [some SAM9] */
+#define AT91_PMC_PROT           0xe4                    /* Write Protect Mode Register [some SAM9] */
 #define         AT91_PMC_WPEN           (0x1  <<  0)            /* Write Protect Enable */
 #define         AT91_PMC_WPKEY          (0xffffff << 8)         /* Write Protect Key */
 #define         AT91_PMC_PROTKEY        (0x504d43 << 8)         /* Activation Code */
-#define AT91_PMC_WPSR           (AT91_PMC + 0xe8)       /* Write Protect Status Register [some SAM9] */
+#define AT91_PMC_WPSR           0xe8                    /* Write Protect Status Register [some SAM9] */
 #define         AT91_PMC_WPVS           (0x1  <<  0)            /* Write Protect Violation Status */
 #define         AT91_PMC_WPVSRC         (0xffff  <<  8)         /* Write Protect Violation Source */
-#define AT91_PMC_PCR            (AT91_PMC + 0x10c)      /* Peripheral Control Register [some SAM9] */
+#define AT91_PMC_PCR            0x10c                   /* Peripheral Control Register [some SAM9] */
 #define         AT91_PMC_PCR_PID        (0x3f  <<  0)           /* Peripheral ID */
 #define         AT91_PMC_PCR_CMD        (0x1  <<  12)           /* Command */
 #define         AT91_PMC_PCR_DIV        (0x3  <<  16)           /* Divisor Value */
diff --git a/arch/arm/mach-at91/include/mach/at91_ramc.h b/arch/arm/mach-at91/include/mach/at91_ramc.h
new file mode 100644
index 000000000000..d8aeb278614e
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_ramc.h
@@ -0,0 +1,32 @@
+/*
+ * Header file for the Atmel RAM Controller
+ *
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2 only
+ */
+#ifndef __AT91_RAMC_H__
+#define __AT91_RAMC_H__
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_ramc_base[];
+#define at91_ramc_read(id, field) \
+        __raw_readl(at91_ramc_base[id] + field)
+#define at91_ramc_write(id, field, value) \
+        __raw_writel(value, at91_ramc_base[id] + field)
+#else
+.extern at91_ramc_base
+#endif
+#define AT91_MEMCTRL_MC         0
+#define AT91_MEMCTRL_SDRAMC     1
+#define AT91_MEMCTRL_DDRSDR     2
+#include <mach/at91rm9200_sdramc.h>
+#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91sam9_sdramc.h>
+#endif /* __AT91_RAMC_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h
index 8847173e4101..969aac27109f 100644
--- a/arch/arm/mach-at91/include/mach/at91_st.h
+++ b/arch/arm/mach-at91/include/mach/at91_st.h
@@ -16,34 +16,46 @@
 #ifndef AT91_ST_H
 #define AT91_ST_H
-#define AT91_ST_CR              (AT91_ST + 0x00)        /* Control Register */
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_st_base;
+#define at91_st_read(field) \
+        __raw_readl(at91_st_base + field)
+#define at91_st_write(field, value) \
+        __raw_writel(value, at91_st_base + field);
+#else
+.extern at91_st_base
+#endif
+#define AT91_ST_CR              0x00                    /* Control Register */
 #define         AT91_ST_WDRST           (1 << 0)                /* Watchdog Timer Restart */
-#define AT91_ST_PIMR            (AT91_ST + 0x04)        /* Period Interval Mode Register */
+#define AT91_ST_PIMR            0x04                    /* Period Interval Mode Register */
 #define         AT91_ST_PIV             (0xffff <<  0)          /* Period Interval Value */
-#define AT91_ST_WDMR            (AT91_ST + 0x08)        /* Watchdog Mode Register */
+#define AT91_ST_WDMR            0x08                    /* Watchdog Mode Register */
 #define         AT91_ST_WDV             (0xffff <<  0)          /* Watchdog Counter Value */
 #define         AT91_ST_RSTEN           (1      << 16)          /* Reset Enable */
 #define         AT91_ST_EXTEN           (1      << 17)          /* External Signal Assertion Enable */
-#define AT91_ST_RTMR            (AT91_ST + 0x0c)        /* Real-time Mode Register */
+#define AT91_ST_RTMR            0x0c                    /* Real-time Mode Register */
 #define         AT91_ST_RTPRES          (0xffff <<  0)          /* Real-time Prescalar Value */
-#define AT91_ST_SR              (AT91_ST + 0x10)        /* Status Register */
+#define AT91_ST_SR              0x10                    /* Status Register */
 #define         AT91_ST_PITS            (1 << 0)                /* Period Interval Timer Status */
 #define         AT91_ST_WDOVF           (1 << 1)                /* Watchdog Overflow */
 #define         AT91_ST_RTTINC          (1 << 2)                /* Real-time Timer Increment */
 #define         AT91_ST_ALMS            (1 << 3)                /* Alarm Status */
-#define AT91_ST_IER             (AT91_ST + 0x14)        /* Interrupt Enable Register */
+#define AT91_ST_IER             0x14                    /* Interrupt Enable Register */
-#define AT91_ST_IDR             (AT91_ST + 0x18)        /* Interrupt Disable Register */
+#define AT91_ST_IDR             0x18                    /* Interrupt Disable Register */
-#define AT91_ST_IMR             (AT91_ST + 0x1c)        /* Interrupt Mask Register */
+#define AT91_ST_IMR             0x1c                    /* Interrupt Mask Register */
-#define AT91_ST_RTAR            (AT91_ST + 0x20)        /* Real-time Alarm Register */
+#define AT91_ST_RTAR            0x20                    /* Real-time Alarm Register */
 #define         AT91_ST_ALMV            (0xfffff << 0)          /* Alarm Value */
-#define AT91_ST_CRTR            (AT91_ST + 0x24)        /* Current Real-time Register */
+#define AT91_ST_CRTR            0x24                    /* Current Real-time Register */
 #define         AT91_ST_CRTV            (0xfffff << 0)          /* Current Real-Time Value */
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index bacb51141819..603e6aac2a4f 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -77,26 +77,22 @@
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
 */
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)    /* Power Management Controller */
-#define AT91_ST         (0xfffffd00 - AT91_BASE_SYS)    /* System Timer */
-#define AT91_MC         (0xffffff00 - AT91_BASE_SYS)    /* Memory Controllers */
 #define AT91RM9200_BASE_DBGU    AT91_BASE_DBGU0 /* Debug Unit */
 #define AT91RM9200_BASE_PIOA    0xfffff400      /* PIO Controller A */
 #define AT91RM9200_BASE_PIOB    0xfffff600      /* PIO Controller B */
 #define AT91RM9200_BASE_PIOC    0xfffff800      /* PIO Controller C */
 #define AT91RM9200_BASE_PIOD    0xfffffa00      /* PIO Controller D */
+#define AT91RM9200_BASE_ST      0xfffffd00      /* System Timer */
 #define AT91RM9200_BASE_RTC     0xfffffe00      /* Real-Time Clock */
+#define AT91RM9200_BASE_MC      0xffffff00      /* Memory Controllers */
 #define AT91_USART0     AT91RM9200_BASE_US0
 #define AT91_USART1     AT91RM9200_BASE_US1
 #define AT91_USART2     AT91RM9200_BASE_US2
 #define AT91_USART3     AT91RM9200_BASE_US3
-#define AT91_MATRIX     0       /* not supported */
 /*
 * Internal Memory.
 */
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
index d34e4ed89349..aeaadfb452af 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
@@ -17,10 +17,10 @@
 #define AT91RM9200_MC_H
 /* Memory Controller */
-#define AT91_MC_RCR             (AT91_MC + 0x00)        /* MC Remap Control Register */
+#define AT91_MC_RCR             0x00                    /* MC Remap Control Register */
 #define         AT91_MC_RCB             (1 <<  0)               /* Remap Command Bit */
-#define AT91_MC_ASR             (AT91_MC + 0x04)        /* MC Abort Status Register */
+#define AT91_MC_ASR             0x04                    /* MC Abort Status Register */
 #define         AT91_MC_UNADD           (1 <<  0)               /* Undefined Address Abort Status */
 #define         AT91_MC_MISADD          (1 <<  1)               /* Misaligned Address Abort Status */
 #define         AT91_MC_ABTSZ           (3 <<  8)               /* Abort Size Status */
@@ -40,16 +40,16 @@
 #define         AT91_MC_SVMST2          (1 << 26)               /* Saved UHP Abort Source */
 #define         AT91_MC_SVMST3          (1 << 27)               /* Saved EMAC Abort Source */
-#define AT91_MC_AASR            (AT91_MC + 0x08)        /* MC Abort Address Status Register */
+#define AT91_MC_AASR            0x08                    /* MC Abort Address Status Register */
-#define AT91_MC_MPR             (AT91_MC + 0x0c)        /* MC Master Priority Register */
+#define AT91_MC_MPR             0x0c                    /* MC Master Priority Register */
 #define         AT91_MPR_MSTP0          (7 <<  0)               /* ARM920T Priority */
 #define         AT91_MPR_MSTP1          (7 <<  4)               /* PDC Priority */
 #define         AT91_MPR_MSTP2          (7 <<  8)               /* UHP Priority */
 #define         AT91_MPR_MSTP3          (7 << 12)               /* EMAC Priority */
 /* External Bus Interface (EBI) registers */
-#define AT91_EBI_CSA            (AT91_MC + 0x60)        /* Chip Select Assignment Register */
+#define AT91_EBI_CSA            0x60                    /* Chip Select Assignment Register */
 #define         AT91_EBI_CS0A           (1 << 0)                /* Chip Select 0 Assignment */
 #define                 AT91_EBI_CS0A_SMC               (0 << 0)
 #define                 AT91_EBI_CS0A_BFC               (1 << 0)
@@ -66,7 +66,7 @@
 #define         AT91_EBI_DBPUC          (1 << 0)                /* Data Bus Pull-Up Configuration */
 /* Static Memory Controller (SMC) registers */
-#define AT91_SMC_CSR(n)         (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
+#define AT91_SMC_CSR(n)         (0x70 + ((n) * 4))      /* SMC Chip Select Register */
 #define         AT91_SMC_NWS            (0x7f <<  0)            /* Number of Wait States */
 #define                 AT91_SMC_NWS_(x)        ((x) << 0)
 #define         AT91_SMC_WSEN           (1    <<  7)            /* Wait State Enable */
@@ -87,52 +87,8 @@
 #define         AT91_SMC_RWHOLD         (7 << 28)               /* Read & Write Signal Hold Time */
 #define                 AT91_SMC_RWHOLD_(x)     ((x) << 28)
-/* SDRAM Controller registers */
-#define AT91_SDRAMC_MR          (AT91_MC + 0x90)        /* Mode Register */
-#define         AT91_SDRAMC_MODE        (0xf << 0)              /* Command Mode */
-#define                 AT91_SDRAMC_MODE_NORMAL         (0 << 0)
-#define                 AT91_SDRAMC_MODE_NOP            (1 << 0)
-#define                 AT91_SDRAMC_MODE_PRECHARGE      (2 << 0)
-#define                 AT91_SDRAMC_MODE_LMR            (3 << 0)
-#define                 AT91_SDRAMC_MODE_REFRESH        (4 << 0)
-#define         AT91_SDRAMC_DBW         (1   << 4)              /* Data Bus Width */
-#define                 AT91_SDRAMC_DBW_32      (0 << 4)
-#define                 AT91_SDRAMC_DBW_16      (1 << 4)
-#define AT91_SDRAMC_TR          (AT91_MC + 0x94)        /* Refresh Timer Register */
-#define         AT91_SDRAMC_COUNT       (0xfff << 0)            /* Refresh Timer Count */
-#define AT91_SDRAMC_CR          (AT91_MC + 0x98)        /* Configuration Register */
-#define         AT91_SDRAMC_NC          (3   <<  0)             /* Number of Column Bits */
-#define                 AT91_SDRAMC_NC_8        (0 << 0)
-#define                 AT91_SDRAMC_NC_9        (1 << 0)
-#define                 AT91_SDRAMC_NC_10       (2 << 0)
-#define                 AT91_SDRAMC_NC_11       (3 << 0)
-#define         AT91_SDRAMC_NR          (3   <<  2)             /* Number of Row Bits */
-#define                 AT91_SDRAMC_NR_11       (0 << 2)
-#define                 AT91_SDRAMC_NR_12       (1 << 2)
-#define                 AT91_SDRAMC_NR_13       (2 << 2)
-#define         AT91_SDRAMC_NB          (1   <<  4)             /* Number of Banks */
-#define                 AT91_SDRAMC_NB_2        (0 << 4)
-#define                 AT91_SDRAMC_NB_4        (1 << 4)
-#define         AT91_SDRAMC_CAS         (3   <<  5)             /* CAS Latency */
-#define                 AT91_SDRAMC_CAS_2       (2 << 5)
-#define         AT91_SDRAMC_TWR         (0xf <<  7)             /* Write Recovery Delay */
-#define         AT91_SDRAMC_TRC         (0xf << 11)             /* Row Cycle Delay */
-#define         AT91_SDRAMC_TRP         (0xf << 15)             /* Row Precharge Delay */
-#define         AT91_SDRAMC_TRCD        (0xf << 19)             /* Row to Column Delay */
-#define         AT91_SDRAMC_TRAS        (0xf << 23)             /* Active to Precharge Delay */
-#define         AT91_SDRAMC_TXSR        (0xf << 27)             /* Exit Self Refresh to Active Delay */
-#define AT91_SDRAMC_SRR         (AT91_MC + 0x9c)        /* Self Refresh Register */
-#define AT91_SDRAMC_LPR         (AT91_MC + 0xa0)        /* Low Power Register */
-#define AT91_SDRAMC_IER         (AT91_MC + 0xa4)        /* Interrupt Enable Register */
-#define AT91_SDRAMC_IDR         (AT91_MC + 0xa8)        /* Interrupt Disable Register */
-#define AT91_SDRAMC_IMR         (AT91_MC + 0xac)        /* Interrupt Mask Register */
-#define AT91_SDRAMC_ISR         (AT91_MC + 0xb0)        /* Interrupt Status Register */
 /* Burst Flash Controller register */
-#define AT91_BFC_MR             (AT91_MC + 0xc0)        /* Mode Register */
+#define AT91_BFC_MR             0xc0                    /* Mode Register */
 #define         AT91_BFC_BFCOM          (3   <<  0)             /* Burst Flash Controller Operating Mode */
 #define                 AT91_BFC_BFCOM_DISABLED (0 << 0)
 #define                 AT91_BFC_BFCOM_ASYNC    (1 << 0)
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h b/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
new file mode 100644
index 000000000000..aa047f458f1b
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
@@ -0,0 +1,63 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Memory Controllers (SDRAMC only) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91RM9200_SDRAMC_H
+#define AT91RM9200_SDRAMC_H
+/* SDRAM Controller registers */
+#define AT91RM9200_SDRAMC_MR            0x90                    /* Mode Register */
+#define         AT91RM9200_SDRAMC_MODE  (0xf << 0)              /* Command Mode */
+#define                 AT91RM9200_SDRAMC_MODE_NORMAL           (0 << 0)
+#define                 AT91RM9200_SDRAMC_MODE_NOP              (1 << 0)
+#define                 AT91RM9200_SDRAMC_MODE_PRECHARGE        (2 << 0)
+#define                 AT91RM9200_SDRAMC_MODE_LMR              (3 << 0)
+#define                 AT91RM9200_SDRAMC_MODE_REFRESH  (4 << 0)
+#define         AT91RM9200_SDRAMC_DBW           (1   << 4)              /* Data Bus Width */
+#define                 AT91RM9200_SDRAMC_DBW_32        (0 << 4)
+#define                 AT91RM9200_SDRAMC_DBW_16        (1 << 4)
+#define AT91RM9200_SDRAMC_TR            0x94                    /* Refresh Timer Register */
+#define         AT91RM9200_SDRAMC_COUNT (0xfff << 0)            /* Refresh Timer Count */
+#define AT91RM9200_SDRAMC_CR            0x98                    /* Configuration Register */
+#define         AT91RM9200_SDRAMC_NC            (3   <<  0)             /* Number of Column Bits */
+#define                 AT91RM9200_SDRAMC_NC_8  (0 << 0)
+#define                 AT91RM9200_SDRAMC_NC_9  (1 << 0)
+#define                 AT91RM9200_SDRAMC_NC_10 (2 << 0)
+#define                 AT91RM9200_SDRAMC_NC_11 (3 << 0)
+#define         AT91RM9200_SDRAMC_NR            (3   <<  2)             /* Number of Row Bits */
+#define                 AT91RM9200_SDRAMC_NR_11 (0 << 2)
+#define                 AT91RM9200_SDRAMC_NR_12 (1 << 2)
+#define                 AT91RM9200_SDRAMC_NR_13 (2 << 2)
+#define         AT91RM9200_SDRAMC_NB            (1   <<  4)             /* Number of Banks */
+#define                 AT91RM9200_SDRAMC_NB_2  (0 << 4)
+#define                 AT91RM9200_SDRAMC_NB_4  (1 << 4)
+#define         AT91RM9200_SDRAMC_CAS           (3   <<  5)             /* CAS Latency */
+#define                 AT91RM9200_SDRAMC_CAS_2 (2 << 5)
+#define         AT91RM9200_SDRAMC_TWR           (0xf <<  7)             /* Write Recovery Delay */
+#define         AT91RM9200_SDRAMC_TRC           (0xf << 11)             /* Row Cycle Delay */
+#define         AT91RM9200_SDRAMC_TRP           (0xf << 15)             /* Row Precharge Delay */
+#define         AT91RM9200_SDRAMC_TRCD  (0xf << 19)             /* Row to Column Delay */
+#define         AT91RM9200_SDRAMC_TRAS  (0xf << 23)             /* Active to Precharge Delay */
+#define         AT91RM9200_SDRAMC_TXSR  (0xf << 27)             /* Exit Self Refresh to Active Delay */
+#define AT91RM9200_SDRAMC_SRR           0x9c                    /* Self Refresh Register */
+#define AT91RM9200_SDRAMC_LPR           0xa0                    /* Low Power Register */
+#define AT91RM9200_SDRAMC_IER           0xa4                    /* Interrupt Enable Register */
+#define AT91RM9200_SDRAMC_IDR           0xa8                    /* Interrupt Disable Register */
+#define AT91RM9200_SDRAMC_IMR           0xac                    /* Interrupt Mask Register */
+#define AT91RM9200_SDRAMC_ISR           0xb0                    /* Interrupt Status Register */
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index fa5ca278adeb..08ae9afd00fe 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -78,15 +78,12 @@
 #define AT91SAM9260_BASE_ADC            0xfffe0000
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
 */
-#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
 #define AT91SAM9260_BASE_ECC    0xffffe800
+#define AT91SAM9260_BASE_SDRAMC 0xffffea00
 #define AT91SAM9260_BASE_SMC    0xffffec00
+#define AT91SAM9260_BASE_MATRIX 0xffffee00
 #define AT91SAM9260_BASE_DBGU   AT91_BASE_DBGU0
 #define AT91SAM9260_BASE_PIOA   0xfffff400
 #define AT91SAM9260_BASE_PIOB   0xfffff600
@@ -96,6 +93,7 @@
 #define AT91SAM9260_BASE_RTT    0xfffffd20
 #define AT91SAM9260_BASE_PIT    0xfffffd30
 #define AT91SAM9260_BASE_WDT    0xfffffd40
+#define AT91SAM9260_BASE_GPBR   0xfffffd50
 #define AT91_USART0     AT91SAM9260_BASE_US0
 #define AT91_USART1     AT91SAM9260_BASE_US1
@@ -115,6 +113,8 @@
 #define AT91SAM9260_SRAM0_SIZE  SZ_4K           /* Internal SRAM 0 size (4Kb) */
 #define AT91SAM9260_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
 #define AT91SAM9260_SRAM1_SIZE  SZ_4K           /* Internal SRAM 1 size (4Kb) */
+#define AT91SAM9260_SRAM_BASE   0x002FF000      /* Internal SRAM base address */
+#define AT91SAM9260_SRAM_SIZE   SZ_8K           /* Internal SRAM size (8Kb) */
 #define AT91SAM9260_UHP_BASE    0x00500000      /* USB Host controller */
@@ -128,6 +128,8 @@
 #define AT91SAM9G20_SRAM0_SIZE  SZ_16K          /* Internal SRAM 0 size (16Kb) */
 #define AT91SAM9G20_SRAM1_BASE  0x00300000      /* Internal SRAM 1 base address */
 #define AT91SAM9G20_SRAM1_SIZE  SZ_16K          /* Internal SRAM 1 size (16Kb) */
+#define AT91SAM9G20_SRAM_BASE   0x002FC000      /* Internal SRAM base address */
+#define AT91SAM9G20_SRAM_SIZE   SZ_32K          /* Internal SRAM size (32Kb) */
 #define AT91SAM9G20_UHP_BASE    0x00500000      /* USB Host controller */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
index 020f02ed921a..f459df420629 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
@@ -15,12 +15,12 @@
 #ifndef AT91SAM9260_MATRIX_H
 #define AT91SAM9260_MATRIX_H
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG0       0x00                    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG1       0x04                    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG2       0x08                    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG3       0x0C                    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG4       0x10                    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG5       0x14                    /* Master Configuration Register 5 */
 #define         AT91_MATRIX_ULBT                (7 << 0)        /* Undefined Length Burst Type */
 #define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
 #define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
@@ -28,11 +28,11 @@
 #define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
 #define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG0       0x40                    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG1       0x44                    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG2       0x48                    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG3       0x4C                    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG4       0x50                    /* Slave Configuration Register 4 */
 #define         AT91_MATRIX_SLOT_CYCLE          (0xff <<  0)    /* Maximum Number of Allowed Cycles for a Burst */
 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
@@ -43,11 +43,11 @@
 #define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
 #define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS0       0x80                    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS1       0x88                    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS2       0x90                    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS3       0x98                    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRAS4       0xA0                    /* Priority Register A for Slave 4 */
 #define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
 #define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
 #define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
@@ -55,11 +55,11 @@
 #define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
 #define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define AT91_MATRIX_MRCR        0x100                   /* Master Remap Control Register */
 #define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x11C)   /* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_EBICSA      0x11C                   /* EBI Chip Select Assignment Register */
 #define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
 #define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 7cde2d36570e..44fbdc12ee62 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -63,14 +63,11 @@
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
 */
-#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
 #define AT91SAM9261_BASE_SMC    0xffffec00
+#define AT91SAM9261_BASE_MATRIX 0xffffee00
+#define AT91SAM9261_BASE_SDRAMC 0xffffea00
 #define AT91SAM9261_BASE_DBGU   AT91_BASE_DBGU0
 #define AT91SAM9261_BASE_PIOA   0xfffff400
 #define AT91SAM9261_BASE_PIOB   0xfffff600
@@ -80,6 +77,7 @@
 #define AT91SAM9261_BASE_RTT    0xfffffd20
 #define AT91SAM9261_BASE_PIT    0xfffffd30
 #define AT91SAM9261_BASE_WDT    0xfffffd40
+#define AT91SAM9261_BASE_GPBR   0xfffffd50
 #define AT91_USART0     AT91SAM9261_BASE_US0
 #define AT91_USART1     AT91SAM9261_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
index 69c6501915d9..a50cdf8b8ca4 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
@@ -15,15 +15,15 @@
 #ifndef AT91SAM9261_MATRIX_H
 #define AT91SAM9261_MATRIX_H
-#define AT91_MATRIX_MCFG        (AT91_MATRIX + 0x00)    /* Master Configuration Register */
+#define AT91_MATRIX_MCFG        0x00                    /* Master Configuration Register */
 #define         AT91_MATRIX_RCB0        (1 << 0)                /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define         AT91_MATRIX_RCB1        (1 << 1)                /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x04)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG0       0x04                    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x08)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG1       0x08                    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x0C)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG2       0x0C                    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x10)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG3       0x10                    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x14)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG4       0x14                    /* Slave Configuration Register 4 */
 #define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
@@ -31,7 +31,7 @@
 #define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
 #define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
-#define AT91_MATRIX_TCR         (AT91_MATRIX + 0x24)    /* TCM Configuration Register */
+#define AT91_MATRIX_TCR         0x24                    /* TCM Configuration Register */
 #define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
 #define                 AT91_MATRIX_ITCM_0              (0 << 0)
 #define                 AT91_MATRIX_ITCM_16             (5 << 0)
@@ -43,7 +43,7 @@
 #define                 AT91_MATRIX_DTCM_32             (6 << 4)
 #define                 AT91_MATRIX_DTCM_64             (7 << 4)
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x30)    /* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_EBICSA      0x30                    /* EBI Chip Select Assignment Register */
 #define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
 #define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
@@ -58,7 +58,7 @@
 #define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
 #define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_USBPUCR     (AT91_MATRIX + 0x34)    /* USB Pad Pull-Up Control Register */
+#define AT91_MATRIX_USBPUCR     0x34                    /* USB Pad Pull-Up Control Register */
 #define         AT91_MATRIX_USBPUCR_PUON        (1 << 30)       /* USB Device PAD Pull-up Enable */
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 5949abda962b..d96cbb2e03c4 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -72,18 +72,15 @@
 #define AT91SAM9263_BASE_2DGE           0xfffc8000
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
 */
-#define AT91_SDRAMC0    (0xffffe200 - AT91_BASE_SYS)
-#define AT91_SDRAMC1    (0xffffe800 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffec00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
 #define AT91SAM9263_BASE_ECC0   0xffffe000
+#define AT91SAM9263_BASE_SDRAMC0 0xffffe200
 #define AT91SAM9263_BASE_SMC0   0xffffe400
 #define AT91SAM9263_BASE_ECC1   0xffffe600
+#define AT91SAM9263_BASE_SDRAMC1 0xffffe800
 #define AT91SAM9263_BASE_SMC1   0xffffea00
+#define AT91SAM9263_BASE_MATRIX 0xffffec00
 #define AT91SAM9263_BASE_DBGU   AT91_BASE_DBGU1
 #define AT91SAM9263_BASE_PIOA   0xfffff200
 #define AT91SAM9263_BASE_PIOB   0xfffff400
@@ -96,6 +93,7 @@
 #define AT91SAM9263_BASE_PIT    0xfffffd30
 #define AT91SAM9263_BASE_WDT    0xfffffd40
 #define AT91SAM9263_BASE_RTT1   0xfffffd50
+#define AT91SAM9263_BASE_GPBR   0xfffffd60
 #define AT91_USART0     AT91SAM9263_BASE_US0
 #define AT91_USART1     AT91SAM9263_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
index 9b3efd3eb2f3..ebb5fdb565e0 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
@@ -15,15 +15,15 @@
 #ifndef AT91SAM9263_MATRIX_H
 #define AT91SAM9263_MATRIX_H
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG0       0x00                    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG1       0x04                    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG2       0x08                    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG3       0x0C                    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG4       0x10                    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG5       0x14                    /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG6       0x18                    /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG7       0x1C                    /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG8       0x20                    /* Master Configuration Register 8 */
 #define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
 #define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
 #define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
@@ -31,14 +31,14 @@
 #define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
 #define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG0       0x40                    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG1       0x44                    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG2       0x48                    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG3       0x4C                    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG4       0x50                    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG5       0x54                    /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG6       0x58                    /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
+#define AT91_MATRIX_SCFG7       0x5C                    /* Slave Configuration Register 7 */
 #define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
@@ -49,22 +49,22 @@
 #define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
 #define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS0       0x80                    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRBS0       0x84                    /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS1       0x88                    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRBS1       0x8C                    /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS2       0x90                    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRBS2       0x94                    /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS3       0x98                    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRBS3       0x9C                    /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRAS4       0xA0                    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRBS4       0xA4                    /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRAS5       0xA8                    /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRBS5       0xAC                    /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRAS6       0xB0                    /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRBS6       0xB4                    /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRAS7       0xB8                    /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
+#define AT91_MATRIX_PRBS7       0xBC                    /* Priority Register B for Slave 7 */
 #define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
 #define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
 #define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
@@ -75,7 +75,7 @@
 #define         AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
 #define         AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define AT91_MATRIX_MRCR        0x100                   /* Master Remap Control Register */
 #define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 #define         AT91_MATRIX_RCB2                (1 << 2)
@@ -86,7 +86,7 @@
 #define         AT91_MATRIX_RCB7                (1 << 7)
 #define         AT91_MATRIX_RCB8                (1 << 8)
-#define AT91_MATRIX_TCMR        (AT91_MATRIX + 0x114)   /* TCM Configuration Register */
+#define AT91_MATRIX_TCMR        0x114                   /* TCM Configuration Register */
 #define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
 #define                 AT91_MATRIX_ITCM_0              (0 << 0)
 #define                 AT91_MATRIX_ITCM_16             (5 << 0)
@@ -96,7 +96,7 @@
 #define                 AT91_MATRIX_DTCM_16             (5 << 4)
 #define                 AT91_MATRIX_DTCM_32             (6 << 4)
-#define AT91_MATRIX_EBI0CSA     (AT91_MATRIX + 0x120)   /* EBI0 Chip Select Assignment Register */
+#define AT91_MATRIX_EBI0CSA     0x120                   /* EBI0 Chip Select Assignment Register */
 #define         AT91_MATRIX_EBI0_CS1A           (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_EBI0_CS1A_SMC               (0 << 1)
 #define                 AT91_MATRIX_EBI0_CS1A_SDRAMC            (1 << 1)
@@ -114,7 +114,7 @@
 #define                 AT91_MATRIX_EBI0_VDDIOMSEL_1_8V         (0 << 16)
 #define                 AT91_MATRIX_EBI0_VDDIOMSEL_3_3V         (1 << 16)
-#define AT91_MATRIX_EBI1CSA     (AT91_MATRIX + 0x124)   /* EBI1 Chip Select Assignment Register */
+#define AT91_MATRIX_EBI1CSA     0x124                   /* EBI1 Chip Select Assignment Register */
 #define         AT91_MATRIX_EBI1_CS1A           (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_EBI1_CS1A_SMC               (0 << 1)
 #define                 AT91_MATRIX_EBI1_CS1A_SDRAMC            (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index 5d4a9f846584..0210797abf2e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -121,10 +121,4 @@
 #define         AT91_DDRSDRC_WPVS       (1 << 0)                /* Write protect violation status */
 #define         AT91_DDRSDRC_WPVSRC     (0xffff << 8)           /* Write protect violation source */
-/* Register access macros */
-#define at91_ramc_read(num, reg) \
-        at91_sys_read(AT91_DDRSDRC##num + reg)
-#define at91_ramc_write(num, reg, value) \
-        at91_sys_write(AT91_DDRSDRC##num + reg, value)
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 100f5a592926..3d085a9a7450 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -82,10 +82,4 @@
 #define                 AT91_SDRAMC_MD_SDRAM            0
 #define                 AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
-/* Register access macros */
-#define at91_ramc_read(num, reg) \
-        at91_sys_read(AT91_SDRAMC##num + reg)
-#define at91_ramc_write(num, reg, value) \
-        at91_sys_write(AT91_SDRAMC##num + reg, value)
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index dd9c95ea0862..d052abcff852 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -84,17 +84,14 @@
 #define AT91SAM9G45_BASE_TC5            0xfffd4080
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
 */
-#define AT91_DDRSDRC1   (0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC0   (0xffffe600 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
 #define AT91SAM9G45_BASE_ECC    0xffffe200
+#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400
+#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600
 #define AT91SAM9G45_BASE_DMA    0xffffec00
 #define AT91SAM9G45_BASE_SMC    0xffffe800
+#define AT91SAM9G45_BASE_MATRIX 0xffffea00
 #define AT91SAM9G45_BASE_DBGU   AT91_BASE_DBGU1
 #define AT91SAM9G45_BASE_PIOA   0xfffff200
 #define AT91SAM9G45_BASE_PIOB   0xfffff400
@@ -107,6 +104,7 @@
 #define AT91SAM9G45_BASE_PIT    0xfffffd30
 #define AT91SAM9G45_BASE_WDT    0xfffffd40
 #define AT91SAM9G45_BASE_RTC    0xfffffdb0
+#define AT91SAM9G45_BASE_GPBR   0xfffffd60
 #define AT91_USART0     AT91SAM9G45_BASE_US0
 #define AT91_USART1     AT91SAM9G45_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
index c972d60e0aeb..b76e2ed2fbc2 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
@@ -15,18 +15,18 @@
 #ifndef AT91SAM9G45_MATRIX_H
 #define AT91SAM9G45_MATRIX_H
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG0       0x00                    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG1       0x04                    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG2       0x08                    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG3       0x0C                    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG4       0x10                    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG5       0x14                    /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG6       0x18                    /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG7       0x1C                    /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG8       0x20                    /* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9       (AT91_MATRIX + 0x24)    /* Master Configuration Register 9 */
+#define AT91_MATRIX_MCFG9       0x24                    /* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10      (AT91_MATRIX + 0x28)    /* Master Configuration Register 10 */
+#define AT91_MATRIX_MCFG10      0x28                    /* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11      (AT91_MATRIX + 0x2C)    /* Master Configuration Register 11 */
+#define AT91_MATRIX_MCFG11      0x2C                    /* Master Configuration Register 11 */
 #define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
 #define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
 #define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
@@ -37,14 +37,14 @@
 #define                 AT91_MATRIX_ULBT_SIXTYFOUR      (6 << 0)
 #define                 AT91_MATRIX_ULBT_128            (7 << 0)
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG0       0x40                    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG1       0x44                    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG2       0x48                    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG3       0x4C                    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG4       0x50                    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG5       0x54                    /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG6       0x58                    /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
+#define AT91_MATRIX_SCFG7       0x5C                    /* Slave Configuration Register 7 */
 #define         AT91_MATRIX_SLOT_CYCLE          (0x1ff << 0)    /* Maximum Number of Allowed Cycles for a Burst */
 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
@@ -52,22 +52,22 @@
 #define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
 #define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS0       0x80                    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRBS0       0x84                    /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS1       0x88                    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRBS1       0x8C                    /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS2       0x90                    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRBS2       0x94                    /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS3       0x98                    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRBS3       0x9C                    /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRAS4       0xA0                    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRBS4       0xA4                    /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRAS5       0xA8                    /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRBS5       0xAC                    /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRAS6       0xB0                    /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRBS6       0xB4                    /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRAS7       0xB8                    /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
+#define AT91_MATRIX_PRBS7       0xBC                    /* Priority Register B for Slave 7 */
 #define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
 #define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
 #define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
@@ -81,7 +81,7 @@
 #define         AT91_MATRIX_M10PR               (3 << 8)        /* Master 10 Priority (in Register B) */
 #define         AT91_MATRIX_M11PR               (3 << 12)       /* Master 11 Priority (in Register B) */
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define AT91_MATRIX_MRCR        0x100                   /* Master Remap Control Register */
 #define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 #define         AT91_MATRIX_RCB2                (1 << 2)
@@ -95,7 +95,7 @@
 #define         AT91_MATRIX_RCB10               (1 << 10)
 #define         AT91_MATRIX_RCB11               (1 << 11)
-#define AT91_MATRIX_TCMR        (AT91_MATRIX + 0x110)   /* TCM Configuration Register */
+#define AT91_MATRIX_TCMR        0x110                   /* TCM Configuration Register */
 #define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
 #define                 AT91_MATRIX_ITCM_0              (0 << 0)
 #define                 AT91_MATRIX_ITCM_32             (6 << 0)
@@ -107,12 +107,12 @@
 #define                 AT91_MATRIX_TCM_NO_WS           (0x0 << 11)
 #define                 AT91_MATRIX_TCM_ONE_WS          (0x1 << 11)
-#define AT91_MATRIX_VIDEO       (AT91_MATRIX + 0x118)   /* Video Mode Configuration Register */
+#define AT91_MATRIX_VIDEO       0x118                   /* Video Mode Configuration Register */
 #define         AT91C_VDEC_SEL                  (0x1 <<  0) /* Video Mode Selection */
 #define                 AT91C_VDEC_SEL_OFF              (0 << 0)
 #define                 AT91C_VDEC_SEL_ON               (1 << 0)
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x128)   /* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_EBICSA      0x128                   /* EBI Chip Select Assignment Register */
 #define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
 #define                 AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
@@ -138,13 +138,13 @@
 #define                 AT91_MATRIX_EBI_DDR_IOSR_REDUCED        (0 << 18)
 #define                 AT91_MATRIX_EBI_DDR_IOSR_NORMAL         (1 << 18)
-#define AT91_MATRIX_WPMR        (AT91_MATRIX + 0x1E4)   /* Write Protect Mode Register */
+#define AT91_MATRIX_WPMR        0x1E4                   /* Write Protect Mode Register */
 #define         AT91_MATRIX_WPMR_WPEN           (1 << 0)        /* Write Protect ENable */
 #define                 AT91_MATRIX_WPMR_WP_WPDIS               (0 << 0)
 #define                 AT91_MATRIX_WPMR_WP_WPEN                (1 << 0)
 #define         AT91_MATRIX_WPMR_WPKEY          (0xFFFFFF << 8) /* Write Protect KEY */
-#define AT91_MATRIX_WPSR        (AT91_MATRIX + 0x1E8)   /* Write Protect Status Register */
+#define AT91_MATRIX_WPSR        0x1E8                   /* Write Protect Status Register */
 #define         AT91_MATRIX_WPSR_WPVS           (1 << 0)        /* Write Protect Violation Status */
 #define                 AT91_MATRIX_WPSR_NO_WPV         (0 << 0)
 #define                 AT91_MATRIX_WPSR_WPV            (1 << 0)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index d7bead7118da..e0073eb10144 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -69,15 +69,13 @@
 /*
 * System Peripherals (offset from AT91_BASE_SYS)
 */
-#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
 #define AT91_SCKCR      (0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
 #define AT91SAM9RL_BASE_DMA     0xffffe600
 #define AT91SAM9RL_BASE_ECC     0xffffe800
+#define AT91SAM9RL_BASE_SDRAMC  0xffffea00
 #define AT91SAM9RL_BASE_SMC     0xffffec00
+#define AT91SAM9RL_BASE_MATRIX  0xffffee00
 #define AT91SAM9RL_BASE_DBGU    AT91_BASE_DBGU0
 #define AT91SAM9RL_BASE_PIOA    0xfffff400
 #define AT91SAM9RL_BASE_PIOB    0xfffff600
@@ -88,6 +86,7 @@
 #define AT91SAM9RL_BASE_RTT     0xfffffd20
 #define AT91SAM9RL_BASE_PIT     0xfffffd30
 #define AT91SAM9RL_BASE_WDT     0xfffffd40
+#define AT91SAM9RL_BASE_GPBR    0xfffffd60
 #define AT91SAM9RL_BASE_RTC     0xfffffe00
 #define AT91_USART0     AT91SAM9RL_BASE_US0
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
index 5f9149071fe5..6d160adadafc 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h
@@ -14,12 +14,12 @@
 #ifndef AT91SAM9RL_MATRIX_H
 #define AT91SAM9RL_MATRIX_H
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG0       0x00                    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG1       0x04                    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG2       0x08                    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG3       0x0C                    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG4       0x10                    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG5       0x14                    /* Master Configuration Register 5 */
 #define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
 #define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
 #define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
@@ -27,12 +27,12 @@
 #define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
 #define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG0       0x40                    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG1       0x44                    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG2       0x48                    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG3       0x4C                    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG4       0x50                    /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG5       0x54                    /* Slave Configuration Register 5 */
 #define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
@@ -43,12 +43,12 @@
 #define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
 #define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS0       0x80                    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS1       0x88                    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS2       0x90                    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS3       0x98                    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRAS4       0xA0                    /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRAS5       0xA8                    /* Priority Register A for Slave 5 */
 #define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
 #define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
 #define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
@@ -56,7 +56,7 @@
 #define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
 #define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define AT91_MATRIX_MRCR        0x100                   /* Master Remap Control Register */
 #define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 #define         AT91_MATRIX_RCB2                (1 << 2)
@@ -64,7 +64,7 @@
 #define         AT91_MATRIX_RCB4                (1 << 4)
 #define         AT91_MATRIX_RCB5                (1 << 5)
-#define AT91_MATRIX_TCMR        (AT91_MATRIX + 0x114)   /* TCM Configuration Register */
+#define AT91_MATRIX_TCMR        0x114                   /* TCM Configuration Register */
 #define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
 #define                 AT91_MATRIX_ITCM_0              (0 << 0)
 #define                 AT91_MATRIX_ITCM_16             (5 << 0)
@@ -74,7 +74,7 @@
 #define                 AT91_MATRIX_DTCM_16             (5 << 4)
 #define                 AT91_MATRIX_DTCM_32             (6 << 4)
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x120)   /* EBI0 Chip Select Assignment Register */
+#define AT91_MATRIX_EBICSA      0x120                   /* EBI0 Chip Select Assignment Register */
 #define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
 #define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
 #define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 8476871a2f9f..a297a77d88e2 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -55,10 +55,9 @@
 #define AT91SAM9X5_BASE_USART2  0xf8024000
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
 */
-#define AT91_DDRSDRC0   (0xffffe800 - AT91_BASE_SYS)
+#define AT91SAM9X5_BASE_DDRSDRC0        0xffffe800
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
 /*
 * Base addresses for early serial code (uncompress.h)
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
index a57829f4fd18..90680217064e 100644
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -28,18 +28,18 @@
 #define AT91X40_ID_IRQ2         18      /* External IRQ 2 */
 /*
- * System Peripherals (offset from AT91_BASE_SYS)
+ * System Peripherals
 */
 #define AT91_BASE_SYS   0xffc00000
-#define AT91_EBI        (0xffe00000 - AT91_BASE_SYS)    /* External Bus Interface */
+#define AT91_EBI        0xffe00000      /* External Bus Interface */
-#define AT91_SF         (0xfff00000 - AT91_BASE_SYS)    /* Special Function */
+#define AT91_SF         0xfff00000      /* Special Function */
-#define AT91_USART1     (0xfffcc000 - AT91_BASE_SYS)    /* USART 1 */
+#define AT91_USART1     0xfffcc000      /* USART 1 */
-#define AT91_USART0     (0xfffd0000 - AT91_BASE_SYS)    /* USART 0 */
+#define AT91_USART0     0xfffd0000      /* USART 0 */
-#define AT91_TC         (0xfffe0000 - AT91_BASE_SYS)    /* Timer Counter */
+#define AT91_TC         0xfffe0000      /* Timer Counter */
-#define AT91_PIOA       (0xffff0000 - AT91_BASE_SYS)    /* PIO Controller A */
+#define AT91_PIOA       0xffff0000      /* PIO Controller A */
-#define AT91_PS         (0xffff4000 - AT91_BASE_SYS)    /* Power Save */
+#define AT91_PS         0xffff4000      /* Power Save */
-#define AT91_WD         (0xffff8000 - AT91_BASE_SYS)    /* Watchdog Timer */
+#define AT91_WD         0xffff8000      /* Watchdog Timer */
 /*
 * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index e3fd225121c7..eed465ab0dd7 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -191,10 +191,15 @@
 extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup);
 extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
 extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
+extern int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup);
+extern int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup);
 extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
 extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
 extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
+extern int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div);
 extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
+extern int __init_or_module at91_set_pulldown(unsigned pin, int is_on);
+extern int __init_or_module at91_disable_schmitt_trig(unsigned pin);
 /* callable at any time */
 extern int at91_set_gpio_value(unsigned pin, int value);
@@ -204,18 +209,6 @@ extern int at91_get_gpio_value(unsigned pin);
 extern void at91_gpio_suspend(void);
 extern void at91_gpio_resume(void);
-/*-------------------------------------------------------------------------*/
-/* wrappers for "new style" GPIO calls. the old AT91-specific ones should
- * eventually be removed (along with this errno.h inclusion), and the
- * gpio request/free calls should probably be implemented.
- */
-#include <asm/errno.h>
-#define gpio_to_irq(gpio) (gpio + NR_AIC_IRQS)
-#define irq_to_gpio(irq)  (irq - NR_AIC_IRQS)
 #endif  /* __ASSEMBLY__ */
 #endif
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index fd7dce4f7378..e9e29a6c3868 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -59,9 +59,10 @@
 /*
 * On all at91 have the Advanced Interrupt Controller starts at address
- * 0xfffff000
+ * 0xfffff000 and the Power Management Controller starts at 0xfffffc00
 */
 #define AT91_AIC        0xfffff000
+#define AT91_PMC        0xfffffc00
 /*
 * Peripheral identifiers/interrupts.
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
index 4ca09ef7ca29..4003001eca3d 100644
--- a/arch/arm/mach-at91/include/mach/io.h
+++ b/arch/arm/mach-at91/include/mach/io.h
@@ -28,22 +28,4 @@
 #define __io(a)         __typesafe_io(a)
 #define __mem_pci(a)    (a)
-#ifndef __ASSEMBLY__
-static inline unsigned int at91_sys_read(unsigned int reg_offset)
-{
-        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
-        return __raw_readl(addr + reg_offset);
-}
-static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
-{
-        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
-        __raw_writel(value, addr + reg_offset);
-}
-#endif
 #endif
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index be6b639ecd7b..cfcfcbe36269 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -24,6 +24,12 @@
 #include <linux/module.h>
 #include <linux/mm.h>
 #include <linux/types.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/err.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -34,22 +40,24 @@
 #include <asm/mach/map.h>
 void __iomem *at91_aic_base;
+static struct irq_domain *at91_aic_domain;
+static struct device_node *at91_aic_np;
 static void at91_aic_mask_irq(struct irq_data *d)
 {
        /* Disable interrupt on AIC */
-        at91_aic_write(AT91_AIC_IDCR, 1 << d->irq);
+        at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
 }
 static void at91_aic_unmask_irq(struct irq_data *d)
 {
        /* Enable interrupt on AIC */
-        at91_aic_write(AT91_AIC_IECR, 1 << d->irq);
+        at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
 }
 unsigned int at91_extern_irq;
-#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
+#define is_extern_irq(hwirq) ((1 << (hwirq)) & at91_extern_irq)
 static int at91_aic_set_type(struct irq_data *d, unsigned type)
 {
@@ -63,13 +71,13 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
                srctype = AT91_AIC_SRCTYPE_RISING;
                break;
        case IRQ_TYPE_LEVEL_LOW:
-                if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq))           /* only supported on external interrupts */
+                if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))               /* only supported on external interrupts */
                        srctype = AT91_AIC_SRCTYPE_LOW;
                else
                        return -EINVAL;
                break;
        case IRQ_TYPE_EDGE_FALLING:
-                if ((d->irq == AT91_ID_FIQ) || is_extern_irq(d->irq))           /* only supported on external interrupts */
+                if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))               /* only supported on external interrupts */
                        srctype = AT91_AIC_SRCTYPE_FALLING;
                else
                        return -EINVAL;
@@ -78,8 +86,8 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
                return -EINVAL;
        }
-        smr = at91_aic_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE;
+        smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
-        at91_aic_write(AT91_AIC_SMR(d->irq), smr | srctype);
+        at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
        return 0;
 }
@@ -90,13 +98,13 @@ static u32 backups;
 static int at91_aic_set_wake(struct irq_data *d, unsigned value)
 {
-        if (unlikely(d->irq >= 32))
+        if (unlikely(d->hwirq >= NR_AIC_IRQS))
                return -EINVAL;
        if (value)
-                wakeups |= (1 << d->irq);
+                wakeups |= (1 << d->hwirq);
        else
-                wakeups &= ~(1 << d->irq);
+                wakeups &= ~(1 << d->hwirq);
        return 0;
 }
@@ -127,46 +135,112 @@ static struct irq_chip at91_aic_chip = {
        .irq_set_wake   = at91_aic_set_wake,
 };
+static void __init at91_aic_hw_init(unsigned int spu_vector)
+{
+        int i;
+        /*
+         * Perform 8 End Of Interrupt Command to make sure AIC
+         * will not Lock out nIRQ
+         */
+        for (i = 0; i < 8; i++)
+                at91_aic_write(AT91_AIC_EOICR, 0);
+        /*
+         * Spurious Interrupt ID in Spurious Vector Register.
+         * When there is no current interrupt, the IRQ Vector Register
+         * reads the value stored in AIC_SPU
+         */
+        at91_aic_write(AT91_AIC_SPU, spu_vector);
+        /* No debugging in AIC: Debug (Protect) Control Register */
+        at91_aic_write(AT91_AIC_DCR, 0);
+        /* Disable and clear all interrupts initially */
+        at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
+        at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
+}
+#if defined(CONFIG_OF)
+static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
+                                                        irq_hw_number_t hw)
+{
+        /* Put virq number in Source Vector Register */
+        at91_aic_write(AT91_AIC_SVR(hw), virq);
+        /* Active Low interrupt, without priority */
+        at91_aic_write(AT91_AIC_SMR(hw), AT91_AIC_SRCTYPE_LOW);
+        irq_set_chip_and_handler(virq, &at91_aic_chip, handle_level_irq);
+        set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+        return 0;
+}
+static struct irq_domain_ops at91_aic_irq_ops = {
+        .map    = at91_aic_irq_map,
+        .xlate  = irq_domain_xlate_twocell,
+};
+int __init at91_aic_of_init(struct device_node *node,
+                                     struct device_node *parent)
+{
+        at91_aic_base = of_iomap(node, 0);
+        at91_aic_np = node;
+        at91_aic_domain = irq_domain_add_linear(at91_aic_np, NR_AIC_IRQS,
+                                                &at91_aic_irq_ops, NULL);
+        if (!at91_aic_domain)
+                panic("Unable to add AIC irq domain (DT)\n");
+        irq_set_default_host(at91_aic_domain);
+        at91_aic_hw_init(NR_AIC_IRQS);
+        return 0;
+}
+#endif
 /*
 * Initialize the AIC interrupt controller.
 */
 void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
 {
        unsigned int i;
+        int irq_base;
        at91_aic_base = ioremap(AT91_AIC, 512);
        if (!at91_aic_base)
-                panic("Impossible to ioremap AT91_AIC\n");
+                panic("Unable to ioremap AIC registers\n");
+        /* Add irq domain for AIC */
+        irq_base = irq_alloc_descs(-1, 0, NR_AIC_IRQS, 0);
+        if (irq_base < 0) {
+                WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
+                irq_base = 0;
+        }
+        at91_aic_domain = irq_domain_add_legacy(at91_aic_np, NR_AIC_IRQS,
+                                                irq_base, 0,
+                                                &irq_domain_simple_ops, NULL);
+        if (!at91_aic_domain)
+                panic("Unable to add AIC irq domain\n");
+        irq_set_default_host(at91_aic_domain);
        /*
         * The IVR is used by macro get_irqnr_and_base to read and verify.
         * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
         */
        for (i = 0; i < NR_AIC_IRQS; i++) {
-                /* Put irq number in Source Vector Register: */
+                /* Put hardware irq number in Source Vector Register: */
                at91_aic_write(AT91_AIC_SVR(i), i);
                /* Active Low interrupt, with the specified priority */
                at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
                irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-                /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
-                if (i < 8)
-                        at91_aic_write(AT91_AIC_EOICR, 0);
        }
-        /*
+        at91_aic_hw_init(NR_AIC_IRQS);
-         * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
-         * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
-         */
-        at91_aic_write(AT91_AIC_SPU, NR_AIC_IRQS);
-        /* No debugging in AIC: Debug (Protect) Control Register */
-        at91_aic_write(AT91_AIC_DCR, 0);
-        /* Disable and clear all interrupts initially */
-        at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
-        at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
 }
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index d554e6771b4e..6c9d5e69ac28 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -136,7 +136,7 @@ static int at91_pm_verify_clocks(void)
        unsigned long scsr;
        int i;
-        scsr = at91_sys_read(AT91_PMC_SCSR);
+        scsr = at91_pmc_read(AT91_PMC_SCSR);
        /* USB must not be using PLLB */
        if (cpu_is_at91rm9200()) {
@@ -160,7 +160,7 @@ static int at91_pm_verify_clocks(void)
                if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
                        continue;
-                css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
+                css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
                if (css != AT91_PMC_CSS_SLOW) {
                        pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
                        return 0;
@@ -188,13 +188,27 @@ int at91_suspend_entering_slow_clock(void)
 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
-static void (*slow_clock)(void);
+static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
+                          void __iomem *ramc1, int memctrl);
 #ifdef CONFIG_AT91_SLOW_CLOCK
-extern void at91_slow_clock(void);
+extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
+                            void __iomem *ramc1, int memctrl);
 extern u32 at91_slow_clock_sz;
 #endif
+void __iomem *at91_ramc_base[2];
+void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
+{
+        if (id < 0 || id > 1) {
+                pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
+                BUG();
+        }
+        at91_ramc_base[id] = ioremap(addr, size);
+        if (!at91_ramc_base[id])
+                panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
+}
 static int at91_pm_enter(suspend_state_t state)
 {
@@ -203,7 +217,7 @@ static int at91_pm_enter(suspend_state_t state)
        pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
                        /* remember all the always-wake irqs */
-                        (at91_sys_read(AT91_PMC_PCSR)
+                        (at91_pmc_read(AT91_PMC_PCSR)
                                        | (1 << AT91_ID_FIQ)
                                        | (1 << AT91_ID_SYS)
                                        | (at91_extern_irq))
@@ -228,11 +242,18 @@ static int at91_pm_enter(suspend_state_t state)
                         * turning off the main oscillator; reverse on wakeup.
                         */
                        if (slow_clock) {
+                                int memctrl = AT91_MEMCTRL_SDRAMC;
+                                if (cpu_is_at91rm9200())
+                                        memctrl = AT91_MEMCTRL_MC;
+                                else if (cpu_is_at91sam9g45())
+                                        memctrl = AT91_MEMCTRL_DDRSDR;
 #ifdef CONFIG_AT91_SLOW_CLOCK
                                /* copy slow_clock handler to SRAM, and call it */
                                memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
 #endif
-                                slow_clock();
+                                slow_clock(at91_pmc_base, at91_ramc_base[0],
+                                           at91_ramc_base[1], memctrl);
                                break;
                        } else {
                                pr_info("AT91: PM - no slow clock mode enabled ...\n");
@@ -301,7 +322,7 @@ static int __init at91_pm_init(void)
 #ifdef CONFIG_ARCH_AT91RM9200
        /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
-        at91_sys_write(AT91_SDRAMC_LPR, 0);
+        at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
 #endif
        suspend_set_ops(&at91_pm_ops);
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index bba9ce1aaaec..89f56f3a802e 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -11,8 +11,9 @@
 #ifndef __ARCH_ARM_MACH_AT91_PM
 #define __ARCH_ARM_MACH_AT91_PM
+#include <mach/at91_ramc.h>
 #ifdef CONFIG_ARCH_AT91RM9200
-#include <mach/at91rm9200_mc.h>
+#include <mach/at91rm9200_sdramc.h>
 /*
 * The AT91RM9200 goes into self-refresh mode with this command, and will
@@ -26,7 +27,7 @@
 static inline void at91rm9200_standby(void)
 {
-        u32 lpr = at91_sys_read(AT91_SDRAMC_LPR);
+        u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
        asm volatile(
                "b    1f\n\t"
@@ -37,15 +38,14 @@ static inline void at91rm9200_standby(void)
                "    mcr    p15, 0, %0, c7, c0, 4\n\t"
                "    str    %5, [%1, %2]"
                :
-                : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91_SDRAMC_LPR),
+                : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
-                  "r" (1), "r" (AT91_SDRAMC_SRR),
+                  "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
                  "r" (lpr));
 }
 #define at91_standby at91rm9200_standby
 #elif defined(CONFIG_ARCH_AT91SAM9G45)
-#include <mach/at91sam9_ddrsdr.h>
 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
 * remember.
@@ -78,7 +78,6 @@ static inline void at91sam9g45_standby(void)
 #define at91_standby at91sam9g45_standby
 #else
-#include <mach/at91sam9_sdramc.h>
 #ifdef CONFIG_ARCH_AT91SAM9263
 /*
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index f8539a8bcd6c..db5452123f17 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -15,14 +15,7 @@
 #include <linux/linkage.h>
 #include <mach/hardware.h>
 #include <mach/at91_pmc.h>
+#include <mach/at91_ramc.h>
-#if defined(CONFIG_ARCH_AT91RM9200)
-#include <mach/at91rm9200_mc.h>
-#elif defined(CONFIG_ARCH_AT91SAM9G45)
-#include <mach/at91sam9_ddrsdr.h>
-#else
-#include <mach/at91sam9_sdramc.h>
-#endif
 #ifdef CONFIG_ARCH_AT91SAM9263
@@ -46,17 +39,23 @@
 #define PLLALOCK_TIMEOUT        1000
 #define PLLBLOCK_TIMEOUT        1000
+pmc     .req    r0
+sdramc  .req    r1
+ramc1   .req    r2
+memctrl .req    r3
+tmp1    .req    r4
+tmp2    .req    r5
 /*
 * Wait until master clock is ready (after switching master clock source)
 */
        .macro wait_mckrdy
-        mov     r4, #MCKRDY_TIMEOUT
+        mov     tmp2, #MCKRDY_TIMEOUT
-1:      sub     r4, r4, #1
+1:      sub     tmp2, tmp2, #1
-        cmp     r4, #0
+        cmp     tmp2, #0
        beq     2f
-        ldr     r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
+        ldr     tmp1, [pmc, #AT91_PMC_SR]
-        tst     r3, #AT91_PMC_MCKRDY
+        tst     tmp1, #AT91_PMC_MCKRDY
        beq     1b
 2:
        .endm
@@ -65,12 +64,12 @@
 * Wait until master oscillator has stabilized.
 */
        .macro wait_moscrdy
-        mov     r4, #MOSCRDY_TIMEOUT
+        mov     tmp2, #MOSCRDY_TIMEOUT
-1:      sub     r4, r4, #1
+1:      sub     tmp2, tmp2, #1
-        cmp     r4, #0
+        cmp     tmp2, #0
        beq     2f
-        ldr     r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
+        ldr     tmp1, [pmc, #AT91_PMC_SR]
-        tst     r3, #AT91_PMC_MOSCS
+        tst     tmp1, #AT91_PMC_MOSCS
        beq     1b
 2:
        .endm
@@ -79,12 +78,12 @@
 * Wait until PLLA has locked.
 */
        .macro wait_pllalock
-        mov     r4, #PLLALOCK_TIMEOUT
+        mov     tmp2, #PLLALOCK_TIMEOUT
-1:      sub     r4, r4, #1
+1:      sub     tmp2, tmp2, #1
-        cmp     r4, #0
+        cmp     tmp2, #0
        beq     2f
-        ldr     r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
+        ldr     tmp1, [pmc, #AT91_PMC_SR]
-        tst     r3, #AT91_PMC_LOCKA
+        tst     tmp1, #AT91_PMC_LOCKA
        beq     1b
 2:
        .endm
@@ -93,79 +92,98 @@
 * Wait until PLLB has locked.
 */
        .macro wait_pllblock
-        mov     r4, #PLLBLOCK_TIMEOUT
+        mov     tmp2, #PLLBLOCK_TIMEOUT
-1:      sub     r4, r4, #1
+1:      sub     tmp2, tmp2, #1
-        cmp     r4, #0
+        cmp     tmp2, #0
        beq     2f
-        ldr     r3, [r1, #(AT91_PMC_SR - AT91_PMC)]
+        ldr     tmp1, [pmc, #AT91_PMC_SR]
-        tst     r3, #AT91_PMC_LOCKB
+        tst     tmp1, #AT91_PMC_LOCKB
        beq     1b
 2:
        .endm
        .text
+/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
+ *                      void __iomem *ramc1, int memctrl)
+ */
 ENTRY(at91_slow_clock)
        /* Save registers on stack */
-        stmfd   sp!, {r0 - r12, lr}
+        stmfd   sp!, {r4 - r12, lr}
        /*
         * Register usage:
-         *  R1 = Base address of AT91_PMC
+         *  R0 = Base address of AT91_PMC
-         *  R2 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
+         *  R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
-         *  R3 = temporary register
+         *  R2 = Base address of second RAM Controller or 0 if not present
+         *  R3 = Memory controller
         *  R4 = temporary register
-         *  R5 = Base address of second RAM Controller or 0 if not present
+         *  R5 = temporary register
         */
-        ldr     r1, .at91_va_base_pmc
-        ldr     r2, .at91_va_base_sdramc
-        ldr     r5, .at91_va_base_ramc1
        /* Drain write buffer */
-        mov     r0, #0
+        mov     tmp1, #0
-        mcr     p15, 0, r0, c7, c10, 4
+        mcr     p15, 0, tmp1, c7, c10, 4
+        cmp     memctrl, #AT91_MEMCTRL_MC
+        bne     ddr_sr_enable
-#ifdef CONFIG_ARCH_AT91RM9200
+        /*
+         * at91rm9200 Memory controller
+         */
        /* Put SDRAM in self-refresh mode */
-        mov     r3, #1
+        mov     tmp1, #1
-        str     r3, [r2, #AT91_SDRAMC_SRR]
+        str     tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
-#elif defined(CONFIG_ARCH_AT91SAM9G45)
+        b       sdr_sr_done
+        /*
+         * DDRSDR Memory controller
+         */
+ddr_sr_enable:
+        cmp     memctrl, #AT91_MEMCTRL_DDRSDR
+        bne     sdr_sr_enable
        /* prepare for DDRAM self-refresh mode */
-        ldr     r3, [r2, #AT91_DDRSDRC_LPR]
+        ldr     tmp1, [sdramc, #AT91_DDRSDRC_LPR]
-        str     r3, .saved_sam9_lpr
+        str     tmp1, .saved_sam9_lpr
-        bic     r3, #AT91_DDRSDRC_LPCB
+        bic     tmp1, #AT91_DDRSDRC_LPCB
-        orr     r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+        orr     tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
        /* figure out if we use the second ram controller */
-        cmp     r5, #0
+        cmp     ramc1, #0
-        ldrne   r4, [r5, #AT91_DDRSDRC_LPR]
+        ldrne   tmp2, [ramc1, #AT91_DDRSDRC_LPR]
-        strne   r4, .saved_sam9_lpr1
+        strne   tmp2, .saved_sam9_lpr1
-        bicne   r4, #AT91_DDRSDRC_LPCB
+        bicne   tmp2, #AT91_DDRSDRC_LPCB
-        orrne   r4, #AT91_DDRSDRC_LPCB_SELF_REFRESH
+        orrne   tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
        /* Enable DDRAM self-refresh mode */
-        str     r3, [r2, #AT91_DDRSDRC_LPR]
+        str     tmp1, [sdramc, #AT91_DDRSDRC_LPR]
-        strne   r4, [r5, #AT91_DDRSDRC_LPR]
+        strne   tmp2, [ramc1, #AT91_DDRSDRC_LPR]
-#else
+        b       sdr_sr_done
+        /*
+         * SDRAMC Memory controller
+         */
+sdr_sr_enable:
        /* Enable SDRAM self-refresh mode */
-        ldr     r3, [r2, #AT91_SDRAMC_LPR]
+        ldr     tmp1, [sdramc, #AT91_SDRAMC_LPR]
-        str     r3, .saved_sam9_lpr
+        str     tmp1, .saved_sam9_lpr
-        bic     r3, #AT91_SDRAMC_LPCB
+        bic     tmp1, #AT91_SDRAMC_LPCB
-        orr     r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
+        orr     tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
-        str     r3, [r2, #AT91_SDRAMC_LPR]
+        str     tmp1, [sdramc, #AT91_SDRAMC_LPR]
-#endif
+sdr_sr_done:
        /* Save Master clock setting */
-        ldr     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+        ldr     tmp1, [pmc, #AT91_PMC_MCKR]
-        str     r3, .saved_mckr
+        str     tmp1, .saved_mckr
        /*
         * Set the Master clock source to slow clock
         */
-        bic     r3, r3, #AT91_PMC_CSS
+        bic     tmp1, tmp1, #AT91_PMC_CSS
-        str     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+        str     tmp1, [pmc, #AT91_PMC_MCKR]
        wait_mckrdy
@@ -175,61 +193,61 @@ ENTRY(at91_slow_clock)
         *
         * See AT91RM9200 errata #27 and #28 for details.
         */
-        mov     r3, #0
+        mov     tmp1, #0
-        str     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+        str     tmp1, [pmc, #AT91_PMC_MCKR]
        wait_mckrdy
 #endif
        /* Save PLLA setting and disable it */
-        ldr     r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
+        ldr     tmp1, [pmc, #AT91_CKGR_PLLAR]
-        str     r3, .saved_pllar
+        str     tmp1, .saved_pllar
-        mov     r3, #AT91_PMC_PLLCOUNT
+        mov     tmp1, #AT91_PMC_PLLCOUNT
-        orr     r3, r3, #(1 << 29)              /* bit 29 always set */
+        orr     tmp1, tmp1, #(1 << 29)          /* bit 29 always set */
-        str     r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
+        str     tmp1, [pmc, #AT91_CKGR_PLLAR]
        /* Save PLLB setting and disable it */
-        ldr     r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
+        ldr     tmp1, [pmc, #AT91_CKGR_PLLBR]
-        str     r3, .saved_pllbr
+        str     tmp1, .saved_pllbr
-        mov     r3, #AT91_PMC_PLLCOUNT
+        mov     tmp1, #AT91_PMC_PLLCOUNT
-        str     r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
+        str     tmp1, [pmc, #AT91_CKGR_PLLBR]
        /* Turn off the main oscillator */
-        ldr     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
+        ldr     tmp1, [pmc, #AT91_CKGR_MOR]
-        bic     r3, r3, #AT91_PMC_MOSCEN
+        bic     tmp1, tmp1, #AT91_PMC_MOSCEN
-        str     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
+        str     tmp1, [pmc, #AT91_CKGR_MOR]
        /* Wait for interrupt */
-        mcr     p15, 0, r0, c7, c0, 4
+        mcr     p15, 0, tmp1, c7, c0, 4
        /* Turn on the main oscillator */
-        ldr     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
+        ldr     tmp1, [pmc, #AT91_CKGR_MOR]
-        orr     r3, r3, #AT91_PMC_MOSCEN
+        orr     tmp1, tmp1, #AT91_PMC_MOSCEN
-        str     r3, [r1, #(AT91_CKGR_MOR - AT91_PMC)]
+        str     tmp1, [pmc, #AT91_CKGR_MOR]
        wait_moscrdy
        /* Restore PLLB setting */
-        ldr     r3, .saved_pllbr
+        ldr     tmp1, .saved_pllbr
-        str     r3, [r1, #(AT91_CKGR_PLLBR - AT91_PMC)]
+        str     tmp1, [pmc, #AT91_CKGR_PLLBR]
-        tst     r3, #(AT91_PMC_MUL &  0xff0000)
+        tst     tmp1, #(AT91_PMC_MUL &  0xff0000)
        bne     1f
-        tst     r3, #(AT91_PMC_MUL & ~0xff0000)
+        tst     tmp1, #(AT91_PMC_MUL & ~0xff0000)
        beq     2f
 1:
        wait_pllblock
 2:
        /* Restore PLLA setting */
-        ldr     r3, .saved_pllar
+        ldr     tmp1, .saved_pllar
-        str     r3, [r1, #(AT91_CKGR_PLLAR - AT91_PMC)]
+        str     tmp1, [pmc, #AT91_CKGR_PLLAR]
-        tst     r3, #(AT91_PMC_MUL &  0xff0000)
+        tst     tmp1, #(AT91_PMC_MUL &  0xff0000)
        bne     3f
-        tst     r3, #(AT91_PMC_MUL & ~0xff0000)
+        tst     tmp1, #(AT91_PMC_MUL & ~0xff0000)
        beq     4f
 3:
        wait_pllalock
@@ -242,11 +260,11 @@ ENTRY(at91_slow_clock)
         *
         * See AT91RM9200 errata #27 and #28 for details.
         */
-        ldr     r3, .saved_mckr
+        ldr     tmp1, .saved_mckr
-        tst     r3, #AT91_PMC_PRES
+        tst     tmp1, #AT91_PMC_PRES
        beq     2f
-        and     r3, r3, #AT91_PMC_PRES
+        and     tmp1, tmp1, #AT91_PMC_PRES
-        str     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+        str     tmp1, [pmc, #AT91_PMC_MCKR]
        wait_mckrdy
 #endif
@@ -254,31 +272,45 @@ ENTRY(at91_slow_clock)
        /*
         * Restore master clock setting
         */
-2:      ldr     r3, .saved_mckr
+2:      ldr     tmp1, .saved_mckr
-        str     r3, [r1, #(AT91_PMC_MCKR - AT91_PMC)]
+        str     tmp1, [pmc, #AT91_PMC_MCKR]
        wait_mckrdy
-#ifdef CONFIG_ARCH_AT91RM9200
+        /*
-        /* Do nothing - self-refresh is automatically disabled. */
+         * at91rm9200 Memory controller
-#elif defined(CONFIG_ARCH_AT91SAM9G45)
+         * Do nothing - self-refresh is automatically disabled.
+         */
+        cmp     memctrl, #AT91_MEMCTRL_MC
+        beq     ram_restored
+        /*
+         * DDRSDR Memory controller
+         */
+        cmp     memctrl, #AT91_MEMCTRL_DDRSDR
+        bne     sdr_en_restore
        /* Restore LPR on AT91 with DDRAM */
-        ldr     r3, .saved_sam9_lpr
+        ldr     tmp1, .saved_sam9_lpr
-        str     r3, [r2, #AT91_DDRSDRC_LPR]
+        str     tmp1, [sdramc, #AT91_DDRSDRC_LPR]
        /* if we use the second ram controller */
-        cmp     r5, #0
+        cmp     ramc1, #0
-        ldrne   r4, .saved_sam9_lpr1
+        ldrne   tmp2, .saved_sam9_lpr1
-        strne   r4, [r5, #AT91_DDRSDRC_LPR]
+        strne   tmp2, [ramc1, #AT91_DDRSDRC_LPR]
+        b       ram_restored
-#else
+        /*
+         * SDRAMC Memory controller
+         */
+sdr_en_restore:
        /* Restore LPR on AT91 with SDRAM */
-        ldr     r3, .saved_sam9_lpr
+        ldr     tmp1, .saved_sam9_lpr
-        str     r3, [r2, #AT91_SDRAMC_LPR]
+        str     tmp1, [sdramc, #AT91_SDRAMC_LPR]
-#endif
+ram_restored:
        /* Restore registers, and return */
-        ldmfd   sp!, {r0 - r12, pc}
+        ldmfd   sp!, {r4 - r12, pc}
 .saved_mckr:
@@ -296,26 +328,5 @@ ENTRY(at91_slow_clock)
 .saved_sam9_lpr1:
        .word 0
-.at91_va_base_pmc:
-        .word AT91_VA_BASE_SYS + AT91_PMC
-#ifdef CONFIG_ARCH_AT91RM9200
-.at91_va_base_sdramc:
-        .word AT91_VA_BASE_SYS
-#elif defined(CONFIG_ARCH_AT91SAM9G45)
-.at91_va_base_sdramc:
-        .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
-#else
-.at91_va_base_sdramc:
-        .word AT91_VA_BASE_SYS + AT91_SDRAMC0
-#endif
-.at91_va_base_ramc1:
-#if defined(CONFIG_ARCH_AT91SAM9G45)
-        .word AT91_VA_BASE_SYS + AT91_DDRSDRC1
-#else
-        .word 0
-#endif
 ENTRY(at91_slow_clock_sz)
        .word .-at91_slow_clock
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 620c67e8f814..372396c2ecb6 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -276,6 +276,15 @@ void __init at91_ioremap_rstc(u32 base_addr)
                panic("Impossible to ioremap at91_rstc_base\n");
 }
+void __iomem *at91_matrix_base;
+void __init at91_ioremap_matrix(u32 base_addr)
+{
+        at91_matrix_base = ioremap(base_addr, 512);
+        if (!at91_matrix_base)
+                panic("Impossible to ioremap at91_matrix_base\n");
+}
 void __init at91_initialize(unsigned long main_clock)
 {
        at91_boot_soc.ioremap_registers();
author	Linus Torvalds <torvalds@linux-foundation.org>	2012-03-27 19:47:35 -0400
committer	Linus Torvalds <torvalds@linux-foundation.org>	2012-03-27 19:47:35 -0400
commit	66f03c614c0902ccf7d6160459362a9352f33271 (patch)
tree	b9a8864efe5aa7fc5c96cc5ccbeca41f5cd6f6a7 /arch/arm/mach-at91
parent	34800598b2eebe061445216473b1e4c2ff5cba99 (diff)
parent	cdc3df6f44f72c5924a16a47e1663c3fb0e57820 (diff)