Merge tag 'imx-dt-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt

From Shawn Guo:
The imx device tree changes for 3.10:

* The huge diff stat is introduced by the pinctrl changes.  With DTC
  macro support ready, we're moving those huge mount of data about pins
  out of pinctrl driver.
* Device tree source updates for GPI, LDB, SRC, cpufreq-cpu0.
* Initial imx6dl device tree support
* Board level DTS changes for some imx27 and imx51 platforms.

* tag 'imx-dt-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6: (605 commits)
  ARM: dts: imx6dl-wandboard: Add USB Host support
  ARM: dts: imx51 cpu node
  ARM: dts: Add missing imx27-phytec-phycore dtb target
  ARM: dts: Add NFC support for i.MX27 Phytec PCM038 module
  ARM: i.MX51: Add PATA support
  ARM: dts: Add initial support for Wandboard Dual-Lite
  ARM: dts: imx: add initial imx6dl-sabreauto support
  ARM: dts: imx: add initial imx6dl-sabresd support
  ARM: dts: imx: make sabreauto and sabresd common
  pinctrl: add pinctrl driver for imx6sl
  pinctrl: add pinctrl driver for imx6dl
  ARM: dts: imx53: fix SD2_DATA1 pad AUDMUX_AUD4 configuration
  ARM: dts: MicroSys sbc6x support (i.MX6)
  ARM i.MX5: Add System Reset Controller (SRC) support for i.MX51 and i.MX53
  ARM i.MX5: Add system reset controller (SRC) to i.MX51 and i.MX53 device tree
  ARM i.MX6q: Link system reset controller (SRC) to IPU in DT
  ARM i.MX6q: Add LDB device to device tree
  ARM: imx5 DT init cpufreq-cpu0 device
  ARM: imx27 DT init cpufreq-cpu0 device
  ARM i.MX53: Add LDB device to device tree
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>

3 files changed, 24 insertions, 14 deletions

diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index eed465ab0dd7..5fc23771c154 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -209,6 +209,14 @@ extern int at91_get_gpio_value(unsigned pin);
 extern void at91_gpio_suspend(void);
 extern void at91_gpio_resume(void);
 
+#ifdef CONFIG_PINCTRL_AT91
+extern void at91_pinctrl_gpio_suspend(void);
+extern void at91_pinctrl_gpio_resume(void);
+#else
+static inline void at91_pinctrl_gpio_suspend(void) {}
+static inline void at91_pinctrl_gpio_resume(void) {}
+#endif
+
 #endif  /* __ASSEMBLY__ */
 
 #endif
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index 8e210262aeee..e0ca59171022 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -92,23 +92,21 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value)
 
 void at91_irq_suspend(void)
 {
-        int i = 0, bit;
+        int bit = -1;
 
         if (has_aic5()) {
                 /* disable enabled irqs */
-                while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) {
+                while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
                         at91_aic_write(AT91_AIC5_SSR,
                                        bit & AT91_AIC5_INTSEL_MSK);
                         at91_aic_write(AT91_AIC5_IDCR, 1);
-                        i = bit;
                 }
                 /* enable wakeup irqs */
-                i = 0;
-                while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) {
+                bit = -1;
+                while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
                         at91_aic_write(AT91_AIC5_SSR,
                                        bit & AT91_AIC5_INTSEL_MSK);
                         at91_aic_write(AT91_AIC5_IECR, 1);
-                        i = bit;
                 }
         } else {
                 at91_aic_write(AT91_AIC_IDCR, *backups);
@@ -118,23 +116,21 @@ void at91_irq_suspend(void)
 
 void at91_irq_resume(void)
 {
-        int i = 0, bit;
+        int bit = -1;
 
         if (has_aic5()) {
                 /* disable wakeup irqs */
-                while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) {
+                while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
                         at91_aic_write(AT91_AIC5_SSR,
                                        bit & AT91_AIC5_INTSEL_MSK);
                         at91_aic_write(AT91_AIC5_IDCR, 1);
-                        i = bit;
                 }
                 /* enable irqs disabled for suspend */
-                i = 0;
-                while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) {
+                bit = -1;
+                while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
                         at91_aic_write(AT91_AIC5_SSR,
                                        bit & AT91_AIC5_INTSEL_MSK);
                         at91_aic_write(AT91_AIC5_IECR, 1);
-                        i = bit;
                 }
         } else {
                 at91_aic_write(AT91_AIC_IDCR, *wakeups);
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index adb6db888a1f..73f1f250403a 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -201,7 +201,10 @@ extern u32 at91_slow_clock_sz;
 
 static int at91_pm_enter(suspend_state_t state)
 {
-        at91_gpio_suspend();
+        if (of_have_populated_dt())
+                at91_pinctrl_gpio_suspend();
+        else
+                at91_gpio_suspend();
         at91_irq_suspend();
 
         pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
@@ -286,7 +289,10 @@ static int at91_pm_enter(suspend_state_t state)
 error:
         target_state = PM_SUSPEND_ON;
         at91_irq_resume();
-        at91_gpio_resume();
+        if (of_have_populated_dt())
+                at91_pinctrl_gpio_resume();
+        else
+                at91_gpio_resume();
         return 0;
 }