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authorGreg Ungerer <gerg@snapgear.com>2010-09-21 06:39:40 -0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2010-10-07 13:56:54 -0400
commitcb809b1a5ebffca8cf0314b788919989e8e4ab5f (patch)
treefec437f53dbc5dd30b7289415ce731ec5db1b5f2 /arch/arm/mach-at91
parenta6e016f19d393fbe4e040bee8155b03b840fa689 (diff)
AT91: fix use of clock disable on idle for AT91x40 devices
The simpler AT91x40 processors do not have the same power management controller as the new AT91 devices. They do have a simpler power controller module that we can use to disable the CPU clock at idle time. Add code to support that. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/include/mach/at91x40.h6
-rw-r--r--arch/arm/mach-at91/include/mach/system.h4
2 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
index d34cdb8abdca..063ac44a0204 100644
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -52,4 +52,10 @@
52#define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */ 52#define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */
53#define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */ 53#define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */
54 54
55/*
56 * Support defines for the simple Power Controller module.
57 */
58#define AT91_PS_CR (AT91_PS + 0) /* PS Control register */
59#define AT91_PS_CR_CPU (1 << 0) /* CPU clock disable bit */
60
55#endif /* AT91X40_H */ 61#endif /* AT91X40_H */
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h
index c80e090b3670..bfbb612265d6 100644
--- a/arch/arm/mach-at91/include/mach/system.h
+++ b/arch/arm/mach-at91/include/mach/system.h
@@ -33,7 +33,11 @@ static inline void arch_idle(void)
33 * Disable the processor clock. The processor will be automatically 33 * Disable the processor clock. The processor will be automatically
34 * re-enabled by an interrupt or by a reset. 34 * re-enabled by an interrupt or by a reset.
35 */ 35 */
36#ifdef AT91_PS
37 at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
38#else
36 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); 39 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
40#endif
37#else 41#else
38 /* 42 /*
39 * Set the processor (CP15) into 'Wait for Interrupt' mode. 43 * Set the processor (CP15) into 'Wait for Interrupt' mode.