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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2011-09-18 10:29:50 -0400
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2011-11-28 09:50:38 -0500
commit4ab0c5998d327cba5b7e0dc8ce67f45859997669 (patch)
tree8e785004e227fa4572a0c459fbde72aa07ddcdfc /arch/arm/mach-at91
parentcfa5a1fe7e65bacdee59d5df60a9f44b0c030532 (diff)
ARM: at91: make pit register base soc independent
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/at91cap9.c1
-rw-r--r--arch/arm/mach-at91/at91sam9260.c1
-rw-r--r--arch/arm/mach-at91/at91sam9261.c1
-rw-r--r--arch/arm/mach-at91/at91sam9263.c1
-rw-r--r--arch/arm/mach-at91/at91sam926x_time.c38
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c1
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c1
-rw-r--r--arch/arm/mach-at91/generic.h1
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pit.h8
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl.h2
15 files changed, 45 insertions, 20 deletions
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index 36872070afef..abfe36858a01 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -335,6 +335,7 @@ static void __init at91cap9_map_io(void)
335 335
336static void __init at91cap9_ioremap_registers(void) 336static void __init at91cap9_ioremap_registers(void)
337{ 337{
338 at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
338} 339}
339 340
340static void __init at91cap9_initialize(void) 341static void __init at91cap9_initialize(void)
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 0e549284b127..0030d5f16ed8 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -327,6 +327,7 @@ static void __init at91sam9260_map_io(void)
327 327
328static void __init at91sam9260_ioremap_registers(void) 328static void __init at91sam9260_ioremap_registers(void)
329{ 329{
330 at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
330} 331}
331 332
332static void __init at91sam9260_initialize(void) 333static void __init at91sam9260_initialize(void)
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index dde831814737..348d5ae4dee2 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -287,6 +287,7 @@ static void __init at91sam9261_map_io(void)
287 287
288static void __init at91sam9261_ioremap_registers(void) 288static void __init at91sam9261_ioremap_registers(void)
289{ 289{
290 at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
290} 291}
291 292
292static void __init at91sam9261_initialize(void) 293static void __init at91sam9261_initialize(void)
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index fc442dd0753c..09ccf734c7d7 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -305,6 +305,7 @@ static void __init at91sam9263_map_io(void)
305 305
306static void __init at91sam9263_ioremap_registers(void) 306static void __init at91sam9263_ioremap_registers(void)
307{ 307{
308 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
308} 309}
309 310
310static void __init at91sam9263_initialize(void) 311static void __init at91sam9263_initialize(void)
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 4ba85499fa97..d89ead740a99 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -25,7 +25,17 @@
25 25
26static u32 pit_cycle; /* write-once */ 26static u32 pit_cycle; /* write-once */
27static u32 pit_cnt; /* access only w/system irq blocked */ 27static u32 pit_cnt; /* access only w/system irq blocked */
28static void __iomem *pit_base_addr __read_mostly;
28 29
30static inline unsigned int pit_read(unsigned int reg_offset)
31{
32 return __raw_readl(pit_base_addr + reg_offset);
33}
34
35static inline void pit_write(unsigned int reg_offset, unsigned long value)
36{
37 __raw_writel(value, pit_base_addr + reg_offset);
38}
29 39
30/* 40/*
31 * Clocksource: just a monotonic counter of MCK/16 cycles. 41 * Clocksource: just a monotonic counter of MCK/16 cycles.
@@ -39,7 +49,7 @@ static cycle_t read_pit_clk(struct clocksource *cs)
39 49
40 raw_local_irq_save(flags); 50 raw_local_irq_save(flags);
41 elapsed = pit_cnt; 51 elapsed = pit_cnt;
42 t = at91_sys_read(AT91_PIT_PIIR); 52 t = pit_read(AT91_PIT_PIIR);
43 raw_local_irq_restore(flags); 53 raw_local_irq_restore(flags);
44 54
45 elapsed += PIT_PICNT(t) * pit_cycle; 55 elapsed += PIT_PICNT(t) * pit_cycle;
@@ -64,8 +74,8 @@ pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
64 switch (mode) { 74 switch (mode) {
65 case CLOCK_EVT_MODE_PERIODIC: 75 case CLOCK_EVT_MODE_PERIODIC:
66 /* update clocksource counter */ 76 /* update clocksource counter */
67 pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); 77 pit_cnt += pit_cycle * PIT_PICNT(pit_read(AT91_PIT_PIVR));
68 at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN 78 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
69 | AT91_PIT_PITIEN); 79 | AT91_PIT_PITIEN);
70 break; 80 break;
71 case CLOCK_EVT_MODE_ONESHOT: 81 case CLOCK_EVT_MODE_ONESHOT:
@@ -74,7 +84,7 @@ pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
74 case CLOCK_EVT_MODE_SHUTDOWN: 84 case CLOCK_EVT_MODE_SHUTDOWN:
75 case CLOCK_EVT_MODE_UNUSED: 85 case CLOCK_EVT_MODE_UNUSED:
76 /* disable irq, leaving the clocksource active */ 86 /* disable irq, leaving the clocksource active */
77 at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); 87 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
78 break; 88 break;
79 case CLOCK_EVT_MODE_RESUME: 89 case CLOCK_EVT_MODE_RESUME:
80 break; 90 break;
@@ -103,11 +113,11 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
103 113
104 /* The PIT interrupt may be disabled, and is shared */ 114 /* The PIT interrupt may be disabled, and is shared */
105 if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC) 115 if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
106 && (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)) { 116 && (pit_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
107 unsigned nr_ticks; 117 unsigned nr_ticks;
108 118
109 /* Get number of ticks performed before irq, and ack it */ 119 /* Get number of ticks performed before irq, and ack it */
110 nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); 120 nr_ticks = PIT_PICNT(pit_read(AT91_PIT_PIVR));
111 do { 121 do {
112 pit_cnt += pit_cycle; 122 pit_cnt += pit_cycle;
113 pit_clkevt.event_handler(&pit_clkevt); 123 pit_clkevt.event_handler(&pit_clkevt);
@@ -129,14 +139,14 @@ static struct irqaction at91sam926x_pit_irq = {
129static void at91sam926x_pit_reset(void) 139static void at91sam926x_pit_reset(void)
130{ 140{
131 /* Disable timer and irqs */ 141 /* Disable timer and irqs */
132 at91_sys_write(AT91_PIT_MR, 0); 142 pit_write(AT91_PIT_MR, 0);
133 143
134 /* Clear any pending interrupts, wait for PIT to stop counting */ 144 /* Clear any pending interrupts, wait for PIT to stop counting */
135 while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0) 145 while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0)
136 cpu_relax(); 146 cpu_relax();
137 147
138 /* Start PIT but don't enable IRQ */ 148 /* Start PIT but don't enable IRQ */
139 at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); 149 pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
140} 150}
141 151
142/* 152/*
@@ -178,7 +188,15 @@ static void __init at91sam926x_pit_init(void)
178static void at91sam926x_pit_suspend(void) 188static void at91sam926x_pit_suspend(void)
179{ 189{
180 /* Disable timer */ 190 /* Disable timer */
181 at91_sys_write(AT91_PIT_MR, 0); 191 pit_write(AT91_PIT_MR, 0);
192}
193
194void __init at91sam926x_ioremap_pit(u32 addr)
195{
196 pit_base_addr = ioremap(addr, 16);
197
198 if (!pit_base_addr)
199 panic("Impossible to ioremap PIT\n");
182} 200}
183 201
184struct sys_timer at91sam926x_timer = { 202struct sys_timer at91sam926x_timer = {
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 56282b26a5a2..aa8b4414f3ed 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -340,6 +340,7 @@ static void __init at91sam9g45_map_io(void)
340 340
341static void __init at91sam9g45_ioremap_registers(void) 341static void __init at91sam9g45_ioremap_registers(void)
342{ 342{
343 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
343} 344}
344 345
345static void __init at91sam9g45_initialize(void) 346static void __init at91sam9g45_initialize(void)
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 29dae9b275b0..291fc9983cc3 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -292,6 +292,7 @@ static void __init at91sam9rl_map_io(void)
292 292
293static void __init at91sam9rl_ioremap_registers(void) 293static void __init at91sam9rl_ioremap_registers(void)
294{ 294{
295 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
295} 296}
296 297
297static void __init at91sam9rl_initialize(void) 298static void __init at91sam9rl_initialize(void)
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 11d7297eee22..8196ecc37ed2 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -29,6 +29,7 @@ extern void __init at91_aic_init(unsigned int priority[]);
29 /* Timer */ 29 /* Timer */
30struct sys_timer; 30struct sys_timer;
31extern struct sys_timer at91rm9200_timer; 31extern struct sys_timer at91rm9200_timer;
32extern void at91sam926x_ioremap_pit(u32 addr);
32extern struct sys_timer at91sam926x_timer; 33extern struct sys_timer at91sam926x_timer;
33extern struct sys_timer at91x40_timer; 34extern struct sys_timer at91x40_timer;
34 35
diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h
index 974d0bd05b5b..d1f80ad7f4d4 100644
--- a/arch/arm/mach-at91/include/mach/at91_pit.h
+++ b/arch/arm/mach-at91/include/mach/at91_pit.h
@@ -16,16 +16,16 @@
16#ifndef AT91_PIT_H 16#ifndef AT91_PIT_H
17#define AT91_PIT_H 17#define AT91_PIT_H
18 18
19#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ 19#define AT91_PIT_MR 0x00 /* Mode Register */
20#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ 20#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
21#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ 21#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
22#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ 22#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
23 23
24#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ 24#define AT91_PIT_SR 0x04 /* Status Register */
25#define AT91_PIT_PITS (1 << 0) /* Timer Status */ 25#define AT91_PIT_PITS (1 << 0) /* Timer Status */
26 26
27#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ 27#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
28#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ 28#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
29#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ 29#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
30#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ 30#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
31 31
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index 1cb42a63c822..ad8d298cf8ba 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -89,7 +89,6 @@
89#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 89#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
90#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 90#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
91#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 91#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
92#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
93#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 92#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
94#define AT91_GPBR (cpu_is_at91cap9_revB() ? \ 93#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
95 (0xfffffd50 - AT91_BASE_SYS) : \ 94 (0xfffffd50 - AT91_BASE_SYS) : \
@@ -102,6 +101,7 @@
102#define AT91CAP9_BASE_PIOC 0xfffff600 101#define AT91CAP9_BASE_PIOC 0xfffff600
103#define AT91CAP9_BASE_PIOD 0xfffff800 102#define AT91CAP9_BASE_PIOD 0xfffff800
104#define AT91CAP9_BASE_RTT 0xfffffd20 103#define AT91CAP9_BASE_RTT 0xfffffd20
104#define AT91CAP9_BASE_PIT 0xfffffd30
105 105
106#define AT91_USART0 AT91CAP9_BASE_US0 106#define AT91_USART0 AT91CAP9_BASE_US0
107#define AT91_USART1 AT91CAP9_BASE_US1 107#define AT91_USART1 AT91CAP9_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 6aa7ca979e4d..b8c85dc4abce 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -89,7 +89,6 @@
89#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 89#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
90#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 90#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
91#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 91#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
92#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
93#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 92#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
94#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 93#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
95 94
@@ -98,6 +97,7 @@
98#define AT91SAM9260_BASE_PIOB 0xfffff600 97#define AT91SAM9260_BASE_PIOB 0xfffff600
99#define AT91SAM9260_BASE_PIOC 0xfffff800 98#define AT91SAM9260_BASE_PIOC 0xfffff800
100#define AT91SAM9260_BASE_RTT 0xfffffd20 99#define AT91SAM9260_BASE_RTT 0xfffffd20
100#define AT91SAM9260_BASE_PIT 0xfffffd30
101 101
102#define AT91_USART0 AT91SAM9260_BASE_US0 102#define AT91_USART0 AT91SAM9260_BASE_US0
103#define AT91_USART1 AT91SAM9260_BASE_US1 103#define AT91_USART1 AT91SAM9260_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index f84b7132cb79..0dccaff5212e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -73,7 +73,6 @@
73#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 73#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
74#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 74#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
75#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 75#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
76#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
77#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 76#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
78#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) 77#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
79 78
@@ -81,6 +80,7 @@
81#define AT91SAM9261_BASE_PIOB 0xfffff600 80#define AT91SAM9261_BASE_PIOB 0xfffff600
82#define AT91SAM9261_BASE_PIOC 0xfffff800 81#define AT91SAM9261_BASE_PIOC 0xfffff800
83#define AT91SAM9261_BASE_RTT 0xfffffd20 82#define AT91SAM9261_BASE_RTT 0xfffffd20
83#define AT91SAM9261_BASE_PIT 0xfffffd30
84 84
85#define AT91_USART0 AT91SAM9261_BASE_US0 85#define AT91_USART0 AT91SAM9261_BASE_US0
86#define AT91_USART1 AT91SAM9261_BASE_US1 86#define AT91_USART1 AT91SAM9261_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 938965ebe775..735408e6d2e6 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -85,7 +85,6 @@
85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 85#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
86#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 86#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
87#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 87#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
88#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
89#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 88#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
90#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 89#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
91 90
@@ -97,6 +96,7 @@
97#define AT91SAM9263_BASE_PIOD 0xfffff800 96#define AT91SAM9263_BASE_PIOD 0xfffff800
98#define AT91SAM9263_BASE_PIOE 0xfffffa00 97#define AT91SAM9263_BASE_PIOE 0xfffffa00
99#define AT91SAM9263_BASE_RTT0 0xfffffd20 98#define AT91SAM9263_BASE_RTT0 0xfffffd20
99#define AT91SAM9263_BASE_PIT 0xfffffd30
100#define AT91SAM9263_BASE_RTT1 0xfffffd50 100#define AT91SAM9263_BASE_RTT1 0xfffffd50
101 101
102#define AT91_USART0 AT91SAM9263_BASE_US0 102#define AT91_USART0 AT91SAM9263_BASE_US0
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 00638c6a65fd..ba609f3872fd 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -95,7 +95,6 @@
95#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 95#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
96#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 96#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
97#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 97#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
98#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
99#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 98#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
100#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 99#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
101#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) 100#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS)
@@ -108,6 +107,7 @@
108#define AT91SAM9G45_BASE_PIOD 0xfffff800 107#define AT91SAM9G45_BASE_PIOD 0xfffff800
109#define AT91SAM9G45_BASE_PIOE 0xfffffa00 108#define AT91SAM9G45_BASE_PIOE 0xfffffa00
110#define AT91SAM9G45_BASE_RTT 0xfffffd20 109#define AT91SAM9G45_BASE_RTT 0xfffffd20
110#define AT91SAM9G45_BASE_PIT 0xfffffd30
111 111
112#define AT91_USART0 AT91SAM9G45_BASE_US0 112#define AT91_USART0 AT91SAM9G45_BASE_US0
113#define AT91_USART1 AT91SAM9G45_BASE_US1 113#define AT91_USART1 AT91SAM9G45_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index 099cefc20bf0..bab09a745d2b 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -78,7 +78,6 @@
78#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) 78#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
79#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) 79#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
80#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) 80#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
81#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
82#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) 81#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
83#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) 82#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
84#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) 83#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
@@ -91,6 +90,7 @@
91#define AT91SAM9RL_BASE_PIOC 0xfffff800 90#define AT91SAM9RL_BASE_PIOC 0xfffff800
92#define AT91SAM9RL_BASE_PIOD 0xfffffa00 91#define AT91SAM9RL_BASE_PIOD 0xfffffa00
93#define AT91SAM9RL_BASE_RTT 0xfffffd20 92#define AT91SAM9RL_BASE_RTT 0xfffffd20
93#define AT91SAM9RL_BASE_PIT 0xfffffd30
94 94
95#define AT91_USART0 AT91SAM9RL_BASE_US0 95#define AT91_USART0 AT91SAM9RL_BASE_US0
96#define AT91_USART1 AT91SAM9RL_BASE_US1 96#define AT91_USART1 AT91SAM9RL_BASE_US1
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 19:33:01 -0500