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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2011-04-22 22:52:16 -0400
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2011-04-22 23:03:07 -0400
commit9baeb7e47aed8e399d15d2ea8c032efe3680f20b (patch)
tree7a6ad2fa820cf9ff1ee41613cf03997fb58a58cf /arch/arm/mach-at91
parent91a2f4d3cd2a2f1a2c6830896bd2403ca0130137 (diff)
at91: Add ARCH_ID and basic cpu macros definition for 5series chips family.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91')
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h28
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 3bef931d0b1c..0700f2125305 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -27,6 +27,7 @@
27#define ARCH_ID_AT91SAM9G45 0x819b05a0 27#define ARCH_ID_AT91SAM9G45 0x819b05a0
28#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */ 28#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
29#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ 29#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
30#define ARCH_ID_AT91SAM9X5 0x819a05a0
30#define ARCH_ID_AT91CAP9 0x039A03A0 31#define ARCH_ID_AT91CAP9 0x039A03A0
31 32
32#define ARCH_ID_AT91SAM9XE128 0x329973a0 33#define ARCH_ID_AT91SAM9XE128 0x329973a0
@@ -55,6 +56,12 @@ static inline unsigned long at91_cpu_fully_identify(void)
55#define ARCH_EXID_AT91SAM9G46 0x00000003 56#define ARCH_EXID_AT91SAM9G46 0x00000003
56#define ARCH_EXID_AT91SAM9G45 0x00000004 57#define ARCH_EXID_AT91SAM9G45 0x00000004
57 58
59#define ARCH_EXID_AT91SAM9G15 0x00000000
60#define ARCH_EXID_AT91SAM9G35 0x00000001
61#define ARCH_EXID_AT91SAM9X35 0x00000002
62#define ARCH_EXID_AT91SAM9G25 0x00000003
63#define ARCH_EXID_AT91SAM9X25 0x00000004
64
58static inline unsigned long at91_exid_identify(void) 65static inline unsigned long at91_exid_identify(void)
59{ 66{
60 return at91_sys_read(AT91_DBGU_EXID); 67 return at91_sys_read(AT91_DBGU_EXID);
@@ -143,6 +150,27 @@ static inline unsigned long at91cap9_rev_identify(void)
143#define cpu_is_at91sam9m11() (0) 150#define cpu_is_at91sam9m11() (0)
144#endif 151#endif
145 152
153#ifdef CONFIG_ARCH_AT91SAM9X5
154#define cpu_is_at91sam9x5() (at91_cpu_identify() == ARCH_ID_AT91SAM9X5)
155#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \
156 (at91_exid_identify() == ARCH_EXID_AT91SAM9G15))
157#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \
158 (at91_exid_identify() == ARCH_EXID_AT91SAM9G35))
159#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \
160 (at91_exid_identify() == ARCH_EXID_AT91SAM9X35))
161#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \
162 (at91_exid_identify() == ARCH_EXID_AT91SAM9G25))
163#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \
164 (at91_exid_identify() == ARCH_EXID_AT91SAM9X25))
165#else
166#define cpu_is_at91sam9x5() (0)
167#define cpu_is_at91sam9g15() (0)
168#define cpu_is_at91sam9g35() (0)
169#define cpu_is_at91sam9x35() (0)
170#define cpu_is_at91sam9g25() (0)
171#define cpu_is_at91sam9x25() (0)
172#endif
173
146#ifdef CONFIG_ARCH_AT91CAP9 174#ifdef CONFIG_ARCH_AT91CAP9
147#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9) 175#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9)
148#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B) 176#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B)