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authorLinus Torvalds <torvalds@linux-foundation.org>2014-01-23 21:36:55 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-01-23 21:36:55 -0500
commitf2c73464d7b399cf4e0c601c1c7d7b079080fa52 (patch)
tree902decd0c280757075bce5068fee679e0ccc261e /arch/arm/mach-at91/sama5d3.c
parent93abdb7785503c269e73e811f3c7fd23a9243b14 (diff)
parent273c2279ca502267fac40bcaecb35942380c429c (diff)
Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Olof Johansson: "This is the branch where we usually queue up cleanup efforts, moving drivers out of the architecture directory, header file restructuring, etc. Sometimes they tangle with new development so it's hard to keep it strictly to cleanups. Some of the things included in this branch are: * Atmel SAMA5 conversion to common clock * Reset framework conversion for tegra platforms - Some of this depends on tegra clock driver reworks that are shared with Mike Turquette's clk tree. * Tegra DMA refactoring, which are shared branches with the DMA tree. * Removal of some header files on exynos to prepare for multiplatform" * tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (169 commits) ARM: mvebu: move Armada 370/XP specific definitions to armada-370-xp.h ARM: mvebu: remove prototypes of non-existing functions from common.h ARM: mvebu: move ARMADA_XP_MAX_CPUS to armada-370-xp.h serial: sh-sci: Rework baud rate calculation serial: sh-sci: Compute overrun_bit without using baud rate algo serial: sh-sci: Remove unused GPIO request code serial: sh-sci: Move overrun_bit and error_mask fields out of pdata serial: sh-sci: Support resources passed through platform resources serial: sh-sci: Don't check IRQ in verify port operation serial: sh-sci: Set the UPF_FIXED_PORT flag serial: sh-sci: Remove duplicate interrupt check in verify port op serial: sh-sci: Simplify baud rate calculation algorithms serial: sh-sci: Remove baud rate calculation algorithm 5 serial: sh-sci: Sort headers alphabetically ARM: EXYNOS: Kill exynos_pm_late_initcall() ARM: EXYNOS: Consolidate selection of PM_GENERIC_DOMAINS for Exynos4 ARM: at91: switch Calao QIL-A9260 board to DT clk: at91: fix pmc_clk_ids data type attriubte PM / devfreq: use inclusion <mach/map.h> instead of <plat/map-s5p.h> ARM: EXYNOS: remove <mach/regs-clock.h> for exynos ...
Diffstat (limited to 'arch/arm/mach-at91/sama5d3.c')
-rw-r--r--arch/arm/mach-at91/sama5d3.c344
1 files changed, 1 insertions, 343 deletions
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index a28873fe3049..3d775d08de08 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -9,360 +9,19 @@
9 9
10#include <linux/module.h> 10#include <linux/module.h>
11#include <linux/dma-mapping.h> 11#include <linux/dma-mapping.h>
12#include <linux/clk/at91_pmc.h>
12 13
13#include <asm/irq.h> 14#include <asm/irq.h>
14#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
15#include <asm/mach/map.h> 16#include <asm/mach/map.h>
16#include <mach/sama5d3.h> 17#include <mach/sama5d3.h>
17#include <mach/at91_pmc.h>
18#include <mach/cpu.h> 18#include <mach/cpu.h>
19 19
20#include "soc.h" 20#include "soc.h"
21#include "generic.h" 21#include "generic.h"
22#include "clock.h"
23#include "sam9_smc.h" 22#include "sam9_smc.h"
24 23
25/* -------------------------------------------------------------------- 24/* --------------------------------------------------------------------
26 * Clocks
27 * -------------------------------------------------------------------- */
28
29/*
30 * The peripheral clocks.
31 */
32
33static struct clk pioA_clk = {
34 .name = "pioA_clk",
35 .pid = SAMA5D3_ID_PIOA,
36 .type = CLK_TYPE_PERIPHERAL,
37};
38static struct clk pioB_clk = {
39 .name = "pioB_clk",
40 .pid = SAMA5D3_ID_PIOB,
41 .type = CLK_TYPE_PERIPHERAL,
42};
43static struct clk pioC_clk = {
44 .name = "pioC_clk",
45 .pid = SAMA5D3_ID_PIOC,
46 .type = CLK_TYPE_PERIPHERAL,
47};
48static struct clk pioD_clk = {
49 .name = "pioD_clk",
50 .pid = SAMA5D3_ID_PIOD,
51 .type = CLK_TYPE_PERIPHERAL,
52};
53static struct clk pioE_clk = {
54 .name = "pioE_clk",
55 .pid = SAMA5D3_ID_PIOE,
56 .type = CLK_TYPE_PERIPHERAL,
57};
58static struct clk usart0_clk = {
59 .name = "usart0_clk",
60 .pid = SAMA5D3_ID_USART0,
61 .type = CLK_TYPE_PERIPHERAL,
62 .div = AT91_PMC_PCR_DIV2,
63};
64static struct clk usart1_clk = {
65 .name = "usart1_clk",
66 .pid = SAMA5D3_ID_USART1,
67 .type = CLK_TYPE_PERIPHERAL,
68 .div = AT91_PMC_PCR_DIV2,
69};
70static struct clk usart2_clk = {
71 .name = "usart2_clk",
72 .pid = SAMA5D3_ID_USART2,
73 .type = CLK_TYPE_PERIPHERAL,
74 .div = AT91_PMC_PCR_DIV2,
75};
76static struct clk usart3_clk = {
77 .name = "usart3_clk",
78 .pid = SAMA5D3_ID_USART3,
79 .type = CLK_TYPE_PERIPHERAL,
80 .div = AT91_PMC_PCR_DIV2,
81};
82static struct clk uart0_clk = {
83 .name = "uart0_clk",
84 .pid = SAMA5D3_ID_UART0,
85 .type = CLK_TYPE_PERIPHERAL,
86 .div = AT91_PMC_PCR_DIV2,
87};
88static struct clk uart1_clk = {
89 .name = "uart1_clk",
90 .pid = SAMA5D3_ID_UART1,
91 .type = CLK_TYPE_PERIPHERAL,
92 .div = AT91_PMC_PCR_DIV2,
93};
94static struct clk twi0_clk = {
95 .name = "twi0_clk",
96 .pid = SAMA5D3_ID_TWI0,
97 .type = CLK_TYPE_PERIPHERAL,
98 .div = AT91_PMC_PCR_DIV8,
99};
100static struct clk twi1_clk = {
101 .name = "twi1_clk",
102 .pid = SAMA5D3_ID_TWI1,
103 .type = CLK_TYPE_PERIPHERAL,
104 .div = AT91_PMC_PCR_DIV8,
105};
106static struct clk twi2_clk = {
107 .name = "twi2_clk",
108 .pid = SAMA5D3_ID_TWI2,
109 .type = CLK_TYPE_PERIPHERAL,
110 .div = AT91_PMC_PCR_DIV8,
111};
112static struct clk mmc0_clk = {
113 .name = "mci0_clk",
114 .pid = SAMA5D3_ID_HSMCI0,
115 .type = CLK_TYPE_PERIPHERAL,
116};
117static struct clk mmc1_clk = {
118 .name = "mci1_clk",
119 .pid = SAMA5D3_ID_HSMCI1,
120 .type = CLK_TYPE_PERIPHERAL,
121};
122static struct clk mmc2_clk = {
123 .name = "mci2_clk",
124 .pid = SAMA5D3_ID_HSMCI2,
125 .type = CLK_TYPE_PERIPHERAL,
126};
127static struct clk spi0_clk = {
128 .name = "spi0_clk",
129 .pid = SAMA5D3_ID_SPI0,
130 .type = CLK_TYPE_PERIPHERAL,
131};
132static struct clk spi1_clk = {
133 .name = "spi1_clk",
134 .pid = SAMA5D3_ID_SPI1,
135 .type = CLK_TYPE_PERIPHERAL,
136};
137static struct clk tcb0_clk = {
138 .name = "tcb0_clk",
139 .pid = SAMA5D3_ID_TC0,
140 .type = CLK_TYPE_PERIPHERAL,
141 .div = AT91_PMC_PCR_DIV2,
142};
143static struct clk tcb1_clk = {
144 .name = "tcb1_clk",
145 .pid = SAMA5D3_ID_TC1,
146 .type = CLK_TYPE_PERIPHERAL,
147 .div = AT91_PMC_PCR_DIV2,
148};
149static struct clk adc_clk = {
150 .name = "adc_clk",
151 .pid = SAMA5D3_ID_ADC,
152 .type = CLK_TYPE_PERIPHERAL,
153 .div = AT91_PMC_PCR_DIV2,
154};
155static struct clk adc_op_clk = {
156 .name = "adc_op_clk",
157 .type = CLK_TYPE_PERIPHERAL,
158 .rate_hz = 5000000,
159};
160static struct clk dma0_clk = {
161 .name = "dma0_clk",
162 .pid = SAMA5D3_ID_DMA0,
163 .type = CLK_TYPE_PERIPHERAL,
164};
165static struct clk dma1_clk = {
166 .name = "dma1_clk",
167 .pid = SAMA5D3_ID_DMA1,
168 .type = CLK_TYPE_PERIPHERAL,
169};
170static struct clk uhphs_clk = {
171 .name = "uhphs",
172 .pid = SAMA5D3_ID_UHPHS,
173 .type = CLK_TYPE_PERIPHERAL,
174};
175static struct clk udphs_clk = {
176 .name = "udphs_clk",
177 .pid = SAMA5D3_ID_UDPHS,
178 .type = CLK_TYPE_PERIPHERAL,
179};
180/* gmac only for sama5d33, sama5d34, sama5d35 */
181static struct clk macb0_clk = {
182 .name = "macb0_clk",
183 .pid = SAMA5D3_ID_GMAC,
184 .type = CLK_TYPE_PERIPHERAL,
185};
186/* emac only for sama5d31, sama5d35 */
187static struct clk macb1_clk = {
188 .name = "macb1_clk",
189 .pid = SAMA5D3_ID_EMAC,
190 .type = CLK_TYPE_PERIPHERAL,
191};
192/* lcd only for sama5d31, sama5d33, sama5d34 */
193static struct clk lcdc_clk = {
194 .name = "lcdc_clk",
195 .pid = SAMA5D3_ID_LCDC,
196 .type = CLK_TYPE_PERIPHERAL,
197};
198/* isi only for sama5d33, sama5d35 */
199static struct clk isi_clk = {
200 .name = "isi_clk",
201 .pid = SAMA5D3_ID_ISI,
202 .type = CLK_TYPE_PERIPHERAL,
203};
204static struct clk can0_clk = {
205 .name = "can0_clk",
206 .pid = SAMA5D3_ID_CAN0,
207 .type = CLK_TYPE_PERIPHERAL,
208 .div = AT91_PMC_PCR_DIV2,
209};
210static struct clk can1_clk = {
211 .name = "can1_clk",
212 .pid = SAMA5D3_ID_CAN1,
213 .type = CLK_TYPE_PERIPHERAL,
214 .div = AT91_PMC_PCR_DIV2,
215};
216static struct clk ssc0_clk = {
217 .name = "ssc0_clk",
218 .pid = SAMA5D3_ID_SSC0,
219 .type = CLK_TYPE_PERIPHERAL,
220 .div = AT91_PMC_PCR_DIV2,
221};
222static struct clk ssc1_clk = {
223 .name = "ssc1_clk",
224 .pid = SAMA5D3_ID_SSC1,
225 .type = CLK_TYPE_PERIPHERAL,
226 .div = AT91_PMC_PCR_DIV2,
227};
228static struct clk sha_clk = {
229 .name = "sha_clk",
230 .pid = SAMA5D3_ID_SHA,
231 .type = CLK_TYPE_PERIPHERAL,
232 .div = AT91_PMC_PCR_DIV8,
233};
234static struct clk aes_clk = {
235 .name = "aes_clk",
236 .pid = SAMA5D3_ID_AES,
237 .type = CLK_TYPE_PERIPHERAL,
238};
239static struct clk tdes_clk = {
240 .name = "tdes_clk",
241 .pid = SAMA5D3_ID_TDES,
242 .type = CLK_TYPE_PERIPHERAL,
243};
244
245static struct clk *periph_clocks[] __initdata = {
246 &pioA_clk,
247 &pioB_clk,
248 &pioC_clk,
249 &pioD_clk,
250 &pioE_clk,
251 &usart0_clk,
252 &usart1_clk,
253 &usart2_clk,
254 &usart3_clk,
255 &uart0_clk,
256 &uart1_clk,
257 &twi0_clk,
258 &twi1_clk,
259 &twi2_clk,
260 &mmc0_clk,
261 &mmc1_clk,
262 &mmc2_clk,
263 &spi0_clk,
264 &spi1_clk,
265 &tcb0_clk,
266 &tcb1_clk,
267 &adc_clk,
268 &adc_op_clk,
269 &dma0_clk,
270 &dma1_clk,
271 &uhphs_clk,
272 &udphs_clk,
273 &macb0_clk,
274 &macb1_clk,
275 &lcdc_clk,
276 &isi_clk,
277 &can0_clk,
278 &can1_clk,
279 &ssc0_clk,
280 &ssc1_clk,
281 &sha_clk,
282 &aes_clk,
283 &tdes_clk,
284};
285
286static struct clk pck0 = {
287 .name = "pck0",
288 .pmc_mask = AT91_PMC_PCK0,
289 .type = CLK_TYPE_PROGRAMMABLE,
290 .id = 0,
291};
292
293static struct clk pck1 = {
294 .name = "pck1",
295 .pmc_mask = AT91_PMC_PCK1,
296 .type = CLK_TYPE_PROGRAMMABLE,
297 .id = 1,
298};
299
300static struct clk pck2 = {
301 .name = "pck2",
302 .pmc_mask = AT91_PMC_PCK2,
303 .type = CLK_TYPE_PROGRAMMABLE,
304 .id = 2,
305};
306
307static struct clk_lookup periph_clocks_lookups[] = {
308 /* lookup table for DT entries */
309 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
310 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
311 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
312 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
313 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk),
314 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk),
315 CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk),
316 CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk),
317 CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk),
318 CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk),
319 CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk),
320 CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk),
321 CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk),
322 CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk),
323 CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk),
324 CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk),
325 CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk),
326 CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk),
327 CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk),
328 CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk),
329 CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk),
330 CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk),
331 CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk),
332 CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
333 CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
334 CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
335 CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
336 CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
337 CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk),
338 CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk),
339 CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk),
340 CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk),
341 CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk),
342 CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk),
343 CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk),
344 CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk),
345 CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk),
346 CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk),
347 CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk),
348};
349
350static void __init sama5d3_register_clocks(void)
351{
352 int i;
353
354 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
355 clk_register(periph_clocks[i]);
356
357 clkdev_add_table(periph_clocks_lookups,
358 ARRAY_SIZE(periph_clocks_lookups));
359
360 clk_register(&pck0);
361 clk_register(&pck1);
362 clk_register(&pck2);
363}
364
365/* --------------------------------------------------------------------
366 * AT91SAM9x5 processor initialization 25 * AT91SAM9x5 processor initialization
367 * -------------------------------------------------------------------- */ 26 * -------------------------------------------------------------------- */
368 27
@@ -378,6 +37,5 @@ static void __init sama5d3_initialize(void)
378 37
379AT91_SOC_START(sama5d3) 38AT91_SOC_START(sama5d3)
380 .map_io = sama5d3_map_io, 39 .map_io = sama5d3_map_io,
381 .register_clocks = sama5d3_register_clocks,
382 .init = sama5d3_initialize, 40 .init = sama5d3_initialize,
383AT91_SOC_END 41AT91_SOC_END
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-28 17:02:47 -0500