ARM: AT91: pm: Factorize standby function

Detect presence of second bank. So we do not need to have on function per SoC

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

1 files changed, 24 insertions, 31 deletions

diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index 76dd1a749ebd..3ed190ce062b 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -49,16 +49,18 @@ static inline void at91rm9200_standby(void)
 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
  * remember.
  */
-static inline void at91sam9g45_standby(void)
+static inline void at91_ddr_standby(void)
 {
         /* Those two values allow us to delay self-refresh activation
          * to the maximum. */
-        u32 lpr0, lpr1;
-        u32 saved_lpr0, saved_lpr1;
+        u32 lpr0, lpr1 = 0;
+        u32 saved_lpr0, saved_lpr1 = 0;
 
-        saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
-        lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
-        lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
+        if (at91_ramc_base[1]) {
+                saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
+                lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
+                lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
+        }
 
         saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
         lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
@@ -66,25 +68,29 @@ static inline void at91sam9g45_standby(void)
 
         /* self-refresh mode now */
         at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
-        at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
+        if (at91_ramc_base[1])
+                at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
 
         cpu_do_idle();
 
         at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
-        at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
+        if (at91_ramc_base[1])
+                at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
 }
 
 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
  * remember.
  */
-static inline void at91sam9263_standby(void)
+static inline void at91sam9_sdram_standby(void)
 {
-        u32 lpr0, lpr1;
-        u32 saved_lpr0, saved_lpr1;
+        u32 lpr0, lpr1 = 0;
+        u32 saved_lpr0, saved_lpr1 = 0;
 
-        saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
-        lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
-        lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
+        if (at91_ramc_base[1]) {
+                saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
+                lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
+                lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
+        }
 
         saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
         lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
@@ -92,27 +98,14 @@ static inline void at91sam9263_standby(void)
 
         /* self-refresh mode now */
         at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
-        at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
+        if (at91_ramc_base[1])
+                at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
 
         cpu_do_idle();
 
         at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
-        at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
-}
-
-static inline void at91sam9_standby(void)
-{
-        u32 saved_lpr, lpr;
-
-        saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
-
-        lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
-        at91_ramc_write(0, AT91_SDRAMC_LPR, lpr |
-                        AT91_SDRAMC_LPCB_SELF_REFRESH);
-
-        cpu_do_idle();
-
-        at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr);
+        if (at91_ramc_base[1])
+                at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
 }
 
 #endif