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authorAlbin Tonnerre <albin.tonnerre@free-electrons.com>2009-11-01 12:40:50 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-11-10 18:46:35 -0500
commit1ea60cf7062271f0d53d09268726aa1544bf4836 (patch)
tree4e975655fa555fd2346ec50112fbbc8244cb03da /arch/arm/mach-at91/pm.c
parentcd3abf98aeaec9b23a926159856b54a95707ee88 (diff)
ARM: 5778/1: AT91: Add cpuidle support
This patch adds the support for cpuidle on AT91 SoCs, taken from the cpuidle support in mach-kirkwood. cpuidle needs sdram_selfrefresh_enable and _disable, so move their definition to a separate header file instead of duplicating the code already used in pm.c. Tested-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-at91/pm.c')
-rw-r--r--arch/arm/mach-at91/pm.c62
1 files changed, 4 insertions, 58 deletions
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 4028724d490d..615668986480 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -29,62 +29,7 @@
29#include <mach/cpu.h> 29#include <mach/cpu.h>
30 30
31#include "generic.h" 31#include "generic.h"
32 32#include "pm.h"
33#ifdef CONFIG_ARCH_AT91RM9200
34#include <mach/at91rm9200_mc.h>
35
36/*
37 * The AT91RM9200 goes into self-refresh mode with this command, and will
38 * terminate self-refresh automatically on the next SDRAM access.
39 */
40#define sdram_selfrefresh_enable() at91_sys_write(AT91_SDRAMC_SRR, 1)
41#define sdram_selfrefresh_disable() do {} while (0)
42
43#elif defined(CONFIG_ARCH_AT91CAP9)
44#include <mach/at91cap9_ddrsdr.h>
45
46static u32 saved_lpr;
47
48static inline void sdram_selfrefresh_enable(void)
49{
50 u32 lpr;
51
52 saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
53
54 lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
55 at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
56}
57
58#define sdram_selfrefresh_disable() at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
59
60#else
61#include <mach/at91sam9_sdramc.h>
62
63#ifdef CONFIG_ARCH_AT91SAM9263
64/*
65 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
66 * handle those cases both here and in the Suspend-To-RAM support.
67 */
68#define AT91_SDRAMC AT91_SDRAMC0
69#warning Assuming EB1 SDRAM controller is *NOT* used
70#endif
71
72static u32 saved_lpr;
73
74static inline void sdram_selfrefresh_enable(void)
75{
76 u32 lpr;
77
78 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
79
80 lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
81 at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
82}
83
84#define sdram_selfrefresh_disable() at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
85
86#endif
87
88 33
89/* 34/*
90 * Show the reason for the previous system reset. 35 * Show the reason for the previous system reset.
@@ -260,6 +205,7 @@ extern u32 at91_slow_clock_sz;
260 205
261static int at91_pm_enter(suspend_state_t state) 206static int at91_pm_enter(suspend_state_t state)
262{ 207{
208 u32 saved_lpr;
263 at91_gpio_suspend(); 209 at91_gpio_suspend();
264 at91_irq_suspend(); 210 at91_irq_suspend();
265 211
@@ -315,9 +261,9 @@ static int at91_pm_enter(suspend_state_t state)
315 */ 261 */
316 asm("b 1f; .align 5; 1:"); 262 asm("b 1f; .align 5; 1:");
317 asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */ 263 asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */
318 sdram_selfrefresh_enable(); 264 saved_lpr = sdram_selfrefresh_enable();
319 asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */ 265 asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */
320 sdram_selfrefresh_disable(); 266 sdram_selfrefresh_disable(saved_lpr);
321 break; 267 break;
322 268
323 case PM_SUSPEND_ON: 269 case PM_SUSPEND_ON: