ARM: at91: make aic soc independent

on all at91 have the Advanced Interrupt Controller starts at address
0xfffff000

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>

1 files changed, 22 insertions, 16 deletions

diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index 9665265ec757..be6b639ecd7b 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -33,17 +33,18 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 
+void __iomem *at91_aic_base;
 
 static void at91_aic_mask_irq(struct irq_data *d)
 {
         /* Disable interrupt on AIC */
-        at91_sys_write(AT91_AIC_IDCR, 1 << d->irq);
+        at91_aic_write(AT91_AIC_IDCR, 1 << d->irq);
 }
 
 static void at91_aic_unmask_irq(struct irq_data *d)
 {
         /* Enable interrupt on AIC */
-        at91_sys_write(AT91_AIC_IECR, 1 << d->irq);
+        at91_aic_write(AT91_AIC_IECR, 1 << d->irq);
 }
 
 unsigned int at91_extern_irq;
@@ -77,8 +78,8 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
                 return -EINVAL;
         }
 
-        smr = at91_sys_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE;
-        at91_sys_write(AT91_AIC_SMR(d->irq), smr | srctype);
+        smr = at91_aic_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE;
+        at91_aic_write(AT91_AIC_SMR(d->irq), smr | srctype);
         return 0;
 }
 
@@ -102,15 +103,15 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value)
 
 void at91_irq_suspend(void)
 {
-        backups = at91_sys_read(AT91_AIC_IMR);
-        at91_sys_write(AT91_AIC_IDCR, backups);
-        at91_sys_write(AT91_AIC_IECR, wakeups);
+        backups = at91_aic_read(AT91_AIC_IMR);
+        at91_aic_write(AT91_AIC_IDCR, backups);
+        at91_aic_write(AT91_AIC_IECR, wakeups);
 }
 
 void at91_irq_resume(void)
 {
-        at91_sys_write(AT91_AIC_IDCR, wakeups);
-        at91_sys_write(AT91_AIC_IECR, backups);
+        at91_aic_write(AT91_AIC_IDCR, wakeups);
+        at91_aic_write(AT91_AIC_IECR, backups);
 }
 
 #else
@@ -133,34 +134,39 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
 {
         unsigned int i;
 
+        at91_aic_base = ioremap(AT91_AIC, 512);
+
+        if (!at91_aic_base)
+                panic("Impossible to ioremap AT91_AIC\n");
+
         /*
          * The IVR is used by macro get_irqnr_and_base to read and verify.
          * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
          */
         for (i = 0; i < NR_AIC_IRQS; i++) {
                 /* Put irq number in Source Vector Register: */
-                at91_sys_write(AT91_AIC_SVR(i), i);
+                at91_aic_write(AT91_AIC_SVR(i), i);
                 /* Active Low interrupt, with the specified priority */
-                at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
+                at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
 
                 irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 
                 /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
                 if (i < 8)
-                        at91_sys_write(AT91_AIC_EOICR, 0);
+                        at91_aic_write(AT91_AIC_EOICR, 0);
         }
 
         /*
          * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
          * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
          */
-        at91_sys_write(AT91_AIC_SPU, NR_AIC_IRQS);
+        at91_aic_write(AT91_AIC_SPU, NR_AIC_IRQS);
 
         /* No debugging in AIC: Debug (Protect) Control Register */
-        at91_sys_write(AT91_AIC_DCR, 0);
+        at91_aic_write(AT91_AIC_DCR, 0);
 
         /* Disable and clear all interrupts initially */
-        at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF);
-        at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF);
+        at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
+        at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
 }