diff options
| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-08-05 11:14:15 -0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-08-07 04:55:48 -0400 |
| commit | a09e64fbc0094e3073dbb09c3b4bfe4ab669244b (patch) | |
| tree | 69689f467179891b498bd7423fcf61925173db31 /arch/arm/mach-at91/include | |
| parent | a1b81a84fff05dbfef45b7012c26e1fee9973e5d (diff) | |
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
This just leaves include/asm-arm/plat-* to deal with.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-at91/include')
48 files changed, 4059 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_adc.h b/arch/arm/mach-at91/include/mach/at91_adc.h new file mode 100644 index 000000000000..8e7ed5c90817 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_adc.h | |||
| @@ -0,0 +1,61 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_adc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) SAN People | ||
| 5 | * | ||
| 6 | * Analog-to-Digital Converter (ADC) registers. | ||
| 7 | * Based on AT91SAM9260 datasheet revision D. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91_ADC_H | ||
| 16 | #define AT91_ADC_H | ||
| 17 | |||
| 18 | #define AT91_ADC_CR 0x00 /* Control Register */ | ||
| 19 | #define AT91_ADC_SWRST (1 << 0) /* Software Reset */ | ||
| 20 | #define AT91_ADC_START (1 << 1) /* Start Conversion */ | ||
| 21 | |||
| 22 | #define AT91_ADC_MR 0x04 /* Mode Register */ | ||
| 23 | #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */ | ||
| 24 | #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */ | ||
| 25 | #define AT91_ADC_TRGSEL_TC0 (0 << 1) | ||
| 26 | #define AT91_ADC_TRGSEL_TC1 (1 << 1) | ||
| 27 | #define AT91_ADC_TRGSEL_TC2 (2 << 1) | ||
| 28 | #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1) | ||
| 29 | #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */ | ||
| 30 | #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */ | ||
| 31 | #define AT91_ADC_PRESCAL (0x3f << 8) /* Prescalar Rate Selection */ | ||
| 32 | #define AT91_ADC_PRESCAL_(x) ((x) << 8) | ||
| 33 | #define AT91_ADC_STARTUP (0x1f << 16) /* Startup Up Time */ | ||
| 34 | #define AT91_ADC_STARTUP_(x) ((x) << 16) | ||
| 35 | #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */ | ||
| 36 | #define AT91_ADC_SHTIM_(x) ((x) << 24) | ||
| 37 | |||
| 38 | #define AT91_ADC_CHER 0x10 /* Channel Enable Register */ | ||
| 39 | #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */ | ||
| 40 | #define AT91_ADC_CHSR 0x18 /* Channel Status Register */ | ||
| 41 | #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */ | ||
| 42 | |||
| 43 | #define AT91_ADC_SR 0x1C /* Status Register */ | ||
| 44 | #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */ | ||
| 45 | #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */ | ||
| 46 | #define AT91_ADC_DRDY (1 << 16) /* Data Ready */ | ||
| 47 | #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */ | ||
| 48 | #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ | ||
| 49 | #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ | ||
| 50 | |||
| 51 | #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ | ||
| 52 | #define AT91_ADC_LDATA (0x3ff) | ||
| 53 | |||
| 54 | #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */ | ||
| 55 | #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */ | ||
| 56 | #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */ | ||
| 57 | |||
| 58 | #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ | ||
| 59 | #define AT91_ADC_DATA (0x3ff) | ||
| 60 | |||
| 61 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h new file mode 100644 index 000000000000..03566799d3be --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_aic.h | |||
| @@ -0,0 +1,53 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_aic.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Advanced Interrupt Controller (AIC) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_AIC_H | ||
| 17 | #define AT91_AIC_H | ||
| 18 | |||
| 19 | #define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */ | ||
| 20 | #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ | ||
| 21 | #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ | ||
| 22 | #define AT91_AIC_SRCTYPE_LOW (0 << 5) | ||
| 23 | #define AT91_AIC_SRCTYPE_FALLING (1 << 5) | ||
| 24 | #define AT91_AIC_SRCTYPE_HIGH (2 << 5) | ||
| 25 | #define AT91_AIC_SRCTYPE_RISING (3 << 5) | ||
| 26 | |||
| 27 | #define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ | ||
| 28 | #define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */ | ||
| 29 | #define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */ | ||
| 30 | #define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */ | ||
| 31 | #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ | ||
| 32 | |||
| 33 | #define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */ | ||
| 34 | #define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */ | ||
| 35 | #define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */ | ||
| 36 | #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ | ||
| 37 | #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ | ||
| 38 | |||
| 39 | #define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */ | ||
| 40 | #define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */ | ||
| 41 | #define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */ | ||
| 42 | #define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */ | ||
| 43 | #define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */ | ||
| 44 | #define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */ | ||
| 45 | #define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */ | ||
| 46 | #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ | ||
| 47 | #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ | ||
| 48 | |||
| 49 | #define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */ | ||
| 50 | #define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */ | ||
| 51 | #define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */ | ||
| 52 | |||
| 53 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h new file mode 100644 index 000000000000..6dcaa7716871 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h | |||
| @@ -0,0 +1,66 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_dbgu.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Debug Unit (DBGU) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_DBGU_H | ||
| 17 | #define AT91_DBGU_H | ||
| 18 | |||
| 19 | #ifdef AT91_DBGU | ||
| 20 | #define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ | ||
| 21 | #define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ | ||
| 22 | #define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ | ||
| 23 | #define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ | ||
| 24 | #define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ | ||
| 25 | #define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */ | ||
| 26 | #define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */ | ||
| 27 | #define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ | ||
| 28 | #define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */ | ||
| 29 | #define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */ | ||
| 30 | #define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */ | ||
| 31 | |||
| 32 | #define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ | ||
| 33 | #define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ | ||
| 34 | #define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ | ||
| 35 | #define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ | ||
| 36 | |||
| 37 | #endif /* AT91_DBGU */ | ||
| 38 | |||
| 39 | /* | ||
| 40 | * Some AT91 parts that don't have full DEBUG units still support the ID | ||
| 41 | * and extensions register. | ||
| 42 | */ | ||
| 43 | #define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ | ||
| 44 | #define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ | ||
| 45 | #define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ | ||
| 46 | #define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */ | ||
| 47 | #define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ | ||
| 48 | #define AT91_CIDR_SRAMSIZ_1K (1 << 16) | ||
| 49 | #define AT91_CIDR_SRAMSIZ_2K (2 << 16) | ||
| 50 | #define AT91_CIDR_SRAMSIZ_112K (4 << 16) | ||
| 51 | #define AT91_CIDR_SRAMSIZ_4K (5 << 16) | ||
| 52 | #define AT91_CIDR_SRAMSIZ_80K (6 << 16) | ||
| 53 | #define AT91_CIDR_SRAMSIZ_160K (7 << 16) | ||
| 54 | #define AT91_CIDR_SRAMSIZ_8K (8 << 16) | ||
| 55 | #define AT91_CIDR_SRAMSIZ_16K (9 << 16) | ||
| 56 | #define AT91_CIDR_SRAMSIZ_32K (10 << 16) | ||
| 57 | #define AT91_CIDR_SRAMSIZ_64K (11 << 16) | ||
| 58 | #define AT91_CIDR_SRAMSIZ_128K (12 << 16) | ||
| 59 | #define AT91_CIDR_SRAMSIZ_256K (13 << 16) | ||
| 60 | #define AT91_CIDR_SRAMSIZ_96K (14 << 16) | ||
| 61 | #define AT91_CIDR_SRAMSIZ_512K (15 << 16) | ||
| 62 | #define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */ | ||
| 63 | #define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ | ||
| 64 | #define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ | ||
| 65 | |||
| 66 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_mci.h b/arch/arm/mach-at91/include/mach/at91_mci.h new file mode 100644 index 000000000000..550d503a1bca --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_mci.h | |||
| @@ -0,0 +1,113 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_mci.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * MultiMedia Card Interface (MCI) registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision F. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_MCI_H | ||
| 17 | #define AT91_MCI_H | ||
| 18 | |||
| 19 | #define AT91_MCI_CR 0x00 /* Control Register */ | ||
| 20 | #define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ | ||
| 21 | #define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ | ||
| 22 | #define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ | ||
| 23 | #define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ | ||
| 24 | #define AT91_MCI_SWRST (1 << 7) /* Software Reset */ | ||
| 25 | |||
| 26 | #define AT91_MCI_MR 0x04 /* Mode Register */ | ||
| 27 | #define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */ | ||
| 28 | #define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ | ||
| 29 | #define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ | ||
| 30 | #define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ | ||
| 31 | #define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ | ||
| 32 | #define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ | ||
| 33 | #define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ | ||
| 34 | #define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ | ||
| 35 | |||
| 36 | #define AT91_MCI_DTOR 0x08 /* Data Timeout Register */ | ||
| 37 | #define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ | ||
| 38 | #define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ | ||
| 39 | #define AT91_MCI_DTOMUL_1 (0 << 4) | ||
| 40 | #define AT91_MCI_DTOMUL_16 (1 << 4) | ||
| 41 | #define AT91_MCI_DTOMUL_128 (2 << 4) | ||
| 42 | #define AT91_MCI_DTOMUL_256 (3 << 4) | ||
| 43 | #define AT91_MCI_DTOMUL_1K (4 << 4) | ||
| 44 | #define AT91_MCI_DTOMUL_4K (5 << 4) | ||
| 45 | #define AT91_MCI_DTOMUL_64K (6 << 4) | ||
| 46 | #define AT91_MCI_DTOMUL_1M (7 << 4) | ||
| 47 | |||
| 48 | #define AT91_MCI_SDCR 0x0c /* SD Card Register */ | ||
| 49 | #define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */ | ||
| 50 | #define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ | ||
| 51 | |||
| 52 | #define AT91_MCI_ARGR 0x10 /* Argument Register */ | ||
| 53 | |||
| 54 | #define AT91_MCI_CMDR 0x14 /* Command Register */ | ||
| 55 | #define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */ | ||
| 56 | #define AT91_MCI_RSPTYP (3 << 6) /* Response Type */ | ||
| 57 | #define AT91_MCI_RSPTYP_NONE (0 << 6) | ||
| 58 | #define AT91_MCI_RSPTYP_48 (1 << 6) | ||
| 59 | #define AT91_MCI_RSPTYP_136 (2 << 6) | ||
| 60 | #define AT91_MCI_SPCMD (7 << 8) /* Special Command */ | ||
| 61 | #define AT91_MCI_SPCMD_NONE (0 << 8) | ||
| 62 | #define AT91_MCI_SPCMD_INIT (1 << 8) | ||
| 63 | #define AT91_MCI_SPCMD_SYNC (2 << 8) | ||
| 64 | #define AT91_MCI_SPCMD_ICMD (4 << 8) | ||
| 65 | #define AT91_MCI_SPCMD_IRESP (5 << 8) | ||
| 66 | #define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */ | ||
| 67 | #define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ | ||
| 68 | #define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */ | ||
| 69 | #define AT91_MCI_TRCMD_NONE (0 << 16) | ||
| 70 | #define AT91_MCI_TRCMD_START (1 << 16) | ||
| 71 | #define AT91_MCI_TRCMD_STOP (2 << 16) | ||
| 72 | #define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */ | ||
| 73 | #define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */ | ||
| 74 | #define AT91_MCI_TRTYP_BLOCK (0 << 19) | ||
| 75 | #define AT91_MCI_TRTYP_MULTIPLE (1 << 19) | ||
| 76 | #define AT91_MCI_TRTYP_STREAM (2 << 19) | ||
| 77 | |||
| 78 | #define AT91_MCI_BLKR 0x18 /* Block Register */ | ||
| 79 | #define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ | ||
| 80 | #define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ | ||
| 81 | |||
| 82 | #define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ | ||
| 83 | #define AT91_MCR_RDR 0x30 /* Receive Data Register */ | ||
| 84 | #define AT91_MCR_TDR 0x34 /* Transmit Data Register */ | ||
| 85 | |||
| 86 | #define AT91_MCI_SR 0x40 /* Status Register */ | ||
| 87 | #define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */ | ||
| 88 | #define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */ | ||
| 89 | #define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */ | ||
| 90 | #define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */ | ||
| 91 | #define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */ | ||
| 92 | #define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */ | ||
| 93 | #define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */ | ||
| 94 | #define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */ | ||
| 95 | #define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */ | ||
| 96 | #define AT91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B */ | ||
| 97 | #define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */ | ||
| 98 | #define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */ | ||
| 99 | #define AT91_MCI_RINDE (1 << 16) /* Response Index Error */ | ||
| 100 | #define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */ | ||
| 101 | #define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */ | ||
| 102 | #define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */ | ||
| 103 | #define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */ | ||
| 104 | #define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */ | ||
| 105 | #define AT91_MCI_DTOE (1 << 22) /* Data Time-out Error */ | ||
| 106 | #define AT91_MCI_OVRE (1 << 30) /* Overrun */ | ||
| 107 | #define AT91_MCI_UNRE (1 << 31) /* Underrun */ | ||
| 108 | |||
| 109 | #define AT91_MCI_IER 0x44 /* Interrupt Enable Register */ | ||
| 110 | #define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */ | ||
| 111 | #define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */ | ||
| 112 | |||
| 113 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h new file mode 100644 index 000000000000..c6a31bf8a5c6 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_pio.h | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_pio.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Parallel I/O Controller (PIO) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_PIO_H | ||
| 17 | #define AT91_PIO_H | ||
| 18 | |||
| 19 | #define PIO_PER 0x00 /* Enable Register */ | ||
| 20 | #define PIO_PDR 0x04 /* Disable Register */ | ||
| 21 | #define PIO_PSR 0x08 /* Status Register */ | ||
| 22 | #define PIO_OER 0x10 /* Output Enable Register */ | ||
| 23 | #define PIO_ODR 0x14 /* Output Disable Register */ | ||
| 24 | #define PIO_OSR 0x18 /* Output Status Register */ | ||
| 25 | #define PIO_IFER 0x20 /* Glitch Input Filter Enable */ | ||
| 26 | #define PIO_IFDR 0x24 /* Glitch Input Filter Disable */ | ||
| 27 | #define PIO_IFSR 0x28 /* Glitch Input Filter Status */ | ||
| 28 | #define PIO_SODR 0x30 /* Set Output Data Register */ | ||
| 29 | #define PIO_CODR 0x34 /* Clear Output Data Register */ | ||
| 30 | #define PIO_ODSR 0x38 /* Output Data Status Register */ | ||
| 31 | #define PIO_PDSR 0x3c /* Pin Data Status Register */ | ||
| 32 | #define PIO_IER 0x40 /* Interrupt Enable Register */ | ||
| 33 | #define PIO_IDR 0x44 /* Interrupt Disable Register */ | ||
| 34 | #define PIO_IMR 0x48 /* Interrupt Mask Register */ | ||
| 35 | #define PIO_ISR 0x4c /* Interrupt Status Register */ | ||
| 36 | #define PIO_MDER 0x50 /* Multi-driver Enable Register */ | ||
| 37 | #define PIO_MDDR 0x54 /* Multi-driver Disable Register */ | ||
| 38 | #define PIO_MDSR 0x58 /* Multi-driver Status Register */ | ||
| 39 | #define PIO_PUDR 0x60 /* Pull-up Disable Register */ | ||
| 40 | #define PIO_PUER 0x64 /* Pull-up Enable Register */ | ||
| 41 | #define PIO_PUSR 0x68 /* Pull-up Status Register */ | ||
| 42 | #define PIO_ASR 0x70 /* Peripheral A Select Register */ | ||
| 43 | #define PIO_BSR 0x74 /* Peripheral B Select Register */ | ||
| 44 | #define PIO_ABSR 0x78 /* AB Status Register */ | ||
| 45 | #define PIO_OWER 0xa0 /* Output Write Enable Register */ | ||
| 46 | #define PIO_OWDR 0xa4 /* Output Write Disable Register */ | ||
| 47 | #define PIO_OWSR 0xa8 /* Output Write Status Register */ | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h new file mode 100644 index 000000000000..0448ac36eadb --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_pit.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_pit.h | ||
| 3 | * | ||
| 4 | * Periodic Interval Timer (PIT) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_PIT_H | ||
| 14 | #define AT91_PIT_H | ||
| 15 | |||
| 16 | #define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */ | ||
| 17 | #define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */ | ||
| 18 | #define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */ | ||
| 19 | #define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */ | ||
| 20 | |||
| 21 | #define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */ | ||
| 22 | #define AT91_PIT_PITS (1 << 0) /* Timer Status */ | ||
| 23 | |||
| 24 | #define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */ | ||
| 25 | #define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */ | ||
| 26 | #define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */ | ||
| 27 | #define AT91_PIT_CPIV (0xfffff) /* Inverval Value */ | ||
| 28 | |||
| 29 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h new file mode 100644 index 000000000000..2e3f2894b704 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h | |||
| @@ -0,0 +1,111 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_pmc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Power Management Controller (PMC) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_PMC_H | ||
| 17 | #define AT91_PMC_H | ||
| 18 | |||
| 19 | #define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */ | ||
| 20 | #define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */ | ||
| 21 | |||
| 22 | #define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */ | ||
| 23 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ | ||
| 24 | #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ | ||
| 25 | #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ | ||
| 26 | #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ | ||
| 27 | #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ | ||
| 28 | #define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ | ||
| 29 | #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ | ||
| 30 | #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ | ||
| 31 | #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ | ||
| 32 | #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ | ||
| 33 | #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ | ||
| 34 | #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ | ||
| 35 | #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ | ||
| 36 | |||
| 37 | #define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */ | ||
| 38 | #define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ | ||
| 39 | #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ | ||
| 40 | |||
| 41 | #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ | ||
| 42 | #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ | ||
| 43 | #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ | ||
| 44 | #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ | ||
| 45 | #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ | ||
| 46 | |||
| 47 | #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ | ||
| 48 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ | ||
| 49 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ | ||
| 50 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ | ||
| 51 | |||
| 52 | #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ | ||
| 53 | #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ | ||
| 54 | #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ | ||
| 55 | |||
| 56 | #define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */ | ||
| 57 | #define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */ | ||
| 58 | #define AT91_PMC_DIV (0xff << 0) /* Divider */ | ||
| 59 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ | ||
| 60 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ | ||
| 61 | #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ | ||
| 62 | #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ | ||
| 63 | #define AT91_PMC_USBDIV_1 (0 << 28) | ||
| 64 | #define AT91_PMC_USBDIV_2 (1 << 28) | ||
| 65 | #define AT91_PMC_USBDIV_4 (2 << 28) | ||
| 66 | #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ | ||
| 67 | |||
| 68 | #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ | ||
| 69 | #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ | ||
| 70 | #define AT91_PMC_CSS_SLOW (0 << 0) | ||
| 71 | #define AT91_PMC_CSS_MAIN (1 << 0) | ||
| 72 | #define AT91_PMC_CSS_PLLA (2 << 0) | ||
| 73 | #define AT91_PMC_CSS_PLLB (3 << 0) | ||
| 74 | #define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */ | ||
| 75 | #define AT91_PMC_PRES_1 (0 << 2) | ||
| 76 | #define AT91_PMC_PRES_2 (1 << 2) | ||
| 77 | #define AT91_PMC_PRES_4 (2 << 2) | ||
| 78 | #define AT91_PMC_PRES_8 (3 << 2) | ||
| 79 | #define AT91_PMC_PRES_16 (4 << 2) | ||
| 80 | #define AT91_PMC_PRES_32 (5 << 2) | ||
| 81 | #define AT91_PMC_PRES_64 (6 << 2) | ||
| 82 | #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ | ||
| 83 | #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ | ||
| 84 | #define AT91RM9200_PMC_MDIV_2 (1 << 8) | ||
| 85 | #define AT91RM9200_PMC_MDIV_3 (2 << 8) | ||
| 86 | #define AT91RM9200_PMC_MDIV_4 (3 << 8) | ||
| 87 | #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ | ||
| 88 | #define AT91SAM9_PMC_MDIV_2 (1 << 8) | ||
| 89 | #define AT91SAM9_PMC_MDIV_4 (2 << 8) | ||
| 90 | #define AT91SAM9_PMC_MDIV_6 (3 << 8) | ||
| 91 | #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ | ||
| 92 | #define AT91_PMC_PDIV_1 (0 << 12) | ||
| 93 | #define AT91_PMC_PDIV_2 (1 << 12) | ||
| 94 | |||
| 95 | #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ | ||
| 96 | |||
| 97 | #define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ | ||
| 98 | #define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ | ||
| 99 | #define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ | ||
| 100 | #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ | ||
| 101 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ | ||
| 102 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ | ||
| 103 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ | ||
| 104 | #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ | ||
| 105 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ | ||
| 106 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ | ||
| 107 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ | ||
| 108 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ | ||
| 109 | #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ | ||
| 110 | |||
| 111 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h new file mode 100644 index 000000000000..7cd1b39aaa43 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_rstc.h | |||
| @@ -0,0 +1,38 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_rstc.h | ||
| 3 | * | ||
| 4 | * Reset Controller (RSTC) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_RSTC_H | ||
| 14 | #define AT91_RSTC_H | ||
| 15 | |||
| 16 | #define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ | ||
| 17 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ | ||
| 18 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ | ||
| 19 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ | ||
| 20 | #define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ | ||
| 21 | |||
| 22 | #define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ | ||
| 23 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ | ||
| 24 | #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ | ||
| 25 | #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) | ||
| 26 | #define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) | ||
| 27 | #define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) | ||
| 28 | #define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) | ||
| 29 | #define AT91_RSTC_RSTTYP_USER (4 << 8) | ||
| 30 | #define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ | ||
| 31 | #define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ | ||
| 32 | |||
| 33 | #define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ | ||
| 34 | #define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ | ||
| 35 | #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ | ||
| 36 | #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ | ||
| 37 | |||
| 38 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_rtc.h b/arch/arm/mach-at91/include/mach/at91_rtc.h new file mode 100644 index 000000000000..e56f4701a3e5 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_rtc.h | |||
| @@ -0,0 +1,75 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_rtc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Real Time Clock (RTC) - System peripheral registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_RTC_H | ||
| 17 | #define AT91_RTC_H | ||
| 18 | |||
| 19 | #define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */ | ||
| 20 | #define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */ | ||
| 21 | #define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */ | ||
| 22 | #define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */ | ||
| 23 | #define AT91_RTC_TIMEVSEL_MINUTE (0 << 8) | ||
| 24 | #define AT91_RTC_TIMEVSEL_HOUR (1 << 8) | ||
| 25 | #define AT91_RTC_TIMEVSEL_DAY24 (2 << 8) | ||
| 26 | #define AT91_RTC_TIMEVSEL_DAY12 (3 << 8) | ||
| 27 | #define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */ | ||
| 28 | #define AT91_RTC_CALEVSEL_WEEK (0 << 16) | ||
| 29 | #define AT91_RTC_CALEVSEL_MONTH (1 << 16) | ||
| 30 | #define AT91_RTC_CALEVSEL_YEAR (2 << 16) | ||
| 31 | |||
| 32 | #define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */ | ||
| 33 | #define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */ | ||
| 34 | |||
| 35 | #define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */ | ||
| 36 | #define AT91_RTC_SEC (0x7f << 0) /* Current Second */ | ||
| 37 | #define AT91_RTC_MIN (0x7f << 8) /* Current Minute */ | ||
| 38 | #define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */ | ||
| 39 | #define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */ | ||
| 40 | |||
| 41 | #define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */ | ||
| 42 | #define AT91_RTC_CENT (0x7f << 0) /* Current Century */ | ||
| 43 | #define AT91_RTC_YEAR (0xff << 8) /* Current Year */ | ||
| 44 | #define AT91_RTC_MONTH (0x1f << 16) /* Current Month */ | ||
| 45 | #define AT91_RTC_DAY (7 << 21) /* Current Day */ | ||
| 46 | #define AT91_RTC_DATE (0x3f << 24) /* Current Date */ | ||
| 47 | |||
| 48 | #define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */ | ||
| 49 | #define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */ | ||
| 50 | #define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */ | ||
| 51 | #define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */ | ||
| 52 | |||
| 53 | #define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */ | ||
| 54 | #define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */ | ||
| 55 | #define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */ | ||
| 56 | |||
| 57 | #define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */ | ||
| 58 | #define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */ | ||
| 59 | #define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */ | ||
| 60 | #define AT91_RTC_SECEV (1 << 2) /* Second Event */ | ||
| 61 | #define AT91_RTC_TIMEV (1 << 3) /* Time Event */ | ||
| 62 | #define AT91_RTC_CALEV (1 << 4) /* Calendar Event */ | ||
| 63 | |||
| 64 | #define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */ | ||
| 65 | #define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */ | ||
| 66 | #define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */ | ||
| 67 | #define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */ | ||
| 68 | |||
| 69 | #define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */ | ||
| 70 | #define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */ | ||
| 71 | #define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */ | ||
| 72 | #define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */ | ||
| 73 | #define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */ | ||
| 74 | |||
| 75 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_rtt.h b/arch/arm/mach-at91/include/mach/at91_rtt.h new file mode 100644 index 000000000000..71782e5d2159 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_rtt.h | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_rtt.h | ||
| 3 | * | ||
| 4 | * Real-time Timer (RTT) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_RTT_H | ||
| 14 | #define AT91_RTT_H | ||
| 15 | |||
| 16 | #define AT91_RTT_MR 0x00 /* Real-time Mode Register */ | ||
| 17 | #define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */ | ||
| 18 | #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ | ||
| 19 | #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ | ||
| 20 | #define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */ | ||
| 21 | |||
| 22 | #define AT91_RTT_AR 0x04 /* Real-time Alarm Register */ | ||
| 23 | #define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */ | ||
| 24 | |||
| 25 | #define AT91_RTT_VR 0x08 /* Real-time Value Register */ | ||
| 26 | #define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */ | ||
| 27 | |||
| 28 | #define AT91_RTT_SR 0x0c /* Real-time Status Register */ | ||
| 29 | #define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */ | ||
| 30 | #define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */ | ||
| 31 | |||
| 32 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_shdwc.h b/arch/arm/mach-at91/include/mach/at91_shdwc.h new file mode 100644 index 000000000000..60be5ae624f1 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_shdwc.h | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_shdwc.h | ||
| 3 | * | ||
| 4 | * Shutdown Controller (SHDWC) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_SHDWC_H | ||
| 14 | #define AT91_SHDWC_H | ||
| 15 | |||
| 16 | #define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */ | ||
| 17 | #define AT91_SHDW_SHDW (1 << 0) /* Shut Down command */ | ||
| 18 | #define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */ | ||
| 19 | |||
| 20 | #define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */ | ||
| 21 | #define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */ | ||
| 22 | #define AT91_SHDW_WKMODE0_NONE 0 | ||
| 23 | #define AT91_SHDW_WKMODE0_HIGH 1 | ||
| 24 | #define AT91_SHDW_WKMODE0_LOW 2 | ||
| 25 | #define AT91_SHDW_WKMODE0_ANYLEVEL 3 | ||
| 26 | #define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */ | ||
| 27 | #define AT91_SHDW_CPTWK0_(x) ((x) << 4) | ||
| 28 | #define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */ | ||
| 29 | |||
| 30 | #define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */ | ||
| 31 | #define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */ | ||
| 32 | #define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */ | ||
| 33 | #define AT91_SHDW_RTCWK (1 << 17) /* Real-time Clock Wake-up [SAM9RL] */ | ||
| 34 | |||
| 35 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_spi.h b/arch/arm/mach-at91/include/mach/at91_spi.h new file mode 100644 index 000000000000..2f6ba0c5636e --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_spi.h | |||
| @@ -0,0 +1,81 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_spi.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Serial Peripheral Interface (SPI) registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_SPI_H | ||
| 17 | #define AT91_SPI_H | ||
| 18 | |||
| 19 | #define AT91_SPI_CR 0x00 /* Control Register */ | ||
| 20 | #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ | ||
| 21 | #define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ | ||
| 22 | #define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */ | ||
| 23 | #define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ | ||
| 24 | |||
| 25 | #define AT91_SPI_MR 0x04 /* Mode Register */ | ||
| 26 | #define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */ | ||
| 27 | #define AT91_SPI_PS (1 << 1) /* Peripheral Select */ | ||
| 28 | #define AT91_SPI_PS_FIXED (0 << 1) | ||
| 29 | #define AT91_SPI_PS_VARIABLE (1 << 1) | ||
| 30 | #define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ | ||
| 31 | #define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */ | ||
| 32 | #define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ | ||
| 33 | #define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ | ||
| 34 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | ||
| 35 | #define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */ | ||
| 36 | |||
| 37 | #define AT91_SPI_RDR 0x08 /* Receive Data Register */ | ||
| 38 | #define AT91_SPI_RD (0xffff << 0) /* Receive Data */ | ||
| 39 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | ||
| 40 | |||
| 41 | #define AT91_SPI_TDR 0x0c /* Transmit Data Register */ | ||
| 42 | #define AT91_SPI_TD (0xffff << 0) /* Transmit Data */ | ||
| 43 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | ||
| 44 | #define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ | ||
| 45 | |||
| 46 | #define AT91_SPI_SR 0x10 /* Status Register */ | ||
| 47 | #define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */ | ||
| 48 | #define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */ | ||
| 49 | #define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */ | ||
| 50 | #define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */ | ||
| 51 | #define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */ | ||
| 52 | #define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */ | ||
| 53 | #define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */ | ||
| 54 | #define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */ | ||
| 55 | #define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */ | ||
| 56 | #define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */ | ||
| 57 | #define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */ | ||
| 58 | |||
| 59 | #define AT91_SPI_IER 0x14 /* Interrupt Enable Register */ | ||
| 60 | #define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */ | ||
| 61 | #define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */ | ||
| 62 | |||
| 63 | #define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */ | ||
| 64 | #define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */ | ||
| 65 | #define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */ | ||
| 66 | #define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */ | ||
| 67 | #define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */ | ||
| 68 | #define AT91_SPI_BITS_8 (0 << 4) | ||
| 69 | #define AT91_SPI_BITS_9 (1 << 4) | ||
| 70 | #define AT91_SPI_BITS_10 (2 << 4) | ||
| 71 | #define AT91_SPI_BITS_11 (3 << 4) | ||
| 72 | #define AT91_SPI_BITS_12 (4 << 4) | ||
| 73 | #define AT91_SPI_BITS_13 (5 << 4) | ||
| 74 | #define AT91_SPI_BITS_14 (6 << 4) | ||
| 75 | #define AT91_SPI_BITS_15 (7 << 4) | ||
| 76 | #define AT91_SPI_BITS_16 (8 << 4) | ||
| 77 | #define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */ | ||
| 78 | #define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */ | ||
| 79 | #define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */ | ||
| 80 | |||
| 81 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_ssc.h b/arch/arm/mach-at91/include/mach/at91_ssc.h new file mode 100644 index 000000000000..a81114c11c74 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_ssc.h | |||
| @@ -0,0 +1,106 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_ssc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) SAN People | ||
| 5 | * | ||
| 6 | * Serial Synchronous Controller (SSC) registers. | ||
| 7 | * Based on AT91RM9200 datasheet revision E. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91_SSC_H | ||
| 16 | #define AT91_SSC_H | ||
| 17 | |||
| 18 | #define AT91_SSC_CR 0x00 /* Control Register */ | ||
| 19 | #define AT91_SSC_RXEN (1 << 0) /* Receive Enable */ | ||
| 20 | #define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */ | ||
| 21 | #define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */ | ||
| 22 | #define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */ | ||
| 23 | #define AT91_SSC_SWRST (1 << 15) /* Software Reset */ | ||
| 24 | |||
| 25 | #define AT91_SSC_CMR 0x04 /* Clock Mode Register */ | ||
| 26 | #define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */ | ||
| 27 | |||
| 28 | #define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */ | ||
| 29 | #define AT91_SSC_CKS (3 << 0) /* Clock Selection */ | ||
| 30 | #define AT91_SSC_CKS_DIV (0 << 0) | ||
| 31 | #define AT91_SSC_CKS_CLOCK (1 << 0) | ||
| 32 | #define AT91_SSC_CKS_PIN (2 << 0) | ||
| 33 | #define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */ | ||
| 34 | #define AT91_SSC_CKO_NONE (0 << 2) | ||
| 35 | #define AT91_SSC_CKO_CONTINUOUS (1 << 2) | ||
| 36 | #define AT91_SSC_CKI (1 << 5) /* Clock Inversion */ | ||
| 37 | #define AT91_SSC_CKI_FALLING (0 << 5) | ||
| 38 | #define AT91_SSC_CK_RISING (1 << 5) | ||
| 39 | #define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */ | ||
| 40 | #define AT91_SSC_CKG_NONE (0 << 6) | ||
| 41 | #define AT91_SSC_CKG_RFLOW (1 << 6) | ||
| 42 | #define AT91_SSC_CKG_RFHIGH (2 << 6) | ||
| 43 | #define AT91_SSC_START (0xf << 8) /* Start Selection */ | ||
| 44 | #define AT91_SSC_START_CONTINUOUS (0 << 8) | ||
| 45 | #define AT91_SSC_START_TX_RX (1 << 8) | ||
| 46 | #define AT91_SSC_START_LOW_RF (2 << 8) | ||
| 47 | #define AT91_SSC_START_HIGH_RF (3 << 8) | ||
| 48 | #define AT91_SSC_START_FALLING_RF (4 << 8) | ||
| 49 | #define AT91_SSC_START_RISING_RF (5 << 8) | ||
| 50 | #define AT91_SSC_START_LEVEL_RF (6 << 8) | ||
| 51 | #define AT91_SSC_START_EDGE_RF (7 << 8) | ||
| 52 | #define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */ | ||
| 53 | #define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */ | ||
| 54 | #define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */ | ||
| 55 | |||
| 56 | #define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */ | ||
| 57 | #define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */ | ||
| 58 | #define AT91_SSC_LOOP (1 << 5) /* Loop Mode */ | ||
| 59 | #define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */ | ||
| 60 | #define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */ | ||
| 61 | #define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */ | ||
| 62 | #define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */ | ||
| 63 | #define AT91_SSC_FSOS_NONE (0 << 20) | ||
| 64 | #define AT91_SSC_FSOS_NEGATIVE (1 << 20) | ||
| 65 | #define AT91_SSC_FSOS_POSITIVE (2 << 20) | ||
| 66 | #define AT91_SSC_FSOS_LOW (3 << 20) | ||
| 67 | #define AT91_SSC_FSOS_HIGH (4 << 20) | ||
| 68 | #define AT91_SSC_FSOS_TOGGLE (5 << 20) | ||
| 69 | #define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */ | ||
| 70 | #define AT91_SSC_FSEDGE_POSITIVE (0 << 24) | ||
| 71 | #define AT91_SSC_FSEDGE_NEGATIVE (1 << 24) | ||
| 72 | |||
| 73 | #define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */ | ||
| 74 | #define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */ | ||
| 75 | #define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */ | ||
| 76 | #define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */ | ||
| 77 | |||
| 78 | #define AT91_SSC_RHR 0x20 /* Receive Holding Register */ | ||
| 79 | #define AT91_SSC_THR 0x24 /* Transmit Holding Register */ | ||
| 80 | #define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */ | ||
| 81 | #define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */ | ||
| 82 | |||
| 83 | #define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */ | ||
| 84 | #define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */ | ||
| 85 | |||
| 86 | #define AT91_SSC_SR 0x40 /* Status Register */ | ||
| 87 | #define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */ | ||
| 88 | #define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */ | ||
| 89 | #define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */ | ||
| 90 | #define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */ | ||
| 91 | #define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */ | ||
| 92 | #define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */ | ||
| 93 | #define AT91_SSC_ENDRX (1 << 6) /* End of Reception */ | ||
| 94 | #define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */ | ||
| 95 | #define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */ | ||
| 96 | #define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */ | ||
| 97 | #define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */ | ||
| 98 | #define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */ | ||
| 99 | #define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */ | ||
| 100 | #define AT91_SSC_RXENA (1 << 17) /* Receive Enable */ | ||
| 101 | |||
| 102 | #define AT91_SSC_IER 0x44 /* Interrupt Enable Register */ | ||
| 103 | #define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */ | ||
| 104 | #define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */ | ||
| 105 | |||
| 106 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h new file mode 100644 index 000000000000..8847173e4101 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_st.h | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_st.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * System Timer (ST) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_ST_H | ||
| 17 | #define AT91_ST_H | ||
| 18 | |||
| 19 | #define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */ | ||
| 20 | #define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */ | ||
| 21 | |||
| 22 | #define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */ | ||
| 23 | #define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */ | ||
| 24 | |||
| 25 | #define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */ | ||
| 26 | #define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */ | ||
| 27 | #define AT91_ST_RSTEN (1 << 16) /* Reset Enable */ | ||
| 28 | #define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */ | ||
| 29 | |||
| 30 | #define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */ | ||
| 31 | #define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */ | ||
| 32 | |||
| 33 | #define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */ | ||
| 34 | #define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */ | ||
| 35 | #define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */ | ||
| 36 | #define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */ | ||
| 37 | #define AT91_ST_ALMS (1 << 3) /* Alarm Status */ | ||
| 38 | |||
| 39 | #define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */ | ||
| 40 | #define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */ | ||
| 41 | #define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */ | ||
| 42 | |||
| 43 | #define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */ | ||
| 44 | #define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */ | ||
| 45 | |||
| 46 | #define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */ | ||
| 47 | #define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */ | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_tc.h b/arch/arm/mach-at91/include/mach/at91_tc.h new file mode 100644 index 000000000000..46a317fd7164 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_tc.h | |||
| @@ -0,0 +1,146 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_tc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) SAN People | ||
| 5 | * | ||
| 6 | * Timer/Counter Unit (TC) registers. | ||
| 7 | * Based on AT91RM9200 datasheet revision E. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91_TC_H | ||
| 16 | #define AT91_TC_H | ||
| 17 | |||
| 18 | #define AT91_TC_BCR 0xc0 /* TC Block Control Register */ | ||
| 19 | #define AT91_TC_SYNC (1 << 0) /* Synchro Command */ | ||
| 20 | |||
| 21 | #define AT91_TC_BMR 0xc4 /* TC Block Mode Register */ | ||
| 22 | #define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */ | ||
| 23 | #define AT91_TC_TC0XC0S_TCLK0 (0 << 0) | ||
| 24 | #define AT91_TC_TC0XC0S_NONE (1 << 0) | ||
| 25 | #define AT91_TC_TC0XC0S_TIOA1 (2 << 0) | ||
| 26 | #define AT91_TC_TC0XC0S_TIOA2 (3 << 0) | ||
| 27 | #define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */ | ||
| 28 | #define AT91_TC_TC1XC1S_TCLK1 (0 << 2) | ||
| 29 | #define AT91_TC_TC1XC1S_NONE (1 << 2) | ||
| 30 | #define AT91_TC_TC1XC1S_TIOA0 (2 << 2) | ||
| 31 | #define AT91_TC_TC1XC1S_TIOA2 (3 << 2) | ||
| 32 | #define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */ | ||
| 33 | #define AT91_TC_TC2XC2S_TCLK2 (0 << 4) | ||
| 34 | #define AT91_TC_TC2XC2S_NONE (1 << 4) | ||
| 35 | #define AT91_TC_TC2XC2S_TIOA0 (2 << 4) | ||
| 36 | #define AT91_TC_TC2XC2S_TIOA1 (3 << 4) | ||
| 37 | |||
| 38 | |||
| 39 | #define AT91_TC_CCR 0x00 /* Channel Control Register */ | ||
| 40 | #define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */ | ||
| 41 | #define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */ | ||
| 42 | #define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */ | ||
| 43 | |||
| 44 | #define AT91_TC_CMR 0x04 /* Channel Mode Register */ | ||
| 45 | #define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */ | ||
| 46 | #define AT91_TC_TIMER_CLOCK1 (0 << 0) | ||
| 47 | #define AT91_TC_TIMER_CLOCK2 (1 << 0) | ||
| 48 | #define AT91_TC_TIMER_CLOCK3 (2 << 0) | ||
| 49 | #define AT91_TC_TIMER_CLOCK4 (3 << 0) | ||
| 50 | #define AT91_TC_TIMER_CLOCK5 (4 << 0) | ||
| 51 | #define AT91_TC_XC0 (5 << 0) | ||
| 52 | #define AT91_TC_XC1 (6 << 0) | ||
| 53 | #define AT91_TC_XC2 (7 << 0) | ||
| 54 | #define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */ | ||
| 55 | #define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */ | ||
| 56 | #define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */ | ||
| 57 | #define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */ | ||
| 58 | #define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */ | ||
| 59 | #define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */ | ||
| 60 | #define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */ | ||
| 61 | #define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */ | ||
| 62 | #define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */ | ||
| 63 | #define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */ | ||
| 64 | |||
| 65 | #define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */ | ||
| 66 | #define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */ | ||
| 67 | #define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */ | ||
| 68 | #define AT91_TC_EEVTEDG_NONE (0 << 8) | ||
| 69 | #define AT91_TC_EEVTEDG_RISING (1 << 8) | ||
| 70 | #define AT91_TC_EEVTEDG_FALLING (2 << 8) | ||
| 71 | #define AT91_TC_EEVTEDG_BOTH (3 << 8) | ||
| 72 | #define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */ | ||
| 73 | #define AT91_TC_EEVT_TIOB (0 << 10) | ||
| 74 | #define AT91_TC_EEVT_XC0 (1 << 10) | ||
| 75 | #define AT91_TC_EEVT_XC1 (2 << 10) | ||
| 76 | #define AT91_TC_EEVT_XC2 (3 << 10) | ||
| 77 | #define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */ | ||
| 78 | #define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */ | ||
| 79 | #define AT91_TC_WAVESEL_UP (0 << 13) | ||
| 80 | #define AT91_TC_WAVESEL_UP_AUTO (2 << 13) | ||
| 81 | #define AT91_TC_WAVESEL_UPDOWN (1 << 13) | ||
| 82 | #define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13) | ||
| 83 | #define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */ | ||
| 84 | #define AT91_TC_ACPA_NONE (0 << 16) | ||
| 85 | #define AT91_TC_ACPA_SET (1 << 16) | ||
| 86 | #define AT91_TC_ACPA_CLEAR (2 << 16) | ||
| 87 | #define AT91_TC_ACPA_TOGGLE (3 << 16) | ||
| 88 | #define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */ | ||
| 89 | #define AT91_TC_ACPC_NONE (0 << 18) | ||
| 90 | #define AT91_TC_ACPC_SET (1 << 18) | ||
| 91 | #define AT91_TC_ACPC_CLEAR (2 << 18) | ||
| 92 | #define AT91_TC_ACPC_TOGGLE (3 << 18) | ||
| 93 | #define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */ | ||
| 94 | #define AT91_TC_AEEVT_NONE (0 << 20) | ||
| 95 | #define AT91_TC_AEEVT_SET (1 << 20) | ||
| 96 | #define AT91_TC_AEEVT_CLEAR (2 << 20) | ||
| 97 | #define AT91_TC_AEEVT_TOGGLE (3 << 20) | ||
| 98 | #define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */ | ||
| 99 | #define AT91_TC_ASWTRG_NONE (0 << 22) | ||
| 100 | #define AT91_TC_ASWTRG_SET (1 << 22) | ||
| 101 | #define AT91_TC_ASWTRG_CLEAR (2 << 22) | ||
| 102 | #define AT91_TC_ASWTRG_TOGGLE (3 << 22) | ||
| 103 | #define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */ | ||
| 104 | #define AT91_TC_BCPB_NONE (0 << 24) | ||
| 105 | #define AT91_TC_BCPB_SET (1 << 24) | ||
| 106 | #define AT91_TC_BCPB_CLEAR (2 << 24) | ||
| 107 | #define AT91_TC_BCPB_TOGGLE (3 << 24) | ||
| 108 | #define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */ | ||
| 109 | #define AT91_TC_BCPC_NONE (0 << 26) | ||
| 110 | #define AT91_TC_BCPC_SET (1 << 26) | ||
| 111 | #define AT91_TC_BCPC_CLEAR (2 << 26) | ||
| 112 | #define AT91_TC_BCPC_TOGGLE (3 << 26) | ||
| 113 | #define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */ | ||
| 114 | #define AT91_TC_BEEVT_NONE (0 << 28) | ||
| 115 | #define AT91_TC_BEEVT_SET (1 << 28) | ||
| 116 | #define AT91_TC_BEEVT_CLEAR (2 << 28) | ||
| 117 | #define AT91_TC_BEEVT_TOGGLE (3 << 28) | ||
| 118 | #define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */ | ||
| 119 | #define AT91_TC_BSWTRG_NONE (0 << 30) | ||
| 120 | #define AT91_TC_BSWTRG_SET (1 << 30) | ||
| 121 | #define AT91_TC_BSWTRG_CLEAR (2 << 30) | ||
| 122 | #define AT91_TC_BSWTRG_TOGGLE (3 << 30) | ||
| 123 | |||
| 124 | #define AT91_TC_CV 0x10 /* Counter Value */ | ||
| 125 | #define AT91_TC_RA 0x14 /* Register A */ | ||
| 126 | #define AT91_TC_RB 0x18 /* Register B */ | ||
| 127 | #define AT91_TC_RC 0x1c /* Register C */ | ||
| 128 | |||
| 129 | #define AT91_TC_SR 0x20 /* Status Register */ | ||
| 130 | #define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */ | ||
| 131 | #define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */ | ||
| 132 | #define AT91_TC_CPAS (1 << 2) /* RA Compare Status */ | ||
| 133 | #define AT91_TC_CPBS (1 << 3) /* RB Compare Status */ | ||
| 134 | #define AT91_TC_CPCS (1 << 4) /* RC Compare Status */ | ||
| 135 | #define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */ | ||
| 136 | #define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */ | ||
| 137 | #define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */ | ||
| 138 | #define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */ | ||
| 139 | #define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */ | ||
| 140 | #define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */ | ||
| 141 | |||
| 142 | #define AT91_TC_IER 0x24 /* Interrupt Enable Register */ | ||
| 143 | #define AT91_TC_IDR 0x28 /* Interrupt Disable Register */ | ||
| 144 | #define AT91_TC_IMR 0x2c /* Interrupt Mask Register */ | ||
| 145 | |||
| 146 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_twi.h b/arch/arm/mach-at91/include/mach/at91_twi.h new file mode 100644 index 000000000000..bb2880f6ba37 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_twi.h | |||
| @@ -0,0 +1,68 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_twi.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Two-wire Interface (TWI) registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_TWI_H | ||
| 17 | #define AT91_TWI_H | ||
| 18 | |||
| 19 | #define AT91_TWI_CR 0x00 /* Control Register */ | ||
| 20 | #define AT91_TWI_START (1 << 0) /* Send a Start Condition */ | ||
| 21 | #define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */ | ||
| 22 | #define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */ | ||
| 23 | #define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */ | ||
| 24 | #define AT91_TWI_SVEN (1 << 4) /* Slave Transfer Enable [SAM9260 only] */ | ||
| 25 | #define AT91_TWI_SVDIS (1 << 5) /* Slave Transfer Disable [SAM9260 only] */ | ||
| 26 | #define AT91_TWI_SWRST (1 << 7) /* Software Reset */ | ||
| 27 | |||
| 28 | #define AT91_TWI_MMR 0x04 /* Master Mode Register */ | ||
| 29 | #define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */ | ||
| 30 | #define AT91_TWI_IADRSZ_NO (0 << 8) | ||
| 31 | #define AT91_TWI_IADRSZ_1 (1 << 8) | ||
| 32 | #define AT91_TWI_IADRSZ_2 (2 << 8) | ||
| 33 | #define AT91_TWI_IADRSZ_3 (3 << 8) | ||
| 34 | #define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */ | ||
| 35 | #define AT91_TWI_DADR (0x7f << 16) /* Device Address */ | ||
| 36 | |||
| 37 | #define AT91_TWI_SMR 0x08 /* Slave Mode Register [SAM9260 only] */ | ||
| 38 | #define AT91_TWI_SADR (0x7f << 16) /* Slave Address */ | ||
| 39 | |||
| 40 | #define AT91_TWI_IADR 0x0c /* Internal Address Register */ | ||
| 41 | |||
| 42 | #define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */ | ||
| 43 | #define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */ | ||
| 44 | #define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */ | ||
| 45 | #define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */ | ||
| 46 | |||
| 47 | #define AT91_TWI_SR 0x20 /* Status Register */ | ||
| 48 | #define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ | ||
| 49 | #define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ | ||
| 50 | #define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ | ||
| 51 | #define AT91_TWI_SVREAD (1 << 3) /* Slave Read [SAM9260 only] */ | ||
| 52 | #define AT91_TWI_SVACC (1 << 4) /* Slave Access [SAM9260 only] */ | ||
| 53 | #define AT91_TWI_GACC (1 << 5) /* General Call Access [SAM9260 only] */ | ||
| 54 | #define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */ | ||
| 55 | #define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */ | ||
| 56 | #define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ | ||
| 57 | #define AT91_TWI_ARBLST (1 << 9) /* Arbitration Lost [SAM9260 only] */ | ||
| 58 | #define AT91_TWI_SCLWS (1 << 10) /* Clock Wait State [SAM9260 only] */ | ||
| 59 | #define AT91_TWI_EOSACC (1 << 11) /* End of Slave Address [SAM9260 only] */ | ||
| 60 | |||
| 61 | #define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ | ||
| 62 | #define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */ | ||
| 63 | #define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */ | ||
| 64 | #define AT91_TWI_RHR 0x30 /* Receive Holding Register */ | ||
| 65 | #define AT91_TWI_THR 0x34 /* Transmit Holding Register */ | ||
| 66 | |||
| 67 | #endif | ||
| 68 | |||
diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h new file mode 100644 index 000000000000..973b4526a98e --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91_wdt.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91_wdt.h | ||
| 3 | * | ||
| 4 | * Watchdog Timer (WDT) - System peripherals regsters. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91_WDT_H | ||
| 14 | #define AT91_WDT_H | ||
| 15 | |||
| 16 | #define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ | ||
| 17 | #define AT91_WDT_WDRSTT (1 << 0) /* Restart */ | ||
| 18 | #define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ | ||
| 19 | |||
| 20 | #define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ | ||
| 21 | #define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ | ||
| 22 | #define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ | ||
| 23 | #define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ | ||
| 24 | #define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ | ||
| 25 | #define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ | ||
| 26 | #define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ | ||
| 27 | #define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ | ||
| 28 | #define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ | ||
| 29 | |||
| 30 | #define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ | ||
| 31 | #define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ | ||
| 32 | #define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ | ||
| 33 | |||
| 34 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h new file mode 100644 index 000000000000..4a4b64135a92 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91cap9.h | |||
| @@ -0,0 +1,126 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91cap9.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> | ||
| 5 | * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> | ||
| 6 | * Copyright (C) 2007 Atmel Corporation. | ||
| 7 | * | ||
| 8 | * Common definitions. | ||
| 9 | * Based on AT91CAP9 datasheet revision B (Preliminary). | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License as published by | ||
| 13 | * the Free Software Foundation; either version 2 of the License, or | ||
| 14 | * (at your option) any later version. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef AT91CAP9_H | ||
| 18 | #define AT91CAP9_H | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Peripheral identifiers/interrupts. | ||
| 22 | */ | ||
| 23 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 24 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 25 | #define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */ | ||
| 26 | #define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */ | ||
| 27 | #define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */ | ||
| 28 | #define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */ | ||
| 29 | #define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */ | ||
| 30 | #define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */ | ||
| 31 | #define AT91CAP9_ID_US0 8 /* USART 0 */ | ||
| 32 | #define AT91CAP9_ID_US1 9 /* USART 1 */ | ||
| 33 | #define AT91CAP9_ID_US2 10 /* USART 2 */ | ||
| 34 | #define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */ | ||
| 35 | #define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */ | ||
| 36 | #define AT91CAP9_ID_CAN 13 /* CAN */ | ||
| 37 | #define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */ | ||
| 38 | #define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */ | ||
| 39 | #define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */ | ||
| 40 | #define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */ | ||
| 41 | #define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */ | ||
| 42 | #define AT91CAP9_ID_AC97C 19 /* AC97 Controller */ | ||
| 43 | #define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */ | ||
| 44 | #define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */ | ||
| 45 | #define AT91CAP9_ID_EMAC 22 /* Ethernet */ | ||
| 46 | #define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */ | ||
| 47 | #define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */ | ||
| 48 | #define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */ | ||
| 49 | #define AT91CAP9_ID_LCDC 26 /* LCD Controller */ | ||
| 50 | #define AT91CAP9_ID_DMA 27 /* DMA Controller */ | ||
| 51 | #define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */ | ||
| 52 | #define AT91CAP9_ID_UHP 29 /* USB Host Port */ | ||
| 53 | #define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 54 | #define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 55 | |||
| 56 | /* | ||
| 57 | * User Peripheral physical base addresses. | ||
| 58 | */ | ||
| 59 | #define AT91CAP9_BASE_UDPHS 0xfff78000 | ||
| 60 | #define AT91CAP9_BASE_TCB0 0xfff7c000 | ||
| 61 | #define AT91CAP9_BASE_TC0 0xfff7c000 | ||
| 62 | #define AT91CAP9_BASE_TC1 0xfff7c040 | ||
| 63 | #define AT91CAP9_BASE_TC2 0xfff7c080 | ||
| 64 | #define AT91CAP9_BASE_MCI0 0xfff80000 | ||
| 65 | #define AT91CAP9_BASE_MCI1 0xfff84000 | ||
| 66 | #define AT91CAP9_BASE_TWI 0xfff88000 | ||
| 67 | #define AT91CAP9_BASE_US0 0xfff8c000 | ||
| 68 | #define AT91CAP9_BASE_US1 0xfff90000 | ||
| 69 | #define AT91CAP9_BASE_US2 0xfff94000 | ||
| 70 | #define AT91CAP9_BASE_SSC0 0xfff98000 | ||
| 71 | #define AT91CAP9_BASE_SSC1 0xfff9c000 | ||
| 72 | #define AT91CAP9_BASE_AC97C 0xfffa0000 | ||
| 73 | #define AT91CAP9_BASE_SPI0 0xfffa4000 | ||
| 74 | #define AT91CAP9_BASE_SPI1 0xfffa8000 | ||
| 75 | #define AT91CAP9_BASE_CAN 0xfffac000 | ||
| 76 | #define AT91CAP9_BASE_PWMC 0xfffb8000 | ||
| 77 | #define AT91CAP9_BASE_EMAC 0xfffbc000 | ||
| 78 | #define AT91CAP9_BASE_ADC 0xfffc0000 | ||
| 79 | #define AT91CAP9_BASE_ISI 0xfffc4000 | ||
| 80 | #define AT91_BASE_SYS 0xffffe200 | ||
| 81 | |||
| 82 | /* | ||
| 83 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 84 | */ | ||
| 85 | #define AT91_ECC (0xffffe200 - AT91_BASE_SYS) | ||
| 86 | #define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS) | ||
| 87 | #define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS) | ||
| 88 | #define AT91_SMC (0xffffe800 - AT91_BASE_SYS) | ||
| 89 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) | ||
| 90 | #define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS) | ||
| 91 | #define AT91_DMA (0xffffec00 - AT91_BASE_SYS) | ||
| 92 | #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) | ||
| 93 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 94 | #define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) | ||
| 95 | #define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) | ||
| 96 | #define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) | ||
| 97 | #define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) | ||
| 98 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 99 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 100 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 101 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
| 102 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 103 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 104 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | ||
| 105 | |||
| 106 | #define AT91_USART0 AT91CAP9_BASE_US0 | ||
| 107 | #define AT91_USART1 AT91CAP9_BASE_US1 | ||
| 108 | #define AT91_USART2 AT91CAP9_BASE_US2 | ||
| 109 | |||
| 110 | |||
| 111 | /* | ||
| 112 | * Internal Memory. | ||
| 113 | */ | ||
| 114 | #define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */ | ||
| 115 | #define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */ | ||
| 116 | |||
| 117 | #define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */ | ||
| 118 | #define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */ | ||
| 119 | |||
| 120 | #define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */ | ||
| 121 | #define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */ | ||
| 122 | #define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */ | ||
| 123 | |||
| 124 | #define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 | ||
| 125 | |||
| 126 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h new file mode 100644 index 000000000000..bca878f3bd87 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h | |||
| @@ -0,0 +1,100 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h | ||
| 3 | * | ||
| 4 | * DDR/SDR Controller (DDRSDRC) - System peripherals registers. | ||
| 5 | * Based on AT91CAP9 datasheet revision B. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91CAP9_DDRSDR_H | ||
| 14 | #define AT91CAP9_DDRSDR_H | ||
| 15 | |||
| 16 | #define AT91_DDRSDRC_MR (AT91_DDRSDRC + 0x00) /* Mode Register */ | ||
| 17 | #define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */ | ||
| 18 | #define AT91_DDRSDRC_MODE_NORMAL 0 | ||
| 19 | #define AT91_DDRSDRC_MODE_NOP 1 | ||
| 20 | #define AT91_DDRSDRC_MODE_PRECHARGE 2 | ||
| 21 | #define AT91_DDRSDRC_MODE_LMR 3 | ||
| 22 | #define AT91_DDRSDRC_MODE_REFRESH 4 | ||
| 23 | #define AT91_DDRSDRC_MODE_EXT_LMR 5 | ||
| 24 | #define AT91_DDRSDRC_MODE_DEEP 6 | ||
| 25 | |||
| 26 | #define AT91_DDRSDRC_RTR (AT91_DDRSDRC + 0x04) /* Refresh Timer Register */ | ||
| 27 | #define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ | ||
| 28 | |||
| 29 | #define AT91_DDRSDRC_CR (AT91_DDRSDRC + 0x08) /* Configuration Register */ | ||
| 30 | #define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ | ||
| 31 | #define AT91_DDRSDRC_NC_SDR8 (0 << 0) | ||
| 32 | #define AT91_DDRSDRC_NC_SDR9 (1 << 0) | ||
| 33 | #define AT91_DDRSDRC_NC_SDR10 (2 << 0) | ||
| 34 | #define AT91_DDRSDRC_NC_SDR11 (3 << 0) | ||
| 35 | #define AT91_DDRSDRC_NC_DDR9 (0 << 0) | ||
| 36 | #define AT91_DDRSDRC_NC_DDR10 (1 << 0) | ||
| 37 | #define AT91_DDRSDRC_NC_DDR11 (2 << 0) | ||
| 38 | #define AT91_DDRSDRC_NC_DDR12 (3 << 0) | ||
| 39 | #define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */ | ||
| 40 | #define AT91_DDRSDRC_NR_11 (0 << 2) | ||
| 41 | #define AT91_DDRSDRC_NR_12 (1 << 2) | ||
| 42 | #define AT91_DDRSDRC_NR_13 (2 << 2) | ||
| 43 | #define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ | ||
| 44 | #define AT91_DDRSDRC_CAS_2 (2 << 4) | ||
| 45 | #define AT91_DDRSDRC_CAS_3 (3 << 4) | ||
| 46 | #define AT91_DDRSDRC_CAS_25 (6 << 4) | ||
| 47 | #define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */ | ||
| 48 | #define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ | ||
| 49 | |||
| 50 | #define AT91_DDRSDRC_T0PR (AT91_DDRSDRC + 0x0C) /* Timing 0 Register */ | ||
| 51 | #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ | ||
| 52 | #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ | ||
| 53 | #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ | ||
| 54 | #define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ | ||
| 55 | #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ | ||
| 56 | #define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ | ||
| 57 | #define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ | ||
| 58 | #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ | ||
| 59 | |||
| 60 | #define AT91_DDRSDRC_T1PR (AT91_DDRSDRC + 0x10) /* Timing 1 Register */ | ||
| 61 | #define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ | ||
| 62 | #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ | ||
| 63 | #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ | ||
| 64 | #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ | ||
| 65 | |||
| 66 | #define AT91_DDRSDRC_LPR (AT91_DDRSDRC + 0x18) /* Low Power Register */ | ||
| 67 | #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ | ||
| 68 | #define AT91_DDRSDRC_LPCB_DISABLE 0 | ||
| 69 | #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 | ||
| 70 | #define AT91_DDRSDRC_LPCB_POWER_DOWN 2 | ||
| 71 | #define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 | ||
| 72 | #define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ | ||
| 73 | #define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ | ||
| 74 | #define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ | ||
| 75 | #define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ | ||
| 76 | #define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ | ||
| 77 | #define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12) | ||
| 78 | #define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) | ||
| 79 | #define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) | ||
| 80 | |||
| 81 | #define AT91_DDRSDRC_MDR (AT91_DDRSDRC + 0x1C) /* Memory Device Register */ | ||
| 82 | #define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ | ||
| 83 | #define AT91_DDRSDRC_MD_SDR 0 | ||
| 84 | #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 | ||
| 85 | #define AT91_DDRSDRC_MD_DDR 2 | ||
| 86 | #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 | ||
| 87 | |||
| 88 | #define AT91_DDRSDRC_DLLR (AT91_DDRSDRC + 0x20) /* DLL Information Register */ | ||
| 89 | #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ | ||
| 90 | #define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ | ||
| 91 | #define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ | ||
| 92 | #define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */ | ||
| 93 | #define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */ | ||
| 94 | #define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */ | ||
| 95 | #define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ | ||
| 96 | #define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ | ||
| 97 | #define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ | ||
| 98 | |||
| 99 | |||
| 100 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_matrix.h b/arch/arm/mach-at91/include/mach/at91cap9_matrix.h new file mode 100644 index 000000000000..4b9d4aff4b4f --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91cap9_matrix.h | |||
| @@ -0,0 +1,137 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91cap9_matrix.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com> | ||
| 5 | * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> | ||
| 6 | * Copyright (C) 2006 Atmel Corporation. | ||
| 7 | * | ||
| 8 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 9 | * Based on AT91CAP9 datasheet revision B (Preliminary). | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License as published by | ||
| 13 | * the Free Software Foundation; either version 2 of the License, or | ||
| 14 | * (at your option) any later version. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef AT91CAP9_MATRIX_H | ||
| 18 | #define AT91CAP9_MATRIX_H | ||
| 19 | |||
| 20 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
| 21 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
| 22 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
| 23 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
| 24 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
| 25 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ | ||
| 26 | #define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ | ||
| 27 | #define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ | ||
| 28 | #define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ | ||
| 29 | #define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ | ||
| 30 | #define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ | ||
| 31 | #define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ | ||
| 32 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
| 33 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
| 34 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
| 35 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
| 36 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
| 37 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
| 38 | |||
| 39 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
| 40 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
| 41 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
| 42 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
| 43 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
| 44 | #define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ | ||
| 45 | #define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ | ||
| 46 | #define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ | ||
| 47 | #define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */ | ||
| 48 | #define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */ | ||
| 49 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 50 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 51 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 52 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 53 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 54 | #define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ | ||
| 55 | #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ | ||
| 56 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | ||
| 57 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | ||
| 58 | |||
| 59 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
| 60 | #define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ | ||
| 61 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
| 62 | #define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ | ||
| 63 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
| 64 | #define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ | ||
| 65 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
| 66 | #define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ | ||
| 67 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
| 68 | #define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ | ||
| 69 | #define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ | ||
| 70 | #define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ | ||
| 71 | #define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ | ||
| 72 | #define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ | ||
| 73 | #define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ | ||
| 74 | #define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ | ||
| 75 | #define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */ | ||
| 76 | #define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */ | ||
| 77 | #define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */ | ||
| 78 | #define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */ | ||
| 79 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
| 80 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
| 81 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
| 82 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
| 83 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
| 84 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
| 85 | #define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ | ||
| 86 | #define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ | ||
| 87 | #define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ | ||
| 88 | #define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ | ||
| 89 | #define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ | ||
| 90 | #define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ | ||
| 91 | |||
| 92 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
| 93 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 94 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 95 | #define AT91_MATRIX_RCB2 (1 << 2) | ||
| 96 | #define AT91_MATRIX_RCB3 (1 << 3) | ||
| 97 | #define AT91_MATRIX_RCB4 (1 << 4) | ||
| 98 | #define AT91_MATRIX_RCB5 (1 << 5) | ||
| 99 | #define AT91_MATRIX_RCB6 (1 << 6) | ||
| 100 | #define AT91_MATRIX_RCB7 (1 << 7) | ||
| 101 | #define AT91_MATRIX_RCB8 (1 << 8) | ||
| 102 | #define AT91_MATRIX_RCB9 (1 << 9) | ||
| 103 | #define AT91_MATRIX_RCB10 (1 << 10) | ||
| 104 | #define AT91_MATRIX_RCB11 (1 << 11) | ||
| 105 | |||
| 106 | #define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */ | ||
| 107 | #define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */ | ||
| 108 | |||
| 109 | #define AT91_MATRIX_UDPHS (AT91_MATRIX + 0x118) /* USBHS Special Function Register [AT91CAP9 only] */ | ||
| 110 | #define AT91_MATRIX_SELECT_UDPHS (0 << 31) /* select High Speed UDP */ | ||
| 111 | #define AT91_MATRIX_SELECT_UDP (1 << 31) /* select standard UDP */ | ||
| 112 | #define AT91_MATRIX_UDPHS_BYPASS_LOCK (1 << 30) /* bypass lock bit */ | ||
| 113 | |||
| 114 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */ | ||
| 115 | #define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 116 | #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) | ||
| 117 | #define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1) | ||
| 118 | #define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 119 | #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) | ||
| 120 | #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 121 | #define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 122 | #define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) | ||
| 123 | #define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4) | ||
| 124 | #define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
| 125 | #define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) | ||
| 126 | #define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5) | ||
| 127 | #define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 128 | #define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */ | ||
| 129 | #define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 130 | #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) | ||
| 131 | #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) | ||
| 132 | |||
| 133 | #define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */ | ||
| 134 | #define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */ | ||
| 135 | #define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */ | ||
| 136 | |||
| 137 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h new file mode 100644 index 000000000000..78983155a074 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91rm9200.h | |||
| @@ -0,0 +1,115 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91rm9200.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Common definitions. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91RM9200_H | ||
| 17 | #define AT91RM9200_H | ||
| 18 | |||
| 19 | /* | ||
| 20 | * Peripheral identifiers/interrupts. | ||
| 21 | */ | ||
| 22 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 23 | #define AT91_ID_SYS 1 /* System Peripheral */ | ||
| 24 | #define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 25 | #define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 26 | #define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */ | ||
| 27 | #define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */ | ||
| 28 | #define AT91RM9200_ID_US0 6 /* USART 0 */ | ||
| 29 | #define AT91RM9200_ID_US1 7 /* USART 1 */ | ||
| 30 | #define AT91RM9200_ID_US2 8 /* USART 2 */ | ||
| 31 | #define AT91RM9200_ID_US3 9 /* USART 3 */ | ||
| 32 | #define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */ | ||
| 33 | #define AT91RM9200_ID_UDP 11 /* USB Device Port */ | ||
| 34 | #define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */ | ||
| 35 | #define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */ | ||
| 36 | #define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */ | ||
| 37 | #define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */ | ||
| 38 | #define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */ | ||
| 39 | #define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */ | ||
| 40 | #define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */ | ||
| 41 | #define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */ | ||
| 42 | #define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */ | ||
| 43 | #define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */ | ||
| 44 | #define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */ | ||
| 45 | #define AT91RM9200_ID_UHP 23 /* USB Host port */ | ||
| 46 | #define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */ | ||
| 47 | #define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 48 | #define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 49 | #define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ | ||
| 50 | #define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ | ||
| 51 | #define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ | ||
| 52 | #define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ | ||
| 53 | #define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ | ||
| 54 | |||
| 55 | |||
| 56 | /* | ||
| 57 | * Peripheral physical base addresses. | ||
| 58 | */ | ||
| 59 | #define AT91RM9200_BASE_TCB0 0xfffa0000 | ||
| 60 | #define AT91RM9200_BASE_TC0 0xfffa0000 | ||
| 61 | #define AT91RM9200_BASE_TC1 0xfffa0040 | ||
| 62 | #define AT91RM9200_BASE_TC2 0xfffa0080 | ||
| 63 | #define AT91RM9200_BASE_TCB1 0xfffa4000 | ||
| 64 | #define AT91RM9200_BASE_TC3 0xfffa4000 | ||
| 65 | #define AT91RM9200_BASE_TC4 0xfffa4040 | ||
| 66 | #define AT91RM9200_BASE_TC5 0xfffa4080 | ||
| 67 | #define AT91RM9200_BASE_UDP 0xfffb0000 | ||
| 68 | #define AT91RM9200_BASE_MCI 0xfffb4000 | ||
| 69 | #define AT91RM9200_BASE_TWI 0xfffb8000 | ||
| 70 | #define AT91RM9200_BASE_EMAC 0xfffbc000 | ||
| 71 | #define AT91RM9200_BASE_US0 0xfffc0000 | ||
| 72 | #define AT91RM9200_BASE_US1 0xfffc4000 | ||
| 73 | #define AT91RM9200_BASE_US2 0xfffc8000 | ||
| 74 | #define AT91RM9200_BASE_US3 0xfffcc000 | ||
| 75 | #define AT91RM9200_BASE_SSC0 0xfffd0000 | ||
| 76 | #define AT91RM9200_BASE_SSC1 0xfffd4000 | ||
| 77 | #define AT91RM9200_BASE_SSC2 0xfffd8000 | ||
| 78 | #define AT91RM9200_BASE_SPI 0xfffe0000 | ||
| 79 | #define AT91_BASE_SYS 0xfffff000 | ||
| 80 | |||
| 81 | |||
| 82 | /* | ||
| 83 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 84 | */ | ||
| 85 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ | ||
| 86 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */ | ||
| 87 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */ | ||
| 88 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */ | ||
| 89 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */ | ||
| 90 | #define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */ | ||
| 91 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */ | ||
| 92 | #define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */ | ||
| 93 | #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */ | ||
| 94 | #define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ | ||
| 95 | |||
| 96 | #define AT91_USART0 AT91RM9200_BASE_US0 | ||
| 97 | #define AT91_USART1 AT91RM9200_BASE_US1 | ||
| 98 | #define AT91_USART2 AT91RM9200_BASE_US2 | ||
| 99 | #define AT91_USART3 AT91RM9200_BASE_US3 | ||
| 100 | |||
| 101 | #define AT91_MATRIX 0 /* not supported */ | ||
| 102 | |||
| 103 | /* | ||
| 104 | * Internal Memory. | ||
| 105 | */ | ||
| 106 | #define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */ | ||
| 107 | #define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ | ||
| 108 | |||
| 109 | #define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */ | ||
| 110 | #define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ | ||
| 111 | |||
| 112 | #define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */ | ||
| 113 | |||
| 114 | |||
| 115 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_emac.h b/arch/arm/mach-at91/include/mach/at91rm9200_emac.h new file mode 100644 index 000000000000..b8260cd8041c --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91rm9200_emac.h | |||
| @@ -0,0 +1,138 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91rm9200_emac.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Ethernet MAC registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91RM9200_EMAC_H | ||
| 17 | #define AT91RM9200_EMAC_H | ||
| 18 | |||
| 19 | #define AT91_EMAC_CTL 0x00 /* Control Register */ | ||
| 20 | #define AT91_EMAC_LB (1 << 0) /* Loopback */ | ||
| 21 | #define AT91_EMAC_LBL (1 << 1) /* Loopback Local */ | ||
| 22 | #define AT91_EMAC_RE (1 << 2) /* Receive Enable */ | ||
| 23 | #define AT91_EMAC_TE (1 << 3) /* Transmit Enable */ | ||
| 24 | #define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */ | ||
| 25 | #define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */ | ||
| 26 | #define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */ | ||
| 27 | #define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */ | ||
| 28 | #define AT91_EMAC_BP (1 << 8) /* Back Pressure */ | ||
| 29 | |||
| 30 | #define AT91_EMAC_CFG 0x04 /* Configuration Register */ | ||
| 31 | #define AT91_EMAC_SPD (1 << 0) /* Speed */ | ||
| 32 | #define AT91_EMAC_FD (1 << 1) /* Full Duplex */ | ||
| 33 | #define AT91_EMAC_BR (1 << 2) /* Bit Rate */ | ||
| 34 | #define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */ | ||
| 35 | #define AT91_EMAC_NBC (1 << 5) /* No Broadcast */ | ||
| 36 | #define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */ | ||
| 37 | #define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */ | ||
| 38 | #define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */ | ||
| 39 | #define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */ | ||
| 40 | #define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */ | ||
| 41 | #define AT91_EMAC_CLK_DIV8 (0 << 10) | ||
| 42 | #define AT91_EMAC_CLK_DIV16 (1 << 10) | ||
| 43 | #define AT91_EMAC_CLK_DIV32 (2 << 10) | ||
| 44 | #define AT91_EMAC_CLK_DIV64 (3 << 10) | ||
| 45 | #define AT91_EMAC_RTY (1 << 12) /* Retry Test */ | ||
| 46 | #define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */ | ||
| 47 | |||
| 48 | #define AT91_EMAC_SR 0x08 /* Status Register */ | ||
| 49 | #define AT91_EMAC_SR_LINK (1 << 0) /* Link */ | ||
| 50 | #define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */ | ||
| 51 | #define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */ | ||
| 52 | |||
| 53 | #define AT91_EMAC_TAR 0x0c /* Transmit Address Register */ | ||
| 54 | |||
| 55 | #define AT91_EMAC_TCR 0x10 /* Transmit Control Register */ | ||
| 56 | #define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */ | ||
| 57 | #define AT91_EMAC_NCRC (1 << 15) /* No CRC */ | ||
| 58 | |||
| 59 | #define AT91_EMAC_TSR 0x14 /* Transmit Status Register */ | ||
| 60 | #define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */ | ||
| 61 | #define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */ | ||
| 62 | #define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */ | ||
| 63 | #define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */ | ||
| 64 | #define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */ | ||
| 65 | #define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */ | ||
| 66 | #define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */ | ||
| 67 | |||
| 68 | #define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */ | ||
| 69 | |||
| 70 | #define AT91_EMAC_RSR 0x20 /* Receive Status Register */ | ||
| 71 | #define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */ | ||
| 72 | #define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */ | ||
| 73 | #define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */ | ||
| 74 | |||
| 75 | #define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */ | ||
| 76 | #define AT91_EMAC_DONE (1 << 0) /* Management Done */ | ||
| 77 | #define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */ | ||
| 78 | #define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */ | ||
| 79 | #define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */ | ||
| 80 | #define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */ | ||
| 81 | #define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */ | ||
| 82 | #define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */ | ||
| 83 | #define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */ | ||
| 84 | #define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */ | ||
| 85 | #define AT91_EMAC_LINK (1 << 9) /* Link */ | ||
| 86 | #define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */ | ||
| 87 | #define AT91_EMAC_ABT (1 << 11) /* Abort */ | ||
| 88 | |||
| 89 | #define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */ | ||
| 90 | #define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */ | ||
| 91 | #define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */ | ||
| 92 | |||
| 93 | #define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */ | ||
| 94 | #define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */ | ||
| 95 | #define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */ | ||
| 96 | #define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */ | ||
| 97 | #define AT91_EMAC_RW (3 << 28) /* Read/Write operation */ | ||
| 98 | #define AT91_EMAC_RW_W (1 << 28) | ||
| 99 | #define AT91_EMAC_RW_R (2 << 28) | ||
| 100 | #define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */ | ||
| 101 | |||
| 102 | /* | ||
| 103 | * Statistics Registers. | ||
| 104 | */ | ||
| 105 | #define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */ | ||
| 106 | #define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */ | ||
| 107 | #define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */ | ||
| 108 | #define AT91_EMAC_OK 0x4c /* Frames Received OK */ | ||
| 109 | #define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */ | ||
| 110 | #define AT91_EMAC_ALE 0x54 /* Alignmemt Error */ | ||
| 111 | #define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */ | ||
| 112 | #define AT91_EMAC_LCOL 0x5c /* Late Collision */ | ||
| 113 | #define AT91_EMAC_ECOL 0x60 /* Excessive Collision */ | ||
| 114 | #define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */ | ||
| 115 | #define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */ | ||
| 116 | #define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */ | ||
| 117 | #define AT91_EMAC_ROV 0x70 /* Receive Overrun */ | ||
| 118 | #define AT91_EMAC_CDE 0x74 /* Code Error */ | ||
| 119 | #define AT91_EMAC_ELR 0x78 /* Excessive Length Error */ | ||
| 120 | #define AT91_EMAC_RJB 0x7c /* Receive Jabber */ | ||
| 121 | #define AT91_EMAC_USF 0x80 /* Undersize Frame */ | ||
| 122 | #define AT91_EMAC_SQEE 0x84 /* SQE Test Error */ | ||
| 123 | |||
| 124 | /* | ||
| 125 | * Address Registers. | ||
| 126 | */ | ||
| 127 | #define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */ | ||
| 128 | #define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */ | ||
| 129 | #define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */ | ||
| 130 | #define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */ | ||
| 131 | #define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */ | ||
| 132 | #define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */ | ||
| 133 | #define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */ | ||
| 134 | #define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */ | ||
| 135 | #define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */ | ||
| 136 | #define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */ | ||
| 137 | |||
| 138 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h new file mode 100644 index 000000000000..d34e4ed89349 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h | |||
| @@ -0,0 +1,160 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91rm9200_mc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91RM9200_MC_H | ||
| 17 | #define AT91RM9200_MC_H | ||
| 18 | |||
| 19 | /* Memory Controller */ | ||
| 20 | #define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */ | ||
| 21 | #define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ | ||
| 22 | |||
| 23 | #define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ | ||
| 24 | #define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */ | ||
| 25 | #define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */ | ||
| 26 | #define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */ | ||
| 27 | #define AT91_MC_ABTSZ_BYTE (0 << 8) | ||
| 28 | #define AT91_MC_ABTSZ_HALFWORD (1 << 8) | ||
| 29 | #define AT91_MC_ABTSZ_WORD (2 << 8) | ||
| 30 | #define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */ | ||
| 31 | #define AT91_MC_ABTTYP_DATAREAD (0 << 10) | ||
| 32 | #define AT91_MC_ABTTYP_DATAWRITE (1 << 10) | ||
| 33 | #define AT91_MC_ABTTYP_FETCH (2 << 10) | ||
| 34 | #define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */ | ||
| 35 | #define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */ | ||
| 36 | #define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */ | ||
| 37 | #define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */ | ||
| 38 | #define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */ | ||
| 39 | #define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */ | ||
| 40 | #define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */ | ||
| 41 | #define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */ | ||
| 42 | |||
| 43 | #define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ | ||
| 44 | |||
| 45 | #define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ | ||
| 46 | #define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */ | ||
| 47 | #define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */ | ||
| 48 | #define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */ | ||
| 49 | #define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */ | ||
| 50 | |||
| 51 | /* External Bus Interface (EBI) registers */ | ||
| 52 | #define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ | ||
| 53 | #define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */ | ||
| 54 | #define AT91_EBI_CS0A_SMC (0 << 0) | ||
| 55 | #define AT91_EBI_CS0A_BFC (1 << 0) | ||
| 56 | #define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 57 | #define AT91_EBI_CS1A_SMC (0 << 1) | ||
| 58 | #define AT91_EBI_CS1A_SDRAMC (1 << 1) | ||
| 59 | #define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */ | ||
| 60 | #define AT91_EBI_CS3A_SMC (0 << 3) | ||
| 61 | #define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 62 | #define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */ | ||
| 63 | #define AT91_EBI_CS4A_SMC (0 << 4) | ||
| 64 | #define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4) | ||
| 65 | #define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */ | ||
| 66 | #define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */ | ||
| 67 | |||
| 68 | /* Static Memory Controller (SMC) registers */ | ||
| 69 | #define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ | ||
| 70 | #define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ | ||
| 71 | #define AT91_SMC_NWS_(x) ((x) << 0) | ||
| 72 | #define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ | ||
| 73 | #define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ | ||
| 74 | #define AT91_SMC_TDF_(x) ((x) << 8) | ||
| 75 | #define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ | ||
| 76 | #define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ | ||
| 77 | #define AT91_SMC_DBW_16 (1 << 13) | ||
| 78 | #define AT91_SMC_DBW_8 (2 << 13) | ||
| 79 | #define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */ | ||
| 80 | #define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */ | ||
| 81 | #define AT91_SMC_ACSS_STD (0 << 16) | ||
| 82 | #define AT91_SMC_ACSS_1 (1 << 16) | ||
| 83 | #define AT91_SMC_ACSS_2 (2 << 16) | ||
| 84 | #define AT91_SMC_ACSS_3 (3 << 16) | ||
| 85 | #define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ | ||
| 86 | #define AT91_SMC_RWSETUP_(x) ((x) << 24) | ||
| 87 | #define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ | ||
| 88 | #define AT91_SMC_RWHOLD_(x) ((x) << 28) | ||
| 89 | |||
| 90 | /* SDRAM Controller registers */ | ||
| 91 | #define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */ | ||
| 92 | #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ | ||
| 93 | #define AT91_SDRAMC_MODE_NORMAL (0 << 0) | ||
| 94 | #define AT91_SDRAMC_MODE_NOP (1 << 0) | ||
| 95 | #define AT91_SDRAMC_MODE_PRECHARGE (2 << 0) | ||
| 96 | #define AT91_SDRAMC_MODE_LMR (3 << 0) | ||
| 97 | #define AT91_SDRAMC_MODE_REFRESH (4 << 0) | ||
| 98 | #define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */ | ||
| 99 | #define AT91_SDRAMC_DBW_32 (0 << 4) | ||
| 100 | #define AT91_SDRAMC_DBW_16 (1 << 4) | ||
| 101 | |||
| 102 | #define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */ | ||
| 103 | #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */ | ||
| 104 | |||
| 105 | #define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */ | ||
| 106 | #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ | ||
| 107 | #define AT91_SDRAMC_NC_8 (0 << 0) | ||
| 108 | #define AT91_SDRAMC_NC_9 (1 << 0) | ||
| 109 | #define AT91_SDRAMC_NC_10 (2 << 0) | ||
| 110 | #define AT91_SDRAMC_NC_11 (3 << 0) | ||
| 111 | #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ | ||
| 112 | #define AT91_SDRAMC_NR_11 (0 << 2) | ||
| 113 | #define AT91_SDRAMC_NR_12 (1 << 2) | ||
| 114 | #define AT91_SDRAMC_NR_13 (2 << 2) | ||
| 115 | #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ | ||
| 116 | #define AT91_SDRAMC_NB_2 (0 << 4) | ||
| 117 | #define AT91_SDRAMC_NB_4 (1 << 4) | ||
| 118 | #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ | ||
| 119 | #define AT91_SDRAMC_CAS_2 (2 << 5) | ||
| 120 | #define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */ | ||
| 121 | #define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */ | ||
| 122 | #define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */ | ||
| 123 | #define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */ | ||
| 124 | #define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */ | ||
| 125 | #define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */ | ||
| 126 | |||
| 127 | #define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */ | ||
| 128 | #define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */ | ||
| 129 | #define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */ | ||
| 130 | #define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */ | ||
| 131 | #define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */ | ||
| 132 | #define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */ | ||
| 133 | |||
| 134 | /* Burst Flash Controller register */ | ||
| 135 | #define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */ | ||
| 136 | #define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */ | ||
| 137 | #define AT91_BFC_BFCOM_DISABLED (0 << 0) | ||
| 138 | #define AT91_BFC_BFCOM_ASYNC (1 << 0) | ||
| 139 | #define AT91_BFC_BFCOM_BURST (2 << 0) | ||
| 140 | #define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */ | ||
| 141 | #define AT91_BFC_BFCC_MCK (1 << 2) | ||
| 142 | #define AT91_BFC_BFCC_DIV2 (2 << 2) | ||
| 143 | #define AT91_BFC_BFCC_DIV4 (3 << 2) | ||
| 144 | #define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */ | ||
| 145 | #define AT91_BFC_PAGES (7 << 8) /* Page Size */ | ||
| 146 | #define AT91_BFC_PAGES_NO_PAGE (0 << 8) | ||
| 147 | #define AT91_BFC_PAGES_16 (1 << 8) | ||
| 148 | #define AT91_BFC_PAGES_32 (2 << 8) | ||
| 149 | #define AT91_BFC_PAGES_64 (3 << 8) | ||
| 150 | #define AT91_BFC_PAGES_128 (4 << 8) | ||
| 151 | #define AT91_BFC_PAGES_256 (5 << 8) | ||
| 152 | #define AT91_BFC_PAGES_512 (6 << 8) | ||
| 153 | #define AT91_BFC_PAGES_1024 (7 << 8) | ||
| 154 | #define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */ | ||
| 155 | #define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */ | ||
| 156 | #define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */ | ||
| 157 | #define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */ | ||
| 158 | #define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */ | ||
| 159 | |||
| 160 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h new file mode 100644 index 000000000000..43c396b9b4cb --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9260.h | |||
| @@ -0,0 +1,138 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91sam9260.h | ||
| 3 | * | ||
| 4 | * (C) 2006 Andrew Victor | ||
| 5 | * | ||
| 6 | * Common definitions. | ||
| 7 | * Based on AT91SAM9260 datasheet revision A (Preliminary). | ||
| 8 | * | ||
| 9 | * Includes also definitions for AT91SAM9XE and AT91SAM9G families | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License as published by | ||
| 13 | * the Free Software Foundation; either version 2 of the License, or | ||
| 14 | * (at your option) any later version. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef AT91SAM9260_H | ||
| 18 | #define AT91SAM9260_H | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Peripheral identifiers/interrupts. | ||
| 22 | */ | ||
| 23 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 24 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 25 | #define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 26 | #define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 27 | #define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */ | ||
| 28 | #define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */ | ||
| 29 | #define AT91SAM9260_ID_US0 6 /* USART 0 */ | ||
| 30 | #define AT91SAM9260_ID_US1 7 /* USART 1 */ | ||
| 31 | #define AT91SAM9260_ID_US2 8 /* USART 2 */ | ||
| 32 | #define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */ | ||
| 33 | #define AT91SAM9260_ID_UDP 10 /* USB Device Port */ | ||
| 34 | #define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */ | ||
| 35 | #define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */ | ||
| 36 | #define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */ | ||
| 37 | #define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */ | ||
| 38 | #define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */ | ||
| 39 | #define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */ | ||
| 40 | #define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */ | ||
| 41 | #define AT91SAM9260_ID_UHP 20 /* USB Host port */ | ||
| 42 | #define AT91SAM9260_ID_EMAC 21 /* Ethernet */ | ||
| 43 | #define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */ | ||
| 44 | #define AT91SAM9260_ID_US3 23 /* USART 3 */ | ||
| 45 | #define AT91SAM9260_ID_US4 24 /* USART 4 */ | ||
| 46 | #define AT91SAM9260_ID_US5 25 /* USART 5 */ | ||
| 47 | #define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */ | ||
| 48 | #define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */ | ||
| 49 | #define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */ | ||
| 50 | #define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 51 | #define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 52 | #define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ | ||
| 53 | |||
| 54 | |||
| 55 | /* | ||
| 56 | * User Peripheral physical base addresses. | ||
| 57 | */ | ||
| 58 | #define AT91SAM9260_BASE_TCB0 0xfffa0000 | ||
| 59 | #define AT91SAM9260_BASE_TC0 0xfffa0000 | ||
| 60 | #define AT91SAM9260_BASE_TC1 0xfffa0040 | ||
| 61 | #define AT91SAM9260_BASE_TC2 0xfffa0080 | ||
| 62 | #define AT91SAM9260_BASE_UDP 0xfffa4000 | ||
| 63 | #define AT91SAM9260_BASE_MCI 0xfffa8000 | ||
| 64 | #define AT91SAM9260_BASE_TWI 0xfffac000 | ||
| 65 | #define AT91SAM9260_BASE_US0 0xfffb0000 | ||
| 66 | #define AT91SAM9260_BASE_US1 0xfffb4000 | ||
| 67 | #define AT91SAM9260_BASE_US2 0xfffb8000 | ||
| 68 | #define AT91SAM9260_BASE_SSC 0xfffbc000 | ||
| 69 | #define AT91SAM9260_BASE_ISI 0xfffc0000 | ||
| 70 | #define AT91SAM9260_BASE_EMAC 0xfffc4000 | ||
| 71 | #define AT91SAM9260_BASE_SPI0 0xfffc8000 | ||
| 72 | #define AT91SAM9260_BASE_SPI1 0xfffcc000 | ||
| 73 | #define AT91SAM9260_BASE_US3 0xfffd0000 | ||
| 74 | #define AT91SAM9260_BASE_US4 0xfffd4000 | ||
| 75 | #define AT91SAM9260_BASE_US5 0xfffd8000 | ||
| 76 | #define AT91SAM9260_BASE_TCB1 0xfffdc000 | ||
| 77 | #define AT91SAM9260_BASE_TC3 0xfffdc000 | ||
| 78 | #define AT91SAM9260_BASE_TC4 0xfffdc040 | ||
| 79 | #define AT91SAM9260_BASE_TC5 0xfffdc080 | ||
| 80 | #define AT91SAM9260_BASE_ADC 0xfffe0000 | ||
| 81 | #define AT91_BASE_SYS 0xffffe800 | ||
| 82 | |||
| 83 | /* | ||
| 84 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 85 | */ | ||
| 86 | #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) | ||
| 87 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) | ||
| 88 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) | ||
| 89 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | ||
| 90 | #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) | ||
| 91 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 92 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) | ||
| 93 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) | ||
| 94 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) | ||
| 95 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) | ||
| 96 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 97 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 98 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 99 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
| 100 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 101 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 102 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | ||
| 103 | |||
| 104 | #define AT91_USART0 AT91SAM9260_BASE_US0 | ||
| 105 | #define AT91_USART1 AT91SAM9260_BASE_US1 | ||
| 106 | #define AT91_USART2 AT91SAM9260_BASE_US2 | ||
| 107 | #define AT91_USART3 AT91SAM9260_BASE_US3 | ||
| 108 | #define AT91_USART4 AT91SAM9260_BASE_US4 | ||
| 109 | #define AT91_USART5 AT91SAM9260_BASE_US5 | ||
| 110 | |||
| 111 | |||
| 112 | /* | ||
| 113 | * Internal Memory. | ||
| 114 | */ | ||
| 115 | #define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */ | ||
| 116 | #define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ | ||
| 117 | |||
| 118 | #define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ | ||
| 119 | #define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */ | ||
| 120 | #define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ | ||
| 121 | #define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */ | ||
| 122 | |||
| 123 | #define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */ | ||
| 124 | |||
| 125 | #define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ | ||
| 126 | #define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | ||
| 127 | |||
| 128 | #define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */ | ||
| 129 | #define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ | ||
| 130 | |||
| 131 | #define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */ | ||
| 132 | #define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */ | ||
| 133 | #define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */ | ||
| 134 | #define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ | ||
| 135 | |||
| 136 | #define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */ | ||
| 137 | |||
| 138 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h new file mode 100644 index 000000000000..f027de5df956 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h | |||
| @@ -0,0 +1,78 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91sam9260_matrix.h | ||
| 3 | * | ||
| 4 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9260 datasheet revision B. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM9260_MATRIX_H | ||
| 14 | #define AT91SAM9260_MATRIX_H | ||
| 15 | |||
| 16 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
| 17 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
| 18 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
| 19 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
| 20 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
| 21 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ | ||
| 22 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
| 23 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
| 24 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
| 25 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
| 26 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
| 27 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
| 28 | |||
| 29 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
| 30 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
| 31 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
| 32 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
| 33 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
| 34 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 35 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 36 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 37 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 38 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 39 | #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ | ||
| 40 | #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ | ||
| 41 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | ||
| 42 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | ||
| 43 | |||
| 44 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
| 45 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
| 46 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
| 47 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
| 48 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
| 49 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
| 50 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
| 51 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
| 52 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
| 53 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
| 54 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
| 55 | |||
| 56 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
| 57 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 58 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 59 | |||
| 60 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */ | ||
| 61 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 62 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | ||
| 63 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | ||
| 64 | #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 65 | #define AT91_MATRIX_CS3A_SMC (0 << 3) | ||
| 66 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 67 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 68 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | ||
| 69 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | ||
| 70 | #define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
| 71 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | ||
| 72 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | ||
| 73 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 74 | #define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 75 | #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) | ||
| 76 | #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) | ||
| 77 | |||
| 78 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h new file mode 100644 index 000000000000..3a348ca20773 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h | |||
| @@ -0,0 +1,105 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91sam9261.h | ||
| 3 | * | ||
| 4 | * Copyright (C) SAN People | ||
| 5 | * | ||
| 6 | * Common definitions. | ||
| 7 | * Based on AT91SAM9261 datasheet revision E. (Preliminary) | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91SAM9261_H | ||
| 16 | #define AT91SAM9261_H | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Peripheral identifiers/interrupts. | ||
| 20 | */ | ||
| 21 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 22 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 23 | #define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 24 | #define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 25 | #define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ | ||
| 26 | #define AT91SAM9261_ID_US0 6 /* USART 0 */ | ||
| 27 | #define AT91SAM9261_ID_US1 7 /* USART 1 */ | ||
| 28 | #define AT91SAM9261_ID_US2 8 /* USART 2 */ | ||
| 29 | #define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ | ||
| 30 | #define AT91SAM9261_ID_UDP 10 /* USB Device Port */ | ||
| 31 | #define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ | ||
| 32 | #define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ | ||
| 33 | #define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ | ||
| 34 | #define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ | ||
| 35 | #define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ | ||
| 36 | #define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ | ||
| 37 | #define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ | ||
| 38 | #define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ | ||
| 39 | #define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ | ||
| 40 | #define AT91SAM9261_ID_UHP 20 /* USB Host port */ | ||
| 41 | #define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ | ||
| 42 | #define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 43 | #define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 44 | #define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ | ||
| 45 | |||
| 46 | |||
| 47 | /* | ||
| 48 | * User Peripheral physical base addresses. | ||
| 49 | */ | ||
| 50 | #define AT91SAM9261_BASE_TCB0 0xfffa0000 | ||
| 51 | #define AT91SAM9261_BASE_TC0 0xfffa0000 | ||
| 52 | #define AT91SAM9261_BASE_TC1 0xfffa0040 | ||
| 53 | #define AT91SAM9261_BASE_TC2 0xfffa0080 | ||
| 54 | #define AT91SAM9261_BASE_UDP 0xfffa4000 | ||
| 55 | #define AT91SAM9261_BASE_MCI 0xfffa8000 | ||
| 56 | #define AT91SAM9261_BASE_TWI 0xfffac000 | ||
| 57 | #define AT91SAM9261_BASE_US0 0xfffb0000 | ||
| 58 | #define AT91SAM9261_BASE_US1 0xfffb4000 | ||
| 59 | #define AT91SAM9261_BASE_US2 0xfffb8000 | ||
| 60 | #define AT91SAM9261_BASE_SSC0 0xfffbc000 | ||
| 61 | #define AT91SAM9261_BASE_SSC1 0xfffc0000 | ||
| 62 | #define AT91SAM9261_BASE_SSC2 0xfffc4000 | ||
| 63 | #define AT91SAM9261_BASE_SPI0 0xfffc8000 | ||
| 64 | #define AT91SAM9261_BASE_SPI1 0xfffcc000 | ||
| 65 | #define AT91_BASE_SYS 0xffffea00 | ||
| 66 | |||
| 67 | |||
| 68 | /* | ||
| 69 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 70 | */ | ||
| 71 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) | ||
| 72 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) | ||
| 73 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | ||
| 74 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 75 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) | ||
| 76 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) | ||
| 77 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) | ||
| 78 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) | ||
| 79 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 80 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 81 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 82 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
| 83 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 84 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 85 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) | ||
| 86 | |||
| 87 | #define AT91_USART0 AT91SAM9261_BASE_US0 | ||
| 88 | #define AT91_USART1 AT91SAM9261_BASE_US1 | ||
| 89 | #define AT91_USART2 AT91SAM9261_BASE_US2 | ||
| 90 | |||
| 91 | |||
| 92 | /* | ||
| 93 | * Internal Memory. | ||
| 94 | */ | ||
| 95 | #define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | ||
| 96 | #define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ | ||
| 97 | |||
| 98 | #define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ | ||
| 99 | #define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ | ||
| 100 | |||
| 101 | #define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ | ||
| 102 | #define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ | ||
| 103 | |||
| 104 | |||
| 105 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h new file mode 100644 index 000000000000..db62b1f18300 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91sam9261_matrix.h | ||
| 3 | * | ||
| 4 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM9261_MATRIX_H | ||
| 14 | #define AT91SAM9261_MATRIX_H | ||
| 15 | |||
| 16 | #define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ | ||
| 17 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 18 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 19 | |||
| 20 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ | ||
| 21 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ | ||
| 22 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ | ||
| 23 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ | ||
| 24 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ | ||
| 25 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 26 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 27 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 28 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 29 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 30 | #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ | ||
| 31 | |||
| 32 | #define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ | ||
| 33 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | ||
| 34 | #define AT91_MATRIX_ITCM_0 (0 << 0) | ||
| 35 | #define AT91_MATRIX_ITCM_16 (5 << 0) | ||
| 36 | #define AT91_MATRIX_ITCM_32 (6 << 0) | ||
| 37 | #define AT91_MATRIX_ITCM_64 (7 << 0) | ||
| 38 | #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ | ||
| 39 | #define AT91_MATRIX_DTCM_0 (0 << 4) | ||
| 40 | #define AT91_MATRIX_DTCM_16 (5 << 4) | ||
| 41 | #define AT91_MATRIX_DTCM_32 (6 << 4) | ||
| 42 | #define AT91_MATRIX_DTCM_64 (7 << 4) | ||
| 43 | |||
| 44 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ | ||
| 45 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 46 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | ||
| 47 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | ||
| 48 | #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 49 | #define AT91_MATRIX_CS3A_SMC (0 << 3) | ||
| 50 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 51 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 52 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | ||
| 53 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | ||
| 54 | #define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
| 55 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | ||
| 56 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | ||
| 57 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 58 | |||
| 59 | #define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ | ||
| 60 | #define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ | ||
| 61 | |||
| 62 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h new file mode 100644 index 000000000000..2091f1e42d43 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9263.h | |||
| @@ -0,0 +1,127 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91sam9263.h | ||
| 3 | * | ||
| 4 | * (C) 2007 Atmel Corporation. | ||
| 5 | * | ||
| 6 | * Common definitions. | ||
| 7 | * Based on AT91SAM9263 datasheet revision B (Preliminary). | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91SAM9263_H | ||
| 16 | #define AT91SAM9263_H | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Peripheral identifiers/interrupts. | ||
| 20 | */ | ||
| 21 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 22 | #define AT91_ID_SYS 1 /* System Peripherals */ | ||
| 23 | #define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 24 | #define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 25 | #define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */ | ||
| 26 | #define AT91SAM9263_ID_US0 7 /* USART 0 */ | ||
| 27 | #define AT91SAM9263_ID_US1 8 /* USART 1 */ | ||
| 28 | #define AT91SAM9263_ID_US2 9 /* USART 2 */ | ||
| 29 | #define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */ | ||
| 30 | #define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */ | ||
| 31 | #define AT91SAM9263_ID_CAN 12 /* CAN */ | ||
| 32 | #define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */ | ||
| 33 | #define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */ | ||
| 34 | #define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */ | ||
| 35 | #define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */ | ||
| 36 | #define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */ | ||
| 37 | #define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */ | ||
| 38 | #define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */ | ||
| 39 | #define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */ | ||
| 40 | #define AT91SAM9263_ID_EMAC 21 /* Ethernet */ | ||
| 41 | #define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */ | ||
| 42 | #define AT91SAM9263_ID_UDP 24 /* USB Device Port */ | ||
| 43 | #define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */ | ||
| 44 | #define AT91SAM9263_ID_LCDC 26 /* LCD Controller */ | ||
| 45 | #define AT91SAM9263_ID_DMA 27 /* DMA Controller */ | ||
| 46 | #define AT91SAM9263_ID_UHP 29 /* USB Host port */ | ||
| 47 | #define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 48 | #define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ | ||
| 49 | |||
| 50 | |||
| 51 | /* | ||
| 52 | * User Peripheral physical base addresses. | ||
| 53 | */ | ||
| 54 | #define AT91SAM9263_BASE_UDP 0xfff78000 | ||
| 55 | #define AT91SAM9263_BASE_TCB0 0xfff7c000 | ||
| 56 | #define AT91SAM9263_BASE_TC0 0xfff7c000 | ||
| 57 | #define AT91SAM9263_BASE_TC1 0xfff7c040 | ||
| 58 | #define AT91SAM9263_BASE_TC2 0xfff7c080 | ||
| 59 | #define AT91SAM9263_BASE_MCI0 0xfff80000 | ||
| 60 | #define AT91SAM9263_BASE_MCI1 0xfff84000 | ||
| 61 | #define AT91SAM9263_BASE_TWI 0xfff88000 | ||
| 62 | #define AT91SAM9263_BASE_US0 0xfff8c000 | ||
| 63 | #define AT91SAM9263_BASE_US1 0xfff90000 | ||
| 64 | #define AT91SAM9263_BASE_US2 0xfff94000 | ||
| 65 | #define AT91SAM9263_BASE_SSC0 0xfff98000 | ||
| 66 | #define AT91SAM9263_BASE_SSC1 0xfff9c000 | ||
| 67 | #define AT91SAM9263_BASE_AC97C 0xfffa0000 | ||
| 68 | #define AT91SAM9263_BASE_SPI0 0xfffa4000 | ||
| 69 | #define AT91SAM9263_BASE_SPI1 0xfffa8000 | ||
| 70 | #define AT91SAM9263_BASE_CAN 0xfffac000 | ||
| 71 | #define AT91SAM9263_BASE_PWMC 0xfffb8000 | ||
| 72 | #define AT91SAM9263_BASE_EMAC 0xfffbc000 | ||
| 73 | #define AT91SAM9263_BASE_ISI 0xfffc4000 | ||
| 74 | #define AT91SAM9263_BASE_2DGE 0xfffc8000 | ||
| 75 | #define AT91_BASE_SYS 0xffffe000 | ||
| 76 | |||
| 77 | /* | ||
| 78 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 79 | */ | ||
| 80 | #define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS) | ||
| 81 | #define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS) | ||
| 82 | #define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS) | ||
| 83 | #define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS) | ||
| 84 | #define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS) | ||
| 85 | #define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS) | ||
| 86 | #define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS) | ||
| 87 | #define AT91_CCFG (0xffffed10 - AT91_BASE_SYS) | ||
| 88 | #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) | ||
| 89 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 90 | #define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) | ||
| 91 | #define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) | ||
| 92 | #define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) | ||
| 93 | #define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) | ||
| 94 | #define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) | ||
| 95 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 96 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 97 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 98 | #define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS) | ||
| 99 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 100 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 101 | #define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS) | ||
| 102 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | ||
| 103 | |||
| 104 | #define AT91_USART0 AT91SAM9263_BASE_US0 | ||
| 105 | #define AT91_USART1 AT91SAM9263_BASE_US1 | ||
| 106 | #define AT91_USART2 AT91SAM9263_BASE_US2 | ||
| 107 | |||
| 108 | #define AT91_SMC AT91_SMC0 | ||
| 109 | |||
| 110 | /* | ||
| 111 | * Internal Memory. | ||
| 112 | */ | ||
| 113 | #define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */ | ||
| 114 | #define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */ | ||
| 115 | |||
| 116 | #define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */ | ||
| 117 | #define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ | ||
| 118 | |||
| 119 | #define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */ | ||
| 120 | #define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */ | ||
| 121 | |||
| 122 | #define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */ | ||
| 123 | #define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ | ||
| 124 | #define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ | ||
| 125 | |||
| 126 | |||
| 127 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h new file mode 100644 index 000000000000..9b3efd3eb2f3 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h | |||
| @@ -0,0 +1,129 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91sam9263_matrix.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Atmel Corporation. | ||
| 5 | * | ||
| 6 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 7 | * Based on AT91SAM9263 datasheet revision B (Preliminary). | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91SAM9263_MATRIX_H | ||
| 16 | #define AT91SAM9263_MATRIX_H | ||
| 17 | |||
| 18 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
| 19 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
| 20 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
| 21 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
| 22 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
| 23 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ | ||
| 24 | #define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ | ||
| 25 | #define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ | ||
| 26 | #define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ | ||
| 27 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
| 28 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
| 29 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
| 30 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
| 31 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
| 32 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
| 33 | |||
| 34 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
| 35 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
| 36 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
| 37 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
| 38 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
| 39 | #define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ | ||
| 40 | #define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ | ||
| 41 | #define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ | ||
| 42 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 43 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 44 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 45 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 46 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 47 | #define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ | ||
| 48 | #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ | ||
| 49 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | ||
| 50 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | ||
| 51 | |||
| 52 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
| 53 | #define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ | ||
| 54 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
| 55 | #define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ | ||
| 56 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
| 57 | #define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ | ||
| 58 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
| 59 | #define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ | ||
| 60 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
| 61 | #define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ | ||
| 62 | #define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ | ||
| 63 | #define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ | ||
| 64 | #define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ | ||
| 65 | #define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ | ||
| 66 | #define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ | ||
| 67 | #define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ | ||
| 68 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
| 69 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
| 70 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
| 71 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
| 72 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
| 73 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
| 74 | #define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ | ||
| 75 | #define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ | ||
| 76 | #define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ | ||
| 77 | |||
| 78 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
| 79 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 80 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 81 | #define AT91_MATRIX_RCB2 (1 << 2) | ||
| 82 | #define AT91_MATRIX_RCB3 (1 << 3) | ||
| 83 | #define AT91_MATRIX_RCB4 (1 << 4) | ||
| 84 | #define AT91_MATRIX_RCB5 (1 << 5) | ||
| 85 | #define AT91_MATRIX_RCB6 (1 << 6) | ||
| 86 | #define AT91_MATRIX_RCB7 (1 << 7) | ||
| 87 | #define AT91_MATRIX_RCB8 (1 << 8) | ||
| 88 | |||
| 89 | #define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ | ||
| 90 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | ||
| 91 | #define AT91_MATRIX_ITCM_0 (0 << 0) | ||
| 92 | #define AT91_MATRIX_ITCM_16 (5 << 0) | ||
| 93 | #define AT91_MATRIX_ITCM_32 (6 << 0) | ||
| 94 | #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ | ||
| 95 | #define AT91_MATRIX_DTCM_0 (0 << 4) | ||
| 96 | #define AT91_MATRIX_DTCM_16 (5 << 4) | ||
| 97 | #define AT91_MATRIX_DTCM_32 (6 << 4) | ||
| 98 | |||
| 99 | #define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ | ||
| 100 | #define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 101 | #define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1) | ||
| 102 | #define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1) | ||
| 103 | #define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 104 | #define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3) | ||
| 105 | #define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 106 | #define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 107 | #define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4) | ||
| 108 | #define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4) | ||
| 109 | #define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
| 110 | #define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5) | ||
| 111 | #define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5) | ||
| 112 | #define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 113 | #define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 114 | #define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16) | ||
| 115 | #define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16) | ||
| 116 | |||
| 117 | #define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */ | ||
| 118 | #define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 119 | #define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1) | ||
| 120 | #define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1) | ||
| 121 | #define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 122 | #define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3) | ||
| 123 | #define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3) | ||
| 124 | #define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 125 | #define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 126 | #define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16) | ||
| 127 | #define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16) | ||
| 128 | |||
| 129 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h new file mode 100644 index 000000000000..1921181c63ca --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h | |||
| @@ -0,0 +1,83 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91sam9_sdramc.h | ||
| 3 | * | ||
| 4 | * SDRAM Controllers (SDRAMC) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM9_SDRAMC_H | ||
| 14 | #define AT91SAM9_SDRAMC_H | ||
| 15 | |||
| 16 | /* SDRAM Controller (SDRAMC) registers */ | ||
| 17 | #define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */ | ||
| 18 | #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */ | ||
| 19 | #define AT91_SDRAMC_MODE_NORMAL 0 | ||
| 20 | #define AT91_SDRAMC_MODE_NOP 1 | ||
| 21 | #define AT91_SDRAMC_MODE_PRECHARGE 2 | ||
| 22 | #define AT91_SDRAMC_MODE_LMR 3 | ||
| 23 | #define AT91_SDRAMC_MODE_REFRESH 4 | ||
| 24 | #define AT91_SDRAMC_MODE_EXT_LMR 5 | ||
| 25 | #define AT91_SDRAMC_MODE_DEEP 6 | ||
| 26 | |||
| 27 | #define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */ | ||
| 28 | #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */ | ||
| 29 | |||
| 30 | #define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */ | ||
| 31 | #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */ | ||
| 32 | #define AT91_SDRAMC_NC_8 (0 << 0) | ||
| 33 | #define AT91_SDRAMC_NC_9 (1 << 0) | ||
| 34 | #define AT91_SDRAMC_NC_10 (2 << 0) | ||
| 35 | #define AT91_SDRAMC_NC_11 (3 << 0) | ||
| 36 | #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ | ||
| 37 | #define AT91_SDRAMC_NR_11 (0 << 2) | ||
| 38 | #define AT91_SDRAMC_NR_12 (1 << 2) | ||
| 39 | #define AT91_SDRAMC_NR_13 (2 << 2) | ||
| 40 | #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ | ||
| 41 | #define AT91_SDRAMC_NB_2 (0 << 4) | ||
| 42 | #define AT91_SDRAMC_NB_4 (1 << 4) | ||
| 43 | #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ | ||
| 44 | #define AT91_SDRAMC_CAS_1 (1 << 5) | ||
| 45 | #define AT91_SDRAMC_CAS_2 (2 << 5) | ||
| 46 | #define AT91_SDRAMC_CAS_3 (3 << 5) | ||
| 47 | #define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */ | ||
| 48 | #define AT91_SDRAMC_DBW_32 (0 << 7) | ||
| 49 | #define AT91_SDRAMC_DBW_16 (1 << 7) | ||
| 50 | #define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */ | ||
| 51 | #define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */ | ||
| 52 | #define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */ | ||
| 53 | #define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */ | ||
| 54 | #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */ | ||
| 55 | #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */ | ||
| 56 | |||
| 57 | #define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */ | ||
| 58 | #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */ | ||
| 59 | #define AT91_SDRAMC_LPCB_DISABLE 0 | ||
| 60 | #define AT91_SDRAMC_LPCB_SELF_REFRESH 1 | ||
| 61 | #define AT91_SDRAMC_LPCB_POWER_DOWN 2 | ||
| 62 | #define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3 | ||
| 63 | #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */ | ||
| 64 | #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ | ||
| 65 | #define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */ | ||
| 66 | #define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ | ||
| 67 | #define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12) | ||
| 68 | #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12) | ||
| 69 | #define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12) | ||
| 70 | |||
| 71 | #define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */ | ||
| 72 | #define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */ | ||
| 73 | #define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */ | ||
| 74 | #define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */ | ||
| 75 | #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */ | ||
| 76 | |||
| 77 | #define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */ | ||
| 78 | #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */ | ||
| 79 | #define AT91_SDRAMC_MD_SDRAM 0 | ||
| 80 | #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1 | ||
| 81 | |||
| 82 | |||
| 83 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h new file mode 100644 index 000000000000..ec6ad1338b5a --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h | |||
| @@ -0,0 +1,73 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91sam9_smc.h | ||
| 3 | * | ||
| 4 | * Static Memory Controllers (SMC) - System peripherals registers. | ||
| 5 | * Based on AT91SAM9261 datasheet revision D. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef AT91SAM9_SMC_H | ||
| 14 | #define AT91SAM9_SMC_H | ||
| 15 | |||
| 16 | #define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | ||
| 17 | #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ | ||
| 18 | #define AT91_SMC_NWESETUP_(x) ((x) << 0) | ||
| 19 | #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ | ||
| 20 | #define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) | ||
| 21 | #define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ | ||
| 22 | #define AT91_SMC_NRDSETUP_(x) ((x) << 16) | ||
| 23 | #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ | ||
| 24 | #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) | ||
| 25 | |||
| 26 | #define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | ||
| 27 | #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ | ||
| 28 | #define AT91_SMC_NWEPULSE_(x) ((x) << 0) | ||
| 29 | #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ | ||
| 30 | #define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) | ||
| 31 | #define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ | ||
| 32 | #define AT91_SMC_NRDPULSE_(x) ((x) << 16) | ||
| 33 | #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ | ||
| 34 | #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) | ||
| 35 | |||
| 36 | #define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | ||
| 37 | #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ | ||
| 38 | #define AT91_SMC_NWECYCLE_(x) ((x) << 0) | ||
| 39 | #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ | ||
| 40 | #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) | ||
| 41 | |||
| 42 | #define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | ||
| 43 | #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ | ||
| 44 | #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ | ||
| 45 | #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ | ||
| 46 | #define AT91_SMC_EXNWMODE_DISABLE (0 << 4) | ||
| 47 | #define AT91_SMC_EXNWMODE_FROZEN (2 << 4) | ||
| 48 | #define AT91_SMC_EXNWMODE_READY (3 << 4) | ||
| 49 | #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ | ||
| 50 | #define AT91_SMC_BAT_SELECT (0 << 8) | ||
| 51 | #define AT91_SMC_BAT_WRITE (1 << 8) | ||
| 52 | #define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ | ||
| 53 | #define AT91_SMC_DBW_8 (0 << 12) | ||
| 54 | #define AT91_SMC_DBW_16 (1 << 12) | ||
| 55 | #define AT91_SMC_DBW_32 (2 << 12) | ||
| 56 | #define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ | ||
| 57 | #define AT91_SMC_TDF_(x) ((x) << 16) | ||
| 58 | #define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ | ||
| 59 | #define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ | ||
| 60 | #define AT91_SMC_PS (3 << 28) /* Page Size */ | ||
| 61 | #define AT91_SMC_PS_4 (0 << 28) | ||
| 62 | #define AT91_SMC_PS_8 (1 << 28) | ||
| 63 | #define AT91_SMC_PS_16 (2 << 28) | ||
| 64 | #define AT91_SMC_PS_32 (3 << 28) | ||
| 65 | |||
| 66 | #if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ | ||
| 67 | #define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | ||
| 68 | #define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | ||
| 69 | #define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | ||
| 70 | #define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | ||
| 71 | #endif | ||
| 72 | |||
| 73 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h new file mode 100644 index 000000000000..fc2de6c09c86 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h | |||
| @@ -0,0 +1,115 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91sam9260.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 Atmel Corporation | ||
| 5 | * | ||
| 6 | * Common definitions. | ||
| 7 | * Based on AT91SAM9RL datasheet revision A. (Preliminary) | ||
| 8 | * | ||
| 9 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 10 | * License. See the file COPYING in the main directory of this archive for | ||
| 11 | * more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef AT91SAM9RL_H | ||
| 15 | #define AT91SAM9RL_H | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Peripheral identifiers/interrupts. | ||
| 19 | */ | ||
| 20 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 21 | #define AT91_ID_SYS 1 /* System Controller */ | ||
| 22 | #define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ | ||
| 23 | #define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ | ||
| 24 | #define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ | ||
| 25 | #define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ | ||
| 26 | #define AT91SAM9RL_ID_US0 6 /* USART 0 */ | ||
| 27 | #define AT91SAM9RL_ID_US1 7 /* USART 1 */ | ||
| 28 | #define AT91SAM9RL_ID_US2 8 /* USART 2 */ | ||
| 29 | #define AT91SAM9RL_ID_US3 9 /* USART 3 */ | ||
| 30 | #define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ | ||
| 31 | #define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ | ||
| 32 | #define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ | ||
| 33 | #define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ | ||
| 34 | #define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ | ||
| 35 | #define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ | ||
| 36 | #define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ | ||
| 37 | #define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ | ||
| 38 | #define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ | ||
| 39 | #define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ | ||
| 40 | #define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ | ||
| 41 | #define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ | ||
| 42 | #define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ | ||
| 43 | #define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ | ||
| 44 | #define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ | ||
| 45 | #define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ | ||
| 46 | |||
| 47 | |||
| 48 | /* | ||
| 49 | * User Peripheral physical base addresses. | ||
| 50 | */ | ||
| 51 | #define AT91SAM9RL_BASE_TCB0 0xfffa0000 | ||
| 52 | #define AT91SAM9RL_BASE_TC0 0xfffa0000 | ||
| 53 | #define AT91SAM9RL_BASE_TC1 0xfffa0040 | ||
| 54 | #define AT91SAM9RL_BASE_TC2 0xfffa0080 | ||
| 55 | #define AT91SAM9RL_BASE_MCI 0xfffa4000 | ||
| 56 | #define AT91SAM9RL_BASE_TWI0 0xfffa8000 | ||
| 57 | #define AT91SAM9RL_BASE_TWI1 0xfffac000 | ||
| 58 | #define AT91SAM9RL_BASE_US0 0xfffb0000 | ||
| 59 | #define AT91SAM9RL_BASE_US1 0xfffb4000 | ||
| 60 | #define AT91SAM9RL_BASE_US2 0xfffb8000 | ||
| 61 | #define AT91SAM9RL_BASE_US3 0xfffbc000 | ||
| 62 | #define AT91SAM9RL_BASE_SSC0 0xfffc0000 | ||
| 63 | #define AT91SAM9RL_BASE_SSC1 0xfffc4000 | ||
| 64 | #define AT91SAM9RL_BASE_PWMC 0xfffc8000 | ||
| 65 | #define AT91SAM9RL_BASE_SPI 0xfffcc000 | ||
| 66 | #define AT91SAM9RL_BASE_TSC 0xfffd0000 | ||
| 67 | #define AT91SAM9RL_BASE_UDPHS 0xfffd4000 | ||
| 68 | #define AT91SAM9RL_BASE_AC97C 0xfffd8000 | ||
| 69 | #define AT91_BASE_SYS 0xffffc000 | ||
| 70 | |||
| 71 | |||
| 72 | /* | ||
| 73 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 74 | */ | ||
| 75 | #define AT91_DMA (0xffffe600 - AT91_BASE_SYS) | ||
| 76 | #define AT91_ECC (0xffffe800 - AT91_BASE_SYS) | ||
| 77 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) | ||
| 78 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) | ||
| 79 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) | ||
| 80 | #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) | ||
| 81 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 82 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) | ||
| 83 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) | ||
| 84 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) | ||
| 85 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) | ||
| 86 | #define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) | ||
| 87 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 88 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 89 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 90 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
| 91 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 92 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 93 | #define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) | ||
| 94 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | ||
| 95 | #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) | ||
| 96 | |||
| 97 | #define AT91_USART0 AT91SAM9RL_BASE_US0 | ||
| 98 | #define AT91_USART1 AT91SAM9RL_BASE_US1 | ||
| 99 | #define AT91_USART2 AT91SAM9RL_BASE_US2 | ||
| 100 | #define AT91_USART3 AT91SAM9RL_BASE_US3 | ||
| 101 | |||
| 102 | |||
| 103 | /* | ||
| 104 | * Internal Memory. | ||
| 105 | */ | ||
| 106 | #define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | ||
| 107 | #define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ | ||
| 108 | |||
| 109 | #define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ | ||
| 110 | #define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ | ||
| 111 | |||
| 112 | #define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ | ||
| 113 | #define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ | ||
| 114 | |||
| 115 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h new file mode 100644 index 000000000000..5f9149071fe5 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h | |||
| @@ -0,0 +1,96 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91sam9rl_matrix.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 Atmel Corporation | ||
| 5 | * | ||
| 6 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 7 | * Based on AT91SAM9RL datasheet revision A. (Preliminary) | ||
| 8 | * | ||
| 9 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 10 | * License. See the file COPYING in the main directory of this archive for | ||
| 11 | * more details. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef AT91SAM9RL_MATRIX_H | ||
| 15 | #define AT91SAM9RL_MATRIX_H | ||
| 16 | |||
| 17 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
| 18 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
| 19 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
| 20 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
| 21 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
| 22 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ | ||
| 23 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
| 24 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
| 25 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
| 26 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
| 27 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
| 28 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
| 29 | |||
| 30 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
| 31 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
| 32 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
| 33 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
| 34 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
| 35 | #define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ | ||
| 36 | #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 37 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 38 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 39 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 40 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 41 | #define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ | ||
| 42 | #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ | ||
| 43 | #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) | ||
| 44 | #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) | ||
| 45 | |||
| 46 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
| 47 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
| 48 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
| 49 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
| 50 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
| 51 | #define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ | ||
| 52 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
| 53 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
| 54 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
| 55 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
| 56 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
| 57 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
| 58 | |||
| 59 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
| 60 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 61 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 62 | #define AT91_MATRIX_RCB2 (1 << 2) | ||
| 63 | #define AT91_MATRIX_RCB3 (1 << 3) | ||
| 64 | #define AT91_MATRIX_RCB4 (1 << 4) | ||
| 65 | #define AT91_MATRIX_RCB5 (1 << 5) | ||
| 66 | |||
| 67 | #define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ | ||
| 68 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | ||
| 69 | #define AT91_MATRIX_ITCM_0 (0 << 0) | ||
| 70 | #define AT91_MATRIX_ITCM_16 (5 << 0) | ||
| 71 | #define AT91_MATRIX_ITCM_32 (6 << 0) | ||
| 72 | #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ | ||
| 73 | #define AT91_MATRIX_DTCM_0 (0 << 4) | ||
| 74 | #define AT91_MATRIX_DTCM_16 (5 << 4) | ||
| 75 | #define AT91_MATRIX_DTCM_32 (6 << 4) | ||
| 76 | |||
| 77 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ | ||
| 78 | #define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 79 | #define AT91_MATRIX_CS1A_SMC (0 << 1) | ||
| 80 | #define AT91_MATRIX_CS1A_SDRAMC (1 << 1) | ||
| 81 | #define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 82 | #define AT91_MATRIX_CS3A_SMC (0 << 3) | ||
| 83 | #define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 84 | #define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 85 | #define AT91_MATRIX_CS4A_SMC (0 << 4) | ||
| 86 | #define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) | ||
| 87 | #define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
| 88 | #define AT91_MATRIX_CS5A_SMC (0 << 5) | ||
| 89 | #define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) | ||
| 90 | #define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 91 | #define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 92 | #define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) | ||
| 93 | #define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) | ||
| 94 | |||
| 95 | |||
| 96 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h new file mode 100644 index 000000000000..d34cdb8abdca --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91x40.h | |||
| @@ -0,0 +1,55 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/at91x40.h | ||
| 3 | * | ||
| 4 | * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef AT91X40_H | ||
| 13 | #define AT91X40_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * IRQ list. | ||
| 17 | */ | ||
| 18 | #define AT91_ID_FIQ 0 /* FIQ */ | ||
| 19 | #define AT91_ID_SYS 1 /* System Peripheral */ | ||
| 20 | #define AT91X40_ID_USART0 2 /* USART port 0 */ | ||
| 21 | #define AT91X40_ID_USART1 3 /* USART port 1 */ | ||
| 22 | #define AT91X40_ID_TC0 4 /* Timer/Counter 0 */ | ||
| 23 | #define AT91X40_ID_TC1 5 /* Timer/Counter 1*/ | ||
| 24 | #define AT91X40_ID_TC2 6 /* Timer/Counter 2*/ | ||
| 25 | #define AT91X40_ID_WD 7 /* Watchdog? */ | ||
| 26 | #define AT91X40_ID_PIOA 8 /* Parallel IO Controller A */ | ||
| 27 | |||
| 28 | #define AT91X40_ID_IRQ0 16 /* External IRQ 0 */ | ||
| 29 | #define AT91X40_ID_IRQ1 17 /* External IRQ 1 */ | ||
| 30 | #define AT91X40_ID_IRQ2 18 /* External IRQ 2 */ | ||
| 31 | |||
| 32 | /* | ||
| 33 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 34 | */ | ||
| 35 | #define AT91_BASE_SYS 0xffc00000 | ||
| 36 | |||
| 37 | #define AT91_EBI (0xffe00000 - AT91_BASE_SYS) /* External Bus Interface */ | ||
| 38 | #define AT91_SF (0xfff00000 - AT91_BASE_SYS) /* Special Function */ | ||
| 39 | #define AT91_USART1 (0xfffcc000 - AT91_BASE_SYS) /* USART 1 */ | ||
| 40 | #define AT91_USART0 (0xfffd0000 - AT91_BASE_SYS) /* USART 0 */ | ||
| 41 | #define AT91_TC (0xfffe0000 - AT91_BASE_SYS) /* Timer Counter */ | ||
| 42 | #define AT91_PIOA (0xffff0000 - AT91_BASE_SYS) /* PIO Controller A */ | ||
| 43 | #define AT91_PS (0xffff4000 - AT91_BASE_SYS) /* Power Save */ | ||
| 44 | #define AT91_WD (0xffff8000 - AT91_BASE_SYS) /* Watchdog Timer */ | ||
| 45 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ | ||
| 46 | |||
| 47 | /* | ||
| 48 | * The AT91x40 series doesn't have a debug unit like the other AT91 parts. | ||
| 49 | * But it does have a chip identify register and extension ID, so define at | ||
| 50 | * least these here. | ||
| 51 | */ | ||
| 52 | #define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */ | ||
| 53 | #define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */ | ||
| 54 | |||
| 55 | #endif /* AT91X40_H */ | ||
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h new file mode 100644 index 000000000000..acd60f2a0724 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/board.h | |||
| @@ -0,0 +1,172 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/board.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 HP Labs | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | /* | ||
| 22 | * These are data structures found in platform_device.dev.platform_data, | ||
| 23 | * and describing board-specific data needed by drivers. For example, | ||
| 24 | * which pin is used for a given GPIO role. | ||
| 25 | * | ||
| 26 | * In 2.6, drivers should strongly avoid board-specific knowledge so | ||
| 27 | * that supporting new boards normally won't require driver patches. | ||
| 28 | * Most board-specific knowledge should be in arch/.../board-*.c files. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #ifndef __ASM_ARCH_BOARD_H | ||
| 32 | #define __ASM_ARCH_BOARD_H | ||
| 33 | |||
| 34 | #include <linux/mtd/partitions.h> | ||
| 35 | #include <linux/device.h> | ||
| 36 | #include <linux/i2c.h> | ||
| 37 | #include <linux/leds.h> | ||
| 38 | #include <linux/spi/spi.h> | ||
| 39 | #include <linux/usb/atmel_usba_udc.h> | ||
| 40 | |||
| 41 | /* USB Device */ | ||
| 42 | struct at91_udc_data { | ||
| 43 | u8 vbus_pin; /* high == host powering us */ | ||
| 44 | u8 pullup_pin; /* active == D+ pulled up */ | ||
| 45 | u8 pullup_active_low; /* true == pullup_pin is active low */ | ||
| 46 | }; | ||
| 47 | extern void __init at91_add_device_udc(struct at91_udc_data *data); | ||
| 48 | |||
| 49 | /* USB High Speed Device */ | ||
| 50 | extern void __init at91_add_device_usba(struct usba_platform_data *data); | ||
| 51 | |||
| 52 | /* Compact Flash */ | ||
| 53 | struct at91_cf_data { | ||
| 54 | u8 irq_pin; /* I/O IRQ */ | ||
| 55 | u8 det_pin; /* Card detect */ | ||
| 56 | u8 vcc_pin; /* power switching */ | ||
| 57 | u8 rst_pin; /* card reset */ | ||
| 58 | u8 chipselect; /* EBI Chip Select number */ | ||
| 59 | }; | ||
| 60 | extern void __init at91_add_device_cf(struct at91_cf_data *data); | ||
| 61 | |||
| 62 | /* MMC / SD */ | ||
| 63 | struct at91_mmc_data { | ||
| 64 | u8 det_pin; /* card detect IRQ */ | ||
| 65 | unsigned slot_b:1; /* uses Slot B */ | ||
| 66 | unsigned wire4:1; /* (SD) supports DAT0..DAT3 */ | ||
| 67 | u8 wp_pin; /* (SD) writeprotect detect */ | ||
| 68 | u8 vcc_pin; /* power switching (high == on) */ | ||
| 69 | }; | ||
| 70 | extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data); | ||
| 71 | |||
| 72 | /* Ethernet (EMAC & MACB) */ | ||
| 73 | struct at91_eth_data { | ||
| 74 | u32 phy_mask; | ||
| 75 | u8 phy_irq_pin; /* PHY IRQ */ | ||
| 76 | u8 is_rmii; /* using RMII interface? */ | ||
| 77 | }; | ||
| 78 | extern void __init at91_add_device_eth(struct at91_eth_data *data); | ||
| 79 | |||
| 80 | #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) | ||
| 81 | #define eth_platform_data at91_eth_data | ||
| 82 | #endif | ||
| 83 | |||
| 84 | /* USB Host */ | ||
| 85 | struct at91_usbh_data { | ||
| 86 | u8 ports; /* number of ports on root hub */ | ||
| 87 | u8 vbus_pin[]; /* port power-control pin */ | ||
| 88 | }; | ||
| 89 | extern void __init at91_add_device_usbh(struct at91_usbh_data *data); | ||
| 90 | |||
| 91 | /* NAND / SmartMedia */ | ||
| 92 | struct atmel_nand_data { | ||
| 93 | u8 enable_pin; /* chip enable */ | ||
| 94 | u8 det_pin; /* card detect */ | ||
| 95 | u8 rdy_pin; /* ready/busy */ | ||
| 96 | u8 ale; /* address line number connected to ALE */ | ||
| 97 | u8 cle; /* address line number connected to CLE */ | ||
| 98 | u8 bus_width_16; /* buswidth is 16 bit */ | ||
| 99 | struct mtd_partition* (*partition_info)(int, int*); | ||
| 100 | }; | ||
| 101 | extern void __init at91_add_device_nand(struct atmel_nand_data *data); | ||
| 102 | |||
| 103 | /* I2C*/ | ||
| 104 | extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices); | ||
| 105 | |||
| 106 | /* SPI */ | ||
| 107 | extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices); | ||
| 108 | |||
| 109 | /* Serial */ | ||
| 110 | #define ATMEL_UART_CTS 0x01 | ||
| 111 | #define ATMEL_UART_RTS 0x02 | ||
| 112 | #define ATMEL_UART_DSR 0x04 | ||
| 113 | #define ATMEL_UART_DTR 0x08 | ||
| 114 | #define ATMEL_UART_DCD 0x10 | ||
| 115 | #define ATMEL_UART_RI 0x20 | ||
| 116 | |||
| 117 | extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins); | ||
| 118 | extern void __init at91_set_serial_console(unsigned portnr); | ||
| 119 | |||
| 120 | struct at91_uart_config { | ||
| 121 | unsigned short console_tty; /* tty number of serial console */ | ||
| 122 | unsigned short nr_tty; /* number of serial tty's */ | ||
| 123 | short tty_map[]; /* map UART to tty number */ | ||
| 124 | }; | ||
| 125 | extern struct platform_device *atmel_default_console_device; | ||
| 126 | extern void __init __deprecated at91_init_serial(struct at91_uart_config *config); | ||
| 127 | |||
| 128 | struct atmel_uart_data { | ||
| 129 | short use_dma_tx; /* use transmit DMA? */ | ||
| 130 | short use_dma_rx; /* use receive DMA? */ | ||
| 131 | void __iomem *regs; /* virtual base address, if any */ | ||
| 132 | }; | ||
| 133 | extern void __init at91_add_device_serial(void); | ||
| 134 | |||
| 135 | /* | ||
| 136 | * SSC -- accessed through ssc_request(id). Drivers don't bind to SSC | ||
| 137 | * platform devices. Their SSC ID is part of their configuration data, | ||
| 138 | * along with information about which SSC signals they should use. | ||
| 139 | */ | ||
| 140 | #define ATMEL_SSC_TK 0x01 | ||
| 141 | #define ATMEL_SSC_TF 0x02 | ||
| 142 | #define ATMEL_SSC_TD 0x04 | ||
| 143 | #define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD) | ||
| 144 | |||
| 145 | #define ATMEL_SSC_RK 0x10 | ||
| 146 | #define ATMEL_SSC_RF 0x20 | ||
| 147 | #define ATMEL_SSC_RD 0x40 | ||
| 148 | #define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD) | ||
| 149 | |||
| 150 | extern void __init at91_add_device_ssc(unsigned id, unsigned pins); | ||
| 151 | |||
| 152 | /* LCD Controller */ | ||
| 153 | struct atmel_lcdfb_info; | ||
| 154 | extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data); | ||
| 155 | |||
| 156 | /* AC97 */ | ||
| 157 | struct atmel_ac97_data { | ||
| 158 | u8 reset_pin; /* reset */ | ||
| 159 | }; | ||
| 160 | extern void __init at91_add_device_ac97(struct atmel_ac97_data *data); | ||
| 161 | |||
| 162 | /* ISI */ | ||
| 163 | extern void __init at91_add_device_isi(void); | ||
| 164 | |||
| 165 | /* LEDs */ | ||
| 166 | extern void __init at91_init_leds(u8 cpu_led, u8 timer_led); | ||
| 167 | extern void __init at91_gpio_leds(struct gpio_led *leds, int nr); | ||
| 168 | |||
| 169 | /* FIXME: this needs a better location, but gets stuff building again */ | ||
| 170 | extern int at91_suspend_entering_slow_clock(void); | ||
| 171 | |||
| 172 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h new file mode 100644 index 000000000000..dbfd9f73f80b --- /dev/null +++ b/arch/arm/mach-at91/include/mach/cpu.h | |||
| @@ -0,0 +1,103 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/cpu.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_CPU_H | ||
| 14 | #define __ASM_ARCH_CPU_H | ||
| 15 | |||
| 16 | #include <mach/hardware.h> | ||
| 17 | #include <mach/at91_dbgu.h> | ||
| 18 | |||
| 19 | |||
| 20 | #define ARCH_ID_AT91RM9200 0x09290780 | ||
| 21 | #define ARCH_ID_AT91SAM9260 0x019803a0 | ||
| 22 | #define ARCH_ID_AT91SAM9261 0x019703a0 | ||
| 23 | #define ARCH_ID_AT91SAM9263 0x019607a0 | ||
| 24 | #define ARCH_ID_AT91SAM9G20 0x019905a0 | ||
| 25 | #define ARCH_ID_AT91SAM9RL64 0x019b03a0 | ||
| 26 | #define ARCH_ID_AT91CAP9 0x039A03A0 | ||
| 27 | |||
| 28 | #define ARCH_ID_AT91SAM9XE128 0x329973a0 | ||
| 29 | #define ARCH_ID_AT91SAM9XE256 0x329a93a0 | ||
| 30 | #define ARCH_ID_AT91SAM9XE512 0x329aa3a0 | ||
| 31 | |||
| 32 | #define ARCH_ID_AT91M40800 0x14080044 | ||
| 33 | #define ARCH_ID_AT91R40807 0x44080746 | ||
| 34 | #define ARCH_ID_AT91M40807 0x14080745 | ||
| 35 | #define ARCH_ID_AT91R40008 0x44000840 | ||
| 36 | |||
| 37 | static inline unsigned long at91_cpu_identify(void) | ||
| 38 | { | ||
| 39 | return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); | ||
| 40 | } | ||
| 41 | |||
| 42 | |||
| 43 | #define ARCH_FAMILY_AT91X92 0x09200000 | ||
| 44 | #define ARCH_FAMILY_AT91SAM9 0x01900000 | ||
| 45 | #define ARCH_FAMILY_AT91SAM9XE 0x02900000 | ||
| 46 | |||
| 47 | static inline unsigned long at91_arch_identify(void) | ||
| 48 | { | ||
| 49 | return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH); | ||
| 50 | } | ||
| 51 | |||
| 52 | |||
| 53 | #ifdef CONFIG_ARCH_AT91RM9200 | ||
| 54 | #define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200) | ||
| 55 | #else | ||
| 56 | #define cpu_is_at91rm9200() (0) | ||
| 57 | #endif | ||
| 58 | |||
| 59 | #ifdef CONFIG_ARCH_AT91SAM9260 | ||
| 60 | #define cpu_is_at91sam9xe() (at91_arch_identify() == ARCH_FAMILY_AT91SAM9XE) | ||
| 61 | #define cpu_is_at91sam9260() ((at91_cpu_identify() == ARCH_ID_AT91SAM9260) || cpu_is_at91sam9xe()) | ||
| 62 | #else | ||
| 63 | #define cpu_is_at91sam9xe() (0) | ||
| 64 | #define cpu_is_at91sam9260() (0) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #ifdef CONFIG_ARCH_AT91SAM9G20 | ||
| 68 | #define cpu_is_at91sam9g20() (at91_cpu_identify() == ARCH_ID_AT91SAM9G20) | ||
| 69 | #else | ||
| 70 | #define cpu_is_at91sam9g20() (0) | ||
| 71 | #endif | ||
| 72 | |||
| 73 | #ifdef CONFIG_ARCH_AT91SAM9261 | ||
| 74 | #define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261) | ||
| 75 | #else | ||
| 76 | #define cpu_is_at91sam9261() (0) | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifdef CONFIG_ARCH_AT91SAM9263 | ||
| 80 | #define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263) | ||
| 81 | #else | ||
| 82 | #define cpu_is_at91sam9263() (0) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | #ifdef CONFIG_ARCH_AT91SAM9RL | ||
| 86 | #define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64) | ||
| 87 | #else | ||
| 88 | #define cpu_is_at91sam9rl() (0) | ||
| 89 | #endif | ||
| 90 | |||
| 91 | #ifdef CONFIG_ARCH_AT91CAP9 | ||
| 92 | #define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9) | ||
| 93 | #else | ||
| 94 | #define cpu_is_at91cap9() (0) | ||
| 95 | #endif | ||
| 96 | |||
| 97 | /* | ||
| 98 | * Since this is ARM, we will never run on any AVR32 CPU. But these | ||
| 99 | * definitions may reduce clutter in common drivers. | ||
| 100 | */ | ||
| 101 | #define cpu_is_at32ap7000() (0) | ||
| 102 | |||
| 103 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S new file mode 100644 index 000000000000..29052ba66ada --- /dev/null +++ b/arch/arm/mach-at91/include/mach/debug-macro.S | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/debug-macro.S | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003-2005 SAN People | ||
| 5 | * | ||
| 6 | * Debugging macro include header | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <mach/hardware.h> | ||
| 15 | #include <mach/at91_dbgu.h> | ||
| 16 | |||
| 17 | .macro addruart,rx | ||
| 18 | mrc p15, 0, \rx, c1, c0 | ||
| 19 | tst \rx, #1 @ MMU enabled? | ||
| 20 | ldreq \rx, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) | ||
| 21 | ldrne \rx, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address) | ||
| 22 | .endm | ||
| 23 | |||
| 24 | .macro senduart,rd,rx | ||
| 25 | strb \rd, [\rx, #(AT91_DBGU_THR - AT91_DBGU)] @ Write to Transmitter Holding Register | ||
| 26 | .endm | ||
| 27 | |||
| 28 | .macro waituart,rd,rx | ||
| 29 | 1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register | ||
| 30 | tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit | ||
| 31 | beq 1001b | ||
| 32 | .endm | ||
| 33 | |||
| 34 | .macro busyuart,rd,rx | ||
| 35 | 1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register | ||
| 36 | tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete | ||
| 37 | beq 1001b | ||
| 38 | .endm | ||
| 39 | |||
diff --git a/arch/arm/mach-at91/include/mach/dma.h b/arch/arm/mach-at91/include/mach/dma.h new file mode 100644 index 000000000000..e4f90c177616 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/dma.h | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
diff --git a/arch/arm/mach-at91/include/mach/entry-macro.S b/arch/arm/mach-at91/include/mach/entry-macro.S new file mode 100644 index 000000000000..7ab68f972227 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/entry-macro.S | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/entry-macro.S | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003-2005 SAN People | ||
| 5 | * | ||
| 6 | * Low-level IRQ helper macros for AT91RM9200 platforms | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <mach/hardware.h> | ||
| 14 | #include <mach/at91_aic.h> | ||
| 15 | |||
| 16 | .macro disable_fiq | ||
| 17 | .endm | ||
| 18 | |||
| 19 | .macro get_irqnr_preamble, base, tmp | ||
| 20 | ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral | ||
| 21 | .endm | ||
| 22 | |||
| 23 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 24 | .endm | ||
| 25 | |||
| 26 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 27 | ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) | ||
| 28 | ldr \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)] @ read interrupt source number | ||
| 29 | teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt | ||
| 30 | streq \tmp, [\base, #(AT91_AIC_EOICR - AT91_AIC)] @ not going to be handled further, then ACK it now. | ||
| 31 | .endm | ||
| 32 | |||
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h new file mode 100644 index 000000000000..76d76e2fa69e --- /dev/null +++ b/arch/arm/mach-at91/include/mach/gpio.h | |||
| @@ -0,0 +1,252 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/gpio.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 HP Labs | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_AT91RM9200_GPIO_H | ||
| 14 | #define __ASM_ARCH_AT91RM9200_GPIO_H | ||
| 15 | |||
| 16 | #include <asm/irq.h> | ||
| 17 | |||
| 18 | #define PIN_BASE NR_AIC_IRQS | ||
| 19 | |||
| 20 | #define MAX_GPIO_BANKS 5 | ||
| 21 | |||
| 22 | /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ | ||
| 23 | |||
| 24 | #define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) | ||
| 25 | #define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) | ||
| 26 | #define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2) | ||
| 27 | #define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3) | ||
| 28 | #define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4) | ||
| 29 | #define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5) | ||
| 30 | #define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6) | ||
| 31 | #define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7) | ||
| 32 | #define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8) | ||
| 33 | #define AT91_PIN_PA9 (PIN_BASE + 0x00 + 9) | ||
| 34 | #define AT91_PIN_PA10 (PIN_BASE + 0x00 + 10) | ||
| 35 | #define AT91_PIN_PA11 (PIN_BASE + 0x00 + 11) | ||
| 36 | #define AT91_PIN_PA12 (PIN_BASE + 0x00 + 12) | ||
| 37 | #define AT91_PIN_PA13 (PIN_BASE + 0x00 + 13) | ||
| 38 | #define AT91_PIN_PA14 (PIN_BASE + 0x00 + 14) | ||
| 39 | #define AT91_PIN_PA15 (PIN_BASE + 0x00 + 15) | ||
| 40 | #define AT91_PIN_PA16 (PIN_BASE + 0x00 + 16) | ||
| 41 | #define AT91_PIN_PA17 (PIN_BASE + 0x00 + 17) | ||
| 42 | #define AT91_PIN_PA18 (PIN_BASE + 0x00 + 18) | ||
| 43 | #define AT91_PIN_PA19 (PIN_BASE + 0x00 + 19) | ||
| 44 | #define AT91_PIN_PA20 (PIN_BASE + 0x00 + 20) | ||
| 45 | #define AT91_PIN_PA21 (PIN_BASE + 0x00 + 21) | ||
| 46 | #define AT91_PIN_PA22 (PIN_BASE + 0x00 + 22) | ||
| 47 | #define AT91_PIN_PA23 (PIN_BASE + 0x00 + 23) | ||
| 48 | #define AT91_PIN_PA24 (PIN_BASE + 0x00 + 24) | ||
| 49 | #define AT91_PIN_PA25 (PIN_BASE + 0x00 + 25) | ||
| 50 | #define AT91_PIN_PA26 (PIN_BASE + 0x00 + 26) | ||
| 51 | #define AT91_PIN_PA27 (PIN_BASE + 0x00 + 27) | ||
| 52 | #define AT91_PIN_PA28 (PIN_BASE + 0x00 + 28) | ||
| 53 | #define AT91_PIN_PA29 (PIN_BASE + 0x00 + 29) | ||
| 54 | #define AT91_PIN_PA30 (PIN_BASE + 0x00 + 30) | ||
| 55 | #define AT91_PIN_PA31 (PIN_BASE + 0x00 + 31) | ||
| 56 | |||
| 57 | #define AT91_PIN_PB0 (PIN_BASE + 0x20 + 0) | ||
| 58 | #define AT91_PIN_PB1 (PIN_BASE + 0x20 + 1) | ||
| 59 | #define AT91_PIN_PB2 (PIN_BASE + 0x20 + 2) | ||
| 60 | #define AT91_PIN_PB3 (PIN_BASE + 0x20 + 3) | ||
| 61 | #define AT91_PIN_PB4 (PIN_BASE + 0x20 + 4) | ||
| 62 | #define AT91_PIN_PB5 (PIN_BASE + 0x20 + 5) | ||
| 63 | #define AT91_PIN_PB6 (PIN_BASE + 0x20 + 6) | ||
| 64 | #define AT91_PIN_PB7 (PIN_BASE + 0x20 + 7) | ||
| 65 | #define AT91_PIN_PB8 (PIN_BASE + 0x20 + 8) | ||
| 66 | #define AT91_PIN_PB9 (PIN_BASE + 0x20 + 9) | ||
| 67 | #define AT91_PIN_PB10 (PIN_BASE + 0x20 + 10) | ||
| 68 | #define AT91_PIN_PB11 (PIN_BASE + 0x20 + 11) | ||
| 69 | #define AT91_PIN_PB12 (PIN_BASE + 0x20 + 12) | ||
| 70 | #define AT91_PIN_PB13 (PIN_BASE + 0x20 + 13) | ||
| 71 | #define AT91_PIN_PB14 (PIN_BASE + 0x20 + 14) | ||
| 72 | #define AT91_PIN_PB15 (PIN_BASE + 0x20 + 15) | ||
| 73 | #define AT91_PIN_PB16 (PIN_BASE + 0x20 + 16) | ||
| 74 | #define AT91_PIN_PB17 (PIN_BASE + 0x20 + 17) | ||
| 75 | #define AT91_PIN_PB18 (PIN_BASE + 0x20 + 18) | ||
| 76 | #define AT91_PIN_PB19 (PIN_BASE + 0x20 + 19) | ||
| 77 | #define AT91_PIN_PB20 (PIN_BASE + 0x20 + 20) | ||
| 78 | #define AT91_PIN_PB21 (PIN_BASE + 0x20 + 21) | ||
| 79 | #define AT91_PIN_PB22 (PIN_BASE + 0x20 + 22) | ||
| 80 | #define AT91_PIN_PB23 (PIN_BASE + 0x20 + 23) | ||
| 81 | #define AT91_PIN_PB24 (PIN_BASE + 0x20 + 24) | ||
| 82 | #define AT91_PIN_PB25 (PIN_BASE + 0x20 + 25) | ||
| 83 | #define AT91_PIN_PB26 (PIN_BASE + 0x20 + 26) | ||
| 84 | #define AT91_PIN_PB27 (PIN_BASE + 0x20 + 27) | ||
| 85 | #define AT91_PIN_PB28 (PIN_BASE + 0x20 + 28) | ||
| 86 | #define AT91_PIN_PB29 (PIN_BASE + 0x20 + 29) | ||
| 87 | #define AT91_PIN_PB30 (PIN_BASE + 0x20 + 30) | ||
| 88 | #define AT91_PIN_PB31 (PIN_BASE + 0x20 + 31) | ||
| 89 | |||
| 90 | #define AT91_PIN_PC0 (PIN_BASE + 0x40 + 0) | ||
| 91 | #define AT91_PIN_PC1 (PIN_BASE + 0x40 + 1) | ||
| 92 | #define AT91_PIN_PC2 (PIN_BASE + 0x40 + 2) | ||
| 93 | #define AT91_PIN_PC3 (PIN_BASE + 0x40 + 3) | ||
| 94 | #define AT91_PIN_PC4 (PIN_BASE + 0x40 + 4) | ||
| 95 | #define AT91_PIN_PC5 (PIN_BASE + 0x40 + 5) | ||
| 96 | #define AT91_PIN_PC6 (PIN_BASE + 0x40 + 6) | ||
| 97 | #define AT91_PIN_PC7 (PIN_BASE + 0x40 + 7) | ||
| 98 | #define AT91_PIN_PC8 (PIN_BASE + 0x40 + 8) | ||
| 99 | #define AT91_PIN_PC9 (PIN_BASE + 0x40 + 9) | ||
| 100 | #define AT91_PIN_PC10 (PIN_BASE + 0x40 + 10) | ||
| 101 | #define AT91_PIN_PC11 (PIN_BASE + 0x40 + 11) | ||
| 102 | #define AT91_PIN_PC12 (PIN_BASE + 0x40 + 12) | ||
| 103 | #define AT91_PIN_PC13 (PIN_BASE + 0x40 + 13) | ||
| 104 | #define AT91_PIN_PC14 (PIN_BASE + 0x40 + 14) | ||
| 105 | #define AT91_PIN_PC15 (PIN_BASE + 0x40 + 15) | ||
| 106 | #define AT91_PIN_PC16 (PIN_BASE + 0x40 + 16) | ||
| 107 | #define AT91_PIN_PC17 (PIN_BASE + 0x40 + 17) | ||
| 108 | #define AT91_PIN_PC18 (PIN_BASE + 0x40 + 18) | ||
| 109 | #define AT91_PIN_PC19 (PIN_BASE + 0x40 + 19) | ||
| 110 | #define AT91_PIN_PC20 (PIN_BASE + 0x40 + 20) | ||
| 111 | #define AT91_PIN_PC21 (PIN_BASE + 0x40 + 21) | ||
| 112 | #define AT91_PIN_PC22 (PIN_BASE + 0x40 + 22) | ||
| 113 | #define AT91_PIN_PC23 (PIN_BASE + 0x40 + 23) | ||
| 114 | #define AT91_PIN_PC24 (PIN_BASE + 0x40 + 24) | ||
| 115 | #define AT91_PIN_PC25 (PIN_BASE + 0x40 + 25) | ||
| 116 | #define AT91_PIN_PC26 (PIN_BASE + 0x40 + 26) | ||
| 117 | #define AT91_PIN_PC27 (PIN_BASE + 0x40 + 27) | ||
| 118 | #define AT91_PIN_PC28 (PIN_BASE + 0x40 + 28) | ||
| 119 | #define AT91_PIN_PC29 (PIN_BASE + 0x40 + 29) | ||
| 120 | #define AT91_PIN_PC30 (PIN_BASE + 0x40 + 30) | ||
| 121 | #define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31) | ||
| 122 | |||
| 123 | #define AT91_PIN_PD0 (PIN_BASE + 0x60 + 0) | ||
| 124 | #define AT91_PIN_PD1 (PIN_BASE + 0x60 + 1) | ||
| 125 | #define AT91_PIN_PD2 (PIN_BASE + 0x60 + 2) | ||
| 126 | #define AT91_PIN_PD3 (PIN_BASE + 0x60 + 3) | ||
| 127 | #define AT91_PIN_PD4 (PIN_BASE + 0x60 + 4) | ||
| 128 | #define AT91_PIN_PD5 (PIN_BASE + 0x60 + 5) | ||
| 129 | #define AT91_PIN_PD6 (PIN_BASE + 0x60 + 6) | ||
| 130 | #define AT91_PIN_PD7 (PIN_BASE + 0x60 + 7) | ||
| 131 | #define AT91_PIN_PD8 (PIN_BASE + 0x60 + 8) | ||
| 132 | #define AT91_PIN_PD9 (PIN_BASE + 0x60 + 9) | ||
| 133 | #define AT91_PIN_PD10 (PIN_BASE + 0x60 + 10) | ||
| 134 | #define AT91_PIN_PD11 (PIN_BASE + 0x60 + 11) | ||
| 135 | #define AT91_PIN_PD12 (PIN_BASE + 0x60 + 12) | ||
| 136 | #define AT91_PIN_PD13 (PIN_BASE + 0x60 + 13) | ||
| 137 | #define AT91_PIN_PD14 (PIN_BASE + 0x60 + 14) | ||
| 138 | #define AT91_PIN_PD15 (PIN_BASE + 0x60 + 15) | ||
| 139 | #define AT91_PIN_PD16 (PIN_BASE + 0x60 + 16) | ||
| 140 | #define AT91_PIN_PD17 (PIN_BASE + 0x60 + 17) | ||
| 141 | #define AT91_PIN_PD18 (PIN_BASE + 0x60 + 18) | ||
| 142 | #define AT91_PIN_PD19 (PIN_BASE + 0x60 + 19) | ||
| 143 | #define AT91_PIN_PD20 (PIN_BASE + 0x60 + 20) | ||
| 144 | #define AT91_PIN_PD21 (PIN_BASE + 0x60 + 21) | ||
| 145 | #define AT91_PIN_PD22 (PIN_BASE + 0x60 + 22) | ||
| 146 | #define AT91_PIN_PD23 (PIN_BASE + 0x60 + 23) | ||
| 147 | #define AT91_PIN_PD24 (PIN_BASE + 0x60 + 24) | ||
| 148 | #define AT91_PIN_PD25 (PIN_BASE + 0x60 + 25) | ||
| 149 | #define AT91_PIN_PD26 (PIN_BASE + 0x60 + 26) | ||
| 150 | #define AT91_PIN_PD27 (PIN_BASE + 0x60 + 27) | ||
| 151 | #define AT91_PIN_PD28 (PIN_BASE + 0x60 + 28) | ||
| 152 | #define AT91_PIN_PD29 (PIN_BASE + 0x60 + 29) | ||
| 153 | #define AT91_PIN_PD30 (PIN_BASE + 0x60 + 30) | ||
| 154 | #define AT91_PIN_PD31 (PIN_BASE + 0x60 + 31) | ||
| 155 | |||
| 156 | #define AT91_PIN_PE0 (PIN_BASE + 0x80 + 0) | ||
| 157 | #define AT91_PIN_PE1 (PIN_BASE + 0x80 + 1) | ||
| 158 | #define AT91_PIN_PE2 (PIN_BASE + 0x80 + 2) | ||
| 159 | #define AT91_PIN_PE3 (PIN_BASE + 0x80 + 3) | ||
| 160 | #define AT91_PIN_PE4 (PIN_BASE + 0x80 + 4) | ||
| 161 | #define AT91_PIN_PE5 (PIN_BASE + 0x80 + 5) | ||
| 162 | #define AT91_PIN_PE6 (PIN_BASE + 0x80 + 6) | ||
| 163 | #define AT91_PIN_PE7 (PIN_BASE + 0x80 + 7) | ||
| 164 | #define AT91_PIN_PE8 (PIN_BASE + 0x80 + 8) | ||
| 165 | #define AT91_PIN_PE9 (PIN_BASE + 0x80 + 9) | ||
| 166 | #define AT91_PIN_PE10 (PIN_BASE + 0x80 + 10) | ||
| 167 | #define AT91_PIN_PE11 (PIN_BASE + 0x80 + 11) | ||
| 168 | #define AT91_PIN_PE12 (PIN_BASE + 0x80 + 12) | ||
| 169 | #define AT91_PIN_PE13 (PIN_BASE + 0x80 + 13) | ||
| 170 | #define AT91_PIN_PE14 (PIN_BASE + 0x80 + 14) | ||
| 171 | #define AT91_PIN_PE15 (PIN_BASE + 0x80 + 15) | ||
| 172 | #define AT91_PIN_PE16 (PIN_BASE + 0x80 + 16) | ||
| 173 | #define AT91_PIN_PE17 (PIN_BASE + 0x80 + 17) | ||
| 174 | #define AT91_PIN_PE18 (PIN_BASE + 0x80 + 18) | ||
| 175 | #define AT91_PIN_PE19 (PIN_BASE + 0x80 + 19) | ||
| 176 | #define AT91_PIN_PE20 (PIN_BASE + 0x80 + 20) | ||
| 177 | #define AT91_PIN_PE21 (PIN_BASE + 0x80 + 21) | ||
| 178 | #define AT91_PIN_PE22 (PIN_BASE + 0x80 + 22) | ||
| 179 | #define AT91_PIN_PE23 (PIN_BASE + 0x80 + 23) | ||
| 180 | #define AT91_PIN_PE24 (PIN_BASE + 0x80 + 24) | ||
| 181 | #define AT91_PIN_PE25 (PIN_BASE + 0x80 + 25) | ||
| 182 | #define AT91_PIN_PE26 (PIN_BASE + 0x80 + 26) | ||
| 183 | #define AT91_PIN_PE27 (PIN_BASE + 0x80 + 27) | ||
| 184 | #define AT91_PIN_PE28 (PIN_BASE + 0x80 + 28) | ||
| 185 | #define AT91_PIN_PE29 (PIN_BASE + 0x80 + 29) | ||
| 186 | #define AT91_PIN_PE30 (PIN_BASE + 0x80 + 30) | ||
| 187 | #define AT91_PIN_PE31 (PIN_BASE + 0x80 + 31) | ||
| 188 | |||
| 189 | #ifndef __ASSEMBLY__ | ||
| 190 | /* setup setup routines, called from board init or driver probe() */ | ||
| 191 | extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup); | ||
| 192 | extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup); | ||
| 193 | extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup); | ||
| 194 | extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup); | ||
| 195 | extern int __init_or_module at91_set_gpio_output(unsigned pin, int value); | ||
| 196 | extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on); | ||
| 197 | extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on); | ||
| 198 | |||
| 199 | /* callable at any time */ | ||
| 200 | extern int at91_set_gpio_value(unsigned pin, int value); | ||
| 201 | extern int at91_get_gpio_value(unsigned pin); | ||
| 202 | |||
| 203 | /* callable only from core power-management code */ | ||
| 204 | extern void at91_gpio_suspend(void); | ||
| 205 | extern void at91_gpio_resume(void); | ||
| 206 | |||
| 207 | /*-------------------------------------------------------------------------*/ | ||
| 208 | |||
| 209 | /* wrappers for "new style" GPIO calls. the old AT91-specfic ones should | ||
| 210 | * eventually be removed (along with this errno.h inclusion), and the | ||
| 211 | * gpio request/free calls should probably be implemented. | ||
| 212 | */ | ||
| 213 | |||
| 214 | #include <asm/errno.h> | ||
| 215 | |||
| 216 | static inline int gpio_request(unsigned gpio, const char *label) | ||
| 217 | { | ||
| 218 | return 0; | ||
| 219 | } | ||
| 220 | |||
| 221 | static inline void gpio_free(unsigned gpio) | ||
| 222 | { | ||
| 223 | } | ||
| 224 | |||
| 225 | extern int gpio_direction_input(unsigned gpio); | ||
| 226 | extern int gpio_direction_output(unsigned gpio, int value); | ||
| 227 | |||
| 228 | static inline int gpio_get_value(unsigned gpio) | ||
| 229 | { | ||
| 230 | return at91_get_gpio_value(gpio); | ||
| 231 | } | ||
| 232 | |||
| 233 | static inline void gpio_set_value(unsigned gpio, int value) | ||
| 234 | { | ||
| 235 | at91_set_gpio_value(gpio, value); | ||
| 236 | } | ||
| 237 | |||
| 238 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | ||
| 239 | |||
| 240 | static inline int gpio_to_irq(unsigned gpio) | ||
| 241 | { | ||
| 242 | return gpio; | ||
| 243 | } | ||
| 244 | |||
| 245 | static inline int irq_to_gpio(unsigned irq) | ||
| 246 | { | ||
| 247 | return irq; | ||
| 248 | } | ||
| 249 | |||
| 250 | #endif /* __ASSEMBLY__ */ | ||
| 251 | |||
| 252 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h new file mode 100644 index 000000000000..da0b681c652c --- /dev/null +++ b/arch/arm/mach-at91/include/mach/hardware.h | |||
| @@ -0,0 +1,92 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/hardware.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * Copyright (C) 2003 ATMEL | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 15 | #define __ASM_ARCH_HARDWARE_H | ||
| 16 | |||
| 17 | #include <asm/sizes.h> | ||
| 18 | |||
| 19 | #if defined(CONFIG_ARCH_AT91RM9200) | ||
| 20 | #include <mach/at91rm9200.h> | ||
| 21 | #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) | ||
| 22 | #include <mach/at91sam9260.h> | ||
| 23 | #elif defined(CONFIG_ARCH_AT91SAM9261) | ||
| 24 | #include <mach/at91sam9261.h> | ||
| 25 | #elif defined(CONFIG_ARCH_AT91SAM9263) | ||
| 26 | #include <mach/at91sam9263.h> | ||
| 27 | #elif defined(CONFIG_ARCH_AT91SAM9RL) | ||
| 28 | #include <mach/at91sam9rl.h> | ||
| 29 | #elif defined(CONFIG_ARCH_AT91CAP9) | ||
| 30 | #include <mach/at91cap9.h> | ||
| 31 | #elif defined(CONFIG_ARCH_AT91X40) | ||
| 32 | #include <mach/at91x40.h> | ||
| 33 | #else | ||
| 34 | #error "Unsupported AT91 processor" | ||
| 35 | #endif | ||
| 36 | |||
| 37 | |||
| 38 | #ifdef CONFIG_MMU | ||
| 39 | /* | ||
| 40 | * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF | ||
| 41 | * to 0xFEF78000 .. 0xFF000000. (544Kb) | ||
| 42 | */ | ||
| 43 | #define AT91_IO_PHYS_BASE 0xFFF78000 | ||
| 44 | #define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE) | ||
| 45 | #else | ||
| 46 | /* | ||
| 47 | * Identity mapping for the non MMU case. | ||
| 48 | */ | ||
| 49 | #define AT91_IO_PHYS_BASE AT91_BASE_SYS | ||
| 50 | #define AT91_IO_VIRT_BASE AT91_IO_PHYS_BASE | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) | ||
| 54 | |||
| 55 | /* Convert a physical IO address to virtual IO address */ | ||
| 56 | #define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE) | ||
| 57 | |||
| 58 | /* | ||
| 59 | * Virtual to Physical Address mapping for IO devices. | ||
| 60 | */ | ||
| 61 | #define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) | ||
| 62 | #define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC) | ||
| 63 | |||
| 64 | /* Internal SRAM is mapped below the IO devices */ | ||
| 65 | #define AT91_SRAM_MAX SZ_1M | ||
| 66 | #define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX) | ||
| 67 | |||
| 68 | /* Serial ports */ | ||
| 69 | #define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */ | ||
| 70 | |||
| 71 | /* External Memory Map */ | ||
| 72 | #define AT91_CHIPSELECT_0 0x10000000 | ||
| 73 | #define AT91_CHIPSELECT_1 0x20000000 | ||
| 74 | #define AT91_CHIPSELECT_2 0x30000000 | ||
| 75 | #define AT91_CHIPSELECT_3 0x40000000 | ||
| 76 | #define AT91_CHIPSELECT_4 0x50000000 | ||
| 77 | #define AT91_CHIPSELECT_5 0x60000000 | ||
| 78 | #define AT91_CHIPSELECT_6 0x70000000 | ||
| 79 | #define AT91_CHIPSELECT_7 0x80000000 | ||
| 80 | |||
| 81 | /* SDRAM */ | ||
| 82 | #ifdef CONFIG_DRAM_BASE | ||
| 83 | #define AT91_SDRAM_BASE CONFIG_DRAM_BASE | ||
| 84 | #else | ||
| 85 | #define AT91_SDRAM_BASE AT91_CHIPSELECT_1 | ||
| 86 | #endif | ||
| 87 | |||
| 88 | /* Clocks */ | ||
| 89 | #define AT91_SLOW_CLOCK 32768 /* slow clock */ | ||
| 90 | |||
| 91 | |||
| 92 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h new file mode 100644 index 000000000000..1611bd03f528 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/io.h | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_IO_H | ||
| 22 | #define __ASM_ARCH_IO_H | ||
| 23 | |||
| 24 | #define IO_SPACE_LIMIT 0xFFFFFFFF | ||
| 25 | |||
| 26 | #define __io(a) ((void __iomem *)(a)) | ||
| 27 | #define __mem_pci(a) (a) | ||
| 28 | |||
| 29 | |||
| 30 | #ifndef __ASSEMBLY__ | ||
| 31 | |||
| 32 | static inline unsigned int at91_sys_read(unsigned int reg_offset) | ||
| 33 | { | ||
| 34 | void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; | ||
| 35 | |||
| 36 | return __raw_readl(addr + reg_offset); | ||
| 37 | } | ||
| 38 | |||
| 39 | static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) | ||
| 40 | { | ||
| 41 | void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; | ||
| 42 | |||
| 43 | __raw_writel(value, addr + reg_offset); | ||
| 44 | } | ||
| 45 | |||
| 46 | #endif | ||
| 47 | |||
| 48 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h new file mode 100644 index 000000000000..bda29ccbcd94 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/irqs.h | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_IRQS_H | ||
| 22 | #define __ASM_ARCH_IRQS_H | ||
| 23 | |||
| 24 | #include <asm/io.h> | ||
| 25 | #include <mach/at91_aic.h> | ||
| 26 | |||
| 27 | #define NR_AIC_IRQS 32 | ||
| 28 | |||
| 29 | |||
| 30 | /* | ||
| 31 | * Acknowledge interrupt with AIC after interrupt has been handled. | ||
| 32 | * (by kernel/irq.c) | ||
| 33 | */ | ||
| 34 | #define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0) | ||
| 35 | |||
| 36 | |||
| 37 | /* | ||
| 38 | * IRQ interrupt symbols are the AT91xxx_ID_* symbols | ||
| 39 | * for IRQs handled directly through the AIC, or else the AT91_PIN_* | ||
| 40 | * symbols in gpio.h for ones handled indirectly as GPIOs. | ||
| 41 | * We make provision for 5 banks of GPIO. | ||
| 42 | */ | ||
| 43 | #define NR_IRQS (NR_AIC_IRQS + (5 * 32)) | ||
| 44 | |||
| 45 | /* FIQ is AIC source 0. */ | ||
| 46 | #define FIQ_START AT91_ID_FIQ | ||
| 47 | |||
| 48 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/memory.h b/arch/arm/mach-at91/include/mach/memory.h new file mode 100644 index 000000000000..9dd1b8c79b08 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/memory.h | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 22 | #define __ASM_ARCH_MEMORY_H | ||
| 23 | |||
| 24 | #include <mach/hardware.h> | ||
| 25 | |||
| 26 | #define PHYS_OFFSET (AT91_SDRAM_BASE) | ||
| 27 | |||
| 28 | |||
| 29 | /* | ||
| 30 | * Virtual view <-> DMA view memory address translations | ||
| 31 | * virt_to_bus: Used to translate the virtual address to an | ||
| 32 | * address suitable to be passed to set_dma_addr | ||
| 33 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 34 | * to an address that the kernel can use. | ||
| 35 | */ | ||
| 36 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
| 37 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
| 38 | |||
| 39 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h new file mode 100644 index 000000000000..e712658d966c --- /dev/null +++ b/arch/arm/mach-at91/include/mach/system.h | |||
| @@ -0,0 +1,53 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 22 | #define __ASM_ARCH_SYSTEM_H | ||
| 23 | |||
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/at91_st.h> | ||
| 26 | #include <mach/at91_dbgu.h> | ||
| 27 | |||
| 28 | static inline void arch_idle(void) | ||
| 29 | { | ||
| 30 | /* | ||
| 31 | * Disable the processor clock. The processor will be automatically | ||
| 32 | * re-enabled by an interrupt or by a reset. | ||
| 33 | */ | ||
| 34 | // at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); | ||
| 35 | |||
| 36 | /* | ||
| 37 | * Set the processor (CP15) into 'Wait for Interrupt' mode. | ||
| 38 | * Unlike disabling the processor clock via the PMC (above) | ||
| 39 | * this allows the processor to be woken via JTAG. | ||
| 40 | */ | ||
| 41 | cpu_do_idle(); | ||
| 42 | } | ||
| 43 | |||
| 44 | void (*at91_arch_reset)(void); | ||
| 45 | |||
| 46 | static inline void arch_reset(char mode) | ||
| 47 | { | ||
| 48 | /* call the CPU-specific reset function */ | ||
| 49 | if (at91_arch_reset) | ||
| 50 | (at91_arch_reset)(); | ||
| 51 | } | ||
| 52 | |||
| 53 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h new file mode 100644 index 000000000000..d84c9948becf --- /dev/null +++ b/arch/arm/mach-at91/include/mach/timex.h | |||
| @@ -0,0 +1,77 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_TIMEX_H | ||
| 22 | #define __ASM_ARCH_TIMEX_H | ||
| 23 | |||
| 24 | #include <mach/hardware.h> | ||
| 25 | |||
| 26 | #if defined(CONFIG_ARCH_AT91RM9200) | ||
| 27 | |||
| 28 | #define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) | ||
| 29 | |||
| 30 | #elif defined(CONFIG_ARCH_AT91SAM9260) | ||
| 31 | |||
| 32 | #if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260) | ||
| 33 | #define AT91SAM9_MASTER_CLOCK 90000000 | ||
| 34 | #else | ||
| 35 | #define AT91SAM9_MASTER_CLOCK 99300000 | ||
| 36 | #endif | ||
| 37 | |||
| 38 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
| 39 | |||
| 40 | #elif defined(CONFIG_ARCH_AT91SAM9261) | ||
| 41 | |||
| 42 | #define AT91SAM9_MASTER_CLOCK 99300000 | ||
| 43 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
| 44 | |||
| 45 | #elif defined(CONFIG_ARCH_AT91SAM9263) | ||
| 46 | |||
| 47 | #if defined(CONFIG_MACH_USB_A9263) | ||
| 48 | #define AT91SAM9_MASTER_CLOCK 90000000 | ||
| 49 | #else | ||
| 50 | #define AT91SAM9_MASTER_CLOCK 99959500 | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
| 54 | |||
| 55 | #elif defined(CONFIG_ARCH_AT91SAM9RL) | ||
| 56 | |||
| 57 | #define AT91SAM9_MASTER_CLOCK 100000000 | ||
| 58 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
| 59 | |||
| 60 | #elif defined(CONFIG_ARCH_AT91SAM9G20) | ||
| 61 | |||
| 62 | #define AT91SAM9_MASTER_CLOCK 132096000 | ||
| 63 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
| 64 | |||
| 65 | #elif defined(CONFIG_ARCH_AT91CAP9) | ||
| 66 | |||
| 67 | #define AT91CAP9_MASTER_CLOCK 100000000 | ||
| 68 | #define CLOCK_TICK_RATE (AT91CAP9_MASTER_CLOCK/16) | ||
| 69 | |||
| 70 | #elif defined(CONFIG_ARCH_AT91X40) | ||
| 71 | |||
| 72 | #define AT91X40_MASTER_CLOCK 40000000 | ||
| 73 | #define CLOCK_TICK_RATE (AT91X40_MASTER_CLOCK) | ||
| 74 | |||
| 75 | #endif | ||
| 76 | |||
| 77 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h new file mode 100644 index 000000000000..0410d548e9b1 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/uncompress.h | |||
| @@ -0,0 +1,76 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
| 22 | #define __ASM_ARCH_UNCOMPRESS_H | ||
| 23 | |||
| 24 | #include <asm/io.h> | ||
| 25 | #include <linux/atmel_serial.h> | ||
| 26 | |||
| 27 | #if defined(CONFIG_AT91_EARLY_DBGU) | ||
| 28 | #define UART_OFFSET (AT91_DBGU + AT91_BASE_SYS) | ||
| 29 | #elif defined(CONFIG_AT91_EARLY_USART0) | ||
| 30 | #define UART_OFFSET AT91_USART0 | ||
| 31 | #elif defined(CONFIG_AT91_EARLY_USART1) | ||
| 32 | #define UART_OFFSET AT91_USART1 | ||
| 33 | #elif defined(CONFIG_AT91_EARLY_USART2) | ||
| 34 | #define UART_OFFSET AT91_USART2 | ||
| 35 | #elif defined(CONFIG_AT91_EARLY_USART3) | ||
| 36 | #define UART_OFFSET AT91_USART3 | ||
| 37 | #elif defined(CONFIG_AT91_EARLY_USART4) | ||
| 38 | #define UART_OFFSET AT91_USART4 | ||
| 39 | #elif defined(CONFIG_AT91_EARLY_USART5) | ||
| 40 | #define UART_OFFSET AT91_USART5 | ||
| 41 | #endif | ||
| 42 | |||
| 43 | /* | ||
| 44 | * The following code assumes the serial port has already been | ||
| 45 | * initialized by the bootloader. If you didn't setup a port in | ||
| 46 | * your bootloader then nothing will appear (which might be desired). | ||
| 47 | * | ||
| 48 | * This does not append a newline | ||
| 49 | */ | ||
| 50 | static void putc(int c) | ||
| 51 | { | ||
| 52 | #ifdef UART_OFFSET | ||
| 53 | void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */ | ||
| 54 | |||
| 55 | while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXRDY)) | ||
| 56 | barrier(); | ||
| 57 | __raw_writel(c, sys + ATMEL_US_THR); | ||
| 58 | #endif | ||
| 59 | } | ||
| 60 | |||
| 61 | static inline void flush(void) | ||
| 62 | { | ||
| 63 | #ifdef UART_OFFSET | ||
| 64 | void __iomem *sys = (void __iomem *) UART_OFFSET; /* physical address */ | ||
| 65 | |||
| 66 | /* wait for transmission to complete */ | ||
| 67 | while (!(__raw_readl(sys + ATMEL_US_CSR) & ATMEL_US_TXEMPTY)) | ||
| 68 | barrier(); | ||
| 69 | #endif | ||
| 70 | } | ||
| 71 | |||
| 72 | #define arch_decomp_setup() | ||
| 73 | |||
| 74 | #define arch_decomp_wdog() | ||
| 75 | |||
| 76 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/vmalloc.h b/arch/arm/mach-at91/include/mach/vmalloc.h new file mode 100644 index 000000000000..8eb459f3f5b7 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/vmalloc.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-at91/include/mach/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2003 SAN People | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __ASM_ARCH_VMALLOC_H | ||
| 22 | #define __ASM_ARCH_VMALLOC_H | ||
| 23 | |||
| 24 | #define VMALLOC_END (AT91_VIRT_BASE & PGDIR_MASK) | ||
| 25 | |||
| 26 | #endif | ||