ARM: 5850/1: [AT91] AT572D940HF processor support

Add support for the Atmel AT572D940HF processor (DIOPSIS range).
This processor integrates an ARM926 core, a DSP and the SoC
peripherals usually found on an AT91 processor (USART, SSC, SPI, TWI,
CAN, etc)

Signed-off-by: Antonio R. Costa <costa.antonior@gmail.com>
Signed-off-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

7 files changed, 266 insertions, 1 deletions

diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h
new file mode 100644
index 000000000000..2d9b0af9c4d5
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at572d940hf.h
@@ -0,0 +1,123 @@
+/*
+ * include/mach/at572d940hf.h
+ *
+ * Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2008 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef AT572D940HF_H
+#define AT572D940HF_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripherals */
+#define AT572D940HF_ID_PIOA     2       /* Parallel IO Controller A */
+#define AT572D940HF_ID_PIOB     3       /* Parallel IO Controller B */
+#define AT572D940HF_ID_PIOC     4       /* Parallel IO Controller C */
+#define AT572D940HF_ID_EMAC     5       /* MACB ethernet controller */
+#define AT572D940HF_ID_US0      6       /* USART 0 */
+#define AT572D940HF_ID_US1      7       /* USART 1 */
+#define AT572D940HF_ID_US2      8       /* USART 2 */
+#define AT572D940HF_ID_MCI      9       /* Multimedia Card Interface */
+#define AT572D940HF_ID_UDP      10      /* USB Device Port */
+#define AT572D940HF_ID_TWI0     11      /* Two-Wire Interface 0 */
+#define AT572D940HF_ID_SPI0     12      /* Serial Peripheral Interface 0 */
+#define AT572D940HF_ID_SPI1     13      /* Serial Peripheral Interface 1 */
+#define AT572D940HF_ID_SSC0     14      /* Serial Synchronous Controller 0 */
+#define AT572D940HF_ID_SSC1     15      /* Serial Synchronous Controller 1 */
+#define AT572D940HF_ID_SSC2     16      /* Serial Synchronous Controller 2 */
+#define AT572D940HF_ID_TC0      17      /* Timer Counter 0 */
+#define AT572D940HF_ID_TC1      18      /* Timer Counter 1 */
+#define AT572D940HF_ID_TC2      19      /* Timer Counter 2 */
+#define AT572D940HF_ID_UHP      20      /* USB Host port */
+#define AT572D940HF_ID_SSC3     21      /* Serial Synchronous Controller 3 */
+#define AT572D940HF_ID_TWI1     22      /* Two-Wire Interface 1 */
+#define AT572D940HF_ID_CAN0     23      /* CAN Controller 0 */
+#define AT572D940HF_ID_CAN1     24      /* CAN Controller 1 */
+#define AT572D940HF_ID_MHALT    25      /* mAgicV HALT line */
+#define AT572D940HF_ID_MSIRQ0   26      /* mAgicV SIRQ0 line */
+#define AT572D940HF_ID_MEXC     27      /* mAgicV exception line */
+#define AT572D940HF_ID_MEDMA    28      /* mAgicV end of DMA line */
+#define AT572D940HF_ID_IRQ0     29      /* External Interrupt Source (IRQ0) */
+#define AT572D940HF_ID_IRQ1     30      /* External Interrupt Source (IRQ1) */
+#define AT572D940HF_ID_IRQ2     31      /* External Interrupt Source (IRQ2) */
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT572D940HF_BASE_TCB    0xfffa0000
+#define AT572D940HF_BASE_TC0    0xfffa0000
+#define AT572D940HF_BASE_TC1    0xfffa0040
+#define AT572D940HF_BASE_TC2    0xfffa0080
+#define AT572D940HF_BASE_UDP    0xfffa4000
+#define AT572D940HF_BASE_MCI    0xfffa8000
+#define AT572D940HF_BASE_TWI0   0xfffac000
+#define AT572D940HF_BASE_US0    0xfffb0000
+#define AT572D940HF_BASE_US1    0xfffb4000
+#define AT572D940HF_BASE_US2    0xfffb8000
+#define AT572D940HF_BASE_SSC0   0xfffbc000
+#define AT572D940HF_BASE_SSC1   0xfffc0000
+#define AT572D940HF_BASE_SSC2   0xfffc4000
+#define AT572D940HF_BASE_SPI0   0xfffc8000
+#define AT572D940HF_BASE_SPI1   0xfffcc000
+#define AT572D940HF_BASE_SSC3   0xfffd0000
+#define AT572D940HF_BASE_TWI1   0xfffd4000
+#define AT572D940HF_BASE_EMAC   0xfffd8000
+#define AT572D940HF_BASE_CAN0   0xfffdc000
+#define AT572D940HF_BASE_CAN1   0xfffe0000
+#define AT91_BASE_SYS           0xffffea00
+
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+
+#define AT91_USART0     AT572D940HF_ID_US0
+#define AT91_USART1     AT572D940HF_ID_US1
+#define AT91_USART2     AT572D940HF_ID_US2
+
+
+/*
+ * Internal Memory.
+ */
+#define AT572D940HF_SRAM_BASE   0x00300000      /* Internal SRAM base address */
+#define AT572D940HF_SRAM_SIZE   (48 * SZ_1K)    /* Internal SRAM size (48Kb) */
+
+#define AT572D940HF_ROM_BASE    0x00400000      /* Internal ROM base address */
+#define AT572D940HF_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
+
+#define AT572D940HF_UHP_BASE    0x00500000      /* USB Host controller */
+
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h b/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
new file mode 100644
index 000000000000..b6751df09488
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
@@ -0,0 +1,123 @@
+/*
+ * include/mach//at572d940hf_matrix.h
+ *
+ * Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2008 Atmel
+ *
+ * Copyright (C) 2005 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef AT572D940HF_MATRIX_H
+#define AT572D940HF_MATRIX_H
+
+#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+
+#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
+#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (0x7  << 18)    /* Fixed Index of Default Master */
+#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
+#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+
+#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
+#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
+#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
+#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
+#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
+#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
+#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
+
+#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+
+#define AT91_MATRIX_SFR0        (AT91_MATRIX + 0x110)   /* Special Function Register 0 */
+#define AT91_MATRIX_SFR1        (AT91_MATRIX + 0x114)   /* Special Function Register 1 */
+#define AT91_MATRIX_SFR2        (AT91_MATRIX + 0x118)   /* Special Function Register 2 */
+#define AT91_MATRIX_SFR3        (AT91_MATRIX + 0x11C)   /* Special Function Register 3 */
+#define AT91_MATRIX_SFR4        (AT91_MATRIX + 0x120)   /* Special Function Register 4 */
+#define AT91_MATRIX_SFR5        (AT91_MATRIX + 0x124)   /* Special Function Register 5 */
+#define AT91_MATRIX_SFR6        (AT91_MATRIX + 0x128)   /* Special Function Register 6 */
+#define AT91_MATRIX_SFR7        (AT91_MATRIX + 0x12C)   /* Special Function Register 7 */
+#define AT91_MATRIX_SFR8        (AT91_MATRIX + 0x130)   /* Special Function Register 8 */
+#define AT91_MATRIX_SFR9        (AT91_MATRIX + 0x134)   /* Special Function Register 9 */
+#define AT91_MATRIX_SFR10       (AT91_MATRIX + 0x138)   /* Special Function Register 10 */
+#define AT91_MATRIX_SFR11       (AT91_MATRIX + 0x13C)   /* Special Function Register 11 */
+#define AT91_MATRIX_SFR12       (AT91_MATRIX + 0x140)   /* Special Function Register 12 */
+#define AT91_MATRIX_SFR13       (AT91_MATRIX + 0x144)   /* Special Function Register 13 */
+#define AT91_MATRIX_SFR14       (AT91_MATRIX + 0x148)   /* Special Function Register 14 */
+#define AT91_MATRIX_SFR15       (AT91_MATRIX + 0x14C)   /* Special Function Register 15 */
+
+
+/*
+ * The following registers / bits are not defined in the Datasheet (Revision A)
+ */
+
+#define AT91_MATRIX_TCR         (AT91_MATRIX + 0x100)   /* TCM Configuration Register */
+#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
+#define                 AT91_MATRIX_ITCM_0              (0 << 0)
+#define                 AT91_MATRIX_ITCM_16             (5 << 0)
+#define                 AT91_MATRIX_ITCM_32             (6 << 0)
+#define                 AT91_MATRIX_ITCM_64             (7 << 0)
+#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
+#define                 AT91_MATRIX_DTCM_0              (0 << 4)
+#define                 AT91_MATRIX_DTCM_16             (5 << 4)
+#define                 AT91_MATRIX_DTCM_32             (6 << 4)
+#define                 AT91_MATRIX_DTCM_64             (7 << 4)
+
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x11C)   /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
+#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
+#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
+#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
+#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
+#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
+#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
+#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 64589eaaaee8..e46f93e34aab 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -32,6 +32,7 @@
 #define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
 #define         AT91_PMC_PCK2           (1 << 10)               /* Programmable Clock 2 */
 #define         AT91_PMC_PCK3           (1 << 11)               /* Programmable Clock 3 */
+#define         AT91_PMC_PCK4           (1 << 12)               /* Programmable Clock 4 [AT572D940HF only] */
 #define         AT91_PMC_HCK0           (1 << 16)               /* AHB Clock (USB host) [AT91SAM9261 only] */
 #define         AT91_PMC_HCK1           (1 << 17)               /* AHB Clock (LCD) [AT91SAM9261 only] */
 
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index bb6f6a7ba5e0..ceaec6c16eb2 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -87,7 +87,7 @@ struct at91_eth_data {
 extern void __init at91_add_device_eth(struct at91_eth_data *data);
 
 #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
-        || defined(CONFIG_ARCH_AT91SAM9G45)
+        || defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT572D940HF)
 #define eth_platform_data       at91_eth_data
 #endif
 
@@ -205,6 +205,9 @@ extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
 extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
 extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
 
+ /* AT572D940HF DSP */
+extern void __init at91_add_device_mAgic(void);
+
 /* FIXME: this needs a better location, but gets stuff building again */
 extern int at91_suspend_entering_slow_clock(void);
 
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index c22df30ed5e5..5a0650101d45 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -33,6 +33,8 @@
 #define ARCH_ID_AT91SAM9XE256   0x329a93a0
 #define ARCH_ID_AT91SAM9XE512   0x329aa3a0
 
+#define ARCH_ID_AT572D940HF     0x0e0303e0
+
 #define ARCH_ID_AT91M40800      0x14080044
 #define ARCH_ID_AT91R40807      0x44080746
 #define ARCH_ID_AT91M40807      0x14080745
@@ -141,6 +143,12 @@ static inline unsigned long at91cap9_rev_identify(void)
 #define cpu_is_at91cap9_revC()  (0)
 #endif
 
+#ifdef CONFIG_ARCH_AT572D940HF
+#define cpu_is_at572d940hf() (at91_cpu_identify() == ARCH_ID_AT572D940HF)
+#else
+#define cpu_is_at572d940hf() (0)
+#endif
+
 /*
  * Since this is ARM, we will never run on any AVR32 CPU. But these
  * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index a0df8b022df2..3d64a75e3ed5 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -32,6 +32,8 @@
 #include <mach/at91cap9.h>
 #elif defined(CONFIG_ARCH_AT91X40)
 #include <mach/at91x40.h>
+#elif defined(CONFIG_ARCH_AT572D940HF)
+#include <mach/at572d940hf.h>
 #else
 #error "Unsupported AT91 processor"
 #endif
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index 31ac2d97f14c..05a6e8af80c4 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -82,6 +82,11 @@
 #define AT91X40_MASTER_CLOCK    40000000
 #define CLOCK_TICK_RATE         (AT91X40_MASTER_CLOCK)
 
+#elif defined(CONFIG_ARCH_AT572D940HF)
+
+#define AT572D940HF_MASTER_CLOCK        80000000
+#define CLOCK_TICK_RATE         (AT572D940HF_MASTER_CLOCK/16)
+
 #endif
 
 #endif