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authorAlexandre Belloni <alexandre.belloni@free-electrons.com>2014-04-15 06:28:01 -0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2014-05-07 12:28:40 -0400
commitbee20c4be1e2c32172f41c24ebaa7762aa9e4825 (patch)
tree3dead72465b1a9db90332f79b3610b06aa9b7ecc /arch/arm/mach-at91/include/mach
parentcab915947466112c6c5139ba132ea8d19ac06c6d (diff)
iio: adc: at91: remove unused include from include/mach
That include file is now only used by the at91_adc driver, remove it from include/mach for better driver separation. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Jonathan Cameron <jic23@kernel.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/include/mach')
-rw-r--r--arch/arm/mach-at91/include/mach/at91_adc.h120
1 files changed, 0 insertions, 120 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_adc.h b/arch/arm/mach-at91/include/mach/at91_adc.h
deleted file mode 100644
index 7d80396346b2..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_adc.h
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/at91_adc.h
3 *
4 * Copyright (C) SAN People
5 *
6 * Analog-to-Digital Converter (ADC) registers.
7 * Based on AT91SAM9260 datasheet revision D.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91_ADC_H
16#define AT91_ADC_H
17
18#define AT91_ADC_CR 0x00 /* Control Register */
19#define AT91_ADC_SWRST (1 << 0) /* Software Reset */
20#define AT91_ADC_START (1 << 1) /* Start Conversion */
21
22#define AT91_ADC_MR 0x04 /* Mode Register */
23#define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */
24#define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */
25#define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */
26#define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
27#define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
28#define AT91_ADC_TRGSEL_TC0 (0 << 1)
29#define AT91_ADC_TRGSEL_TC1 (1 << 1)
30#define AT91_ADC_TRGSEL_TC2 (2 << 1)
31#define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
32#define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
33#define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
34#define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */
35#define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */
36#define AT91_ADC_PRESCAL_9G45 (0xff << 8)
37#define AT91_ADC_PRESCAL_(x) ((x) << 8)
38#define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */
39#define AT91_ADC_STARTUP_9G45 (0x7f << 16)
40#define AT91_ADC_STARTUP_9X5 (0xf << 16)
41#define AT91_ADC_STARTUP_(x) ((x) << 16)
42#define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
43#define AT91_ADC_SHTIM_(x) ((x) << 24)
44#define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */
45#define AT91_ADC_PENDBC_(x) ((x) << 28)
46
47#define AT91_ADC_TSR 0x0C
48#define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */
49#define AT91_ADC_TSR_SHTIM_(x) ((x) << 24)
50
51#define AT91_ADC_CHER 0x10 /* Channel Enable Register */
52#define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
53#define AT91_ADC_CHSR 0x18 /* Channel Status Register */
54#define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
55
56#define AT91_ADC_SR 0x1C /* Status Register */
57#define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
58#define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
59#define AT91_ADC_DRDY (1 << 16) /* Data Ready */
60#define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
61#define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
62#define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
63
64#define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */
65#define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */
66
67#define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
68#define AT91_ADC_LDATA (0x3ff)
69
70#define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
71#define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
72#define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
73#define AT91RL_ADC_IER_PEN (1 << 20)
74#define AT91RL_ADC_IER_NOPEN (1 << 21)
75#define AT91_ADC_IER_PEN (1 << 29)
76#define AT91_ADC_IER_NOPEN (1 << 30)
77#define AT91_ADC_IER_XRDY (1 << 20)
78#define AT91_ADC_IER_YRDY (1 << 21)
79#define AT91_ADC_IER_PRDY (1 << 22)
80#define AT91_ADC_ISR_PENS (1 << 31)
81
82#define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
83#define AT91_ADC_DATA (0x3ff)
84
85#define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */
86
87#define AT91_ADC_ACR 0x94 /* Analog Control Register */
88#define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */
89
90#define AT91_ADC_TSMR 0xB0
91#define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */
92#define AT91_ADC_TSMR_TSMODE_NONE (0 << 0)
93#define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0)
94#define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0)
95#define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0)
96#define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */
97#define AT91_ADC_TSMR_TSAV_(x) ((x) << 4)
98#define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */
99#define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */
100#define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28)
101#define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */
102#define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */
103#define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */
104
105#define AT91_ADC_TSXPOSR 0xB4
106#define AT91_ADC_TSYPOSR 0xB8
107#define AT91_ADC_TSPRESSR 0xBC
108
109#define AT91_ADC_TRGR_9260 AT91_ADC_MR
110#define AT91_ADC_TRGR_9G45 0x08
111#define AT91_ADC_TRGR_9X5 0xC0
112
113/* Trigger Register bit field */
114#define AT91_ADC_TRGR_TRGPER (0xffff << 16)
115#define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16)
116#define AT91_ADC_TRGR_TRGMOD (0x7 << 0)
117#define AT91_ADC_TRGR_NONE (0 << 0)
118#define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0)
119
120#endif
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