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authorAlexandre Belloni <alexandre.belloni@free-electrons.com>2015-01-12 13:42:14 -0500
committerNicolas Ferre <nicolas.ferre@atmel.com>2015-01-15 09:24:06 -0500
commit5f58c97099f20cb12b463d3bb8bf0cbe522deb22 (patch)
tree36c485eb3e3409e4ad7c42c138e33e47c578430a /arch/arm/mach-at91/include/mach
parent415c94743524696d66e2bbbc00b72ad593cb0187 (diff)
ARM: at91: move debug-macro.S into the common space
Move debug-macro.S from include/mach/ to include/debug where all other common debug macros are. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm/mach-at91/include/mach')
-rw-r--r--arch/arm/mach-at91/include/mach/debug-macro.S46
1 files changed, 0 insertions, 46 deletions
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S
deleted file mode 100644
index 2103a90f2261..000000000000
--- a/arch/arm/mach-at91/include/mach/debug-macro.S
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * arch/arm/mach-at91/include/mach/debug-macro.S
3 *
4 * Copyright (C) 2003-2005 SAN People
5 *
6 * Debugging macro include header
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <mach/hardware.h>
15#include <mach/at91_dbgu.h>
16
17#if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
18#define AT91_DBGU AT91_BASE_DBGU0
19#elif defined(CONFIG_AT91_DEBUG_LL_DBGU1)
20#define AT91_DBGU AT91_BASE_DBGU1
21#else
22/* On sama5d4, use USART3 as low level serial console */
23#define AT91_DBGU SAMA5D4_BASE_USART3
24#endif
25
26 .macro addruart, rp, rv, tmp
27 ldr \rp, =AT91_DBGU @ System peripherals (phys address)
28 ldr \rv, =AT91_IO_P2V(AT91_DBGU) @ System peripherals (virt address)
29 .endm
30
31 .macro senduart,rd,rx
32 strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
33 .endm
34
35 .macro waituart,rd,rx
361001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
37 tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
38 beq 1001b
39 .endm
40
41 .macro busyuart,rd,rx
421001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
43 tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
44 beq 1001b
45 .endm
46