Merge branch 'at91-3.4-base2+cleanup' of git://github.com/at91linux/linux-at91 into at91/staging/base2+cleanup

* 'at91-3.4-base2+cleanup' of git://github.com/at91linux/linux-at91: (20 commits)
  ARM: at91: properly sort dtb files in Makefile.boot
  ARM: at91: add at91sam9g25ek.dts in Makefile.boot
  ARM: at91/board-dt: drop default console
  Atmel: move console default platform_device to serial driver
  ARM: at91: merge SRAM Memory banks thanks to mirroring
  ARM: at91: finally drop at91_sys_read/write
  ARM: at91/rtc-at91sam9: pass the GPBR to use via resources
  ARM: at91:rtc/rtc-at91sam9: ioremap register bank
  ARM: at91/rtc-at91sam9: each SoC can select the RTT device to use
  ARM: at91/PMC: make register base soc independent
  ARM: at91/PMC: move assignment out of printf
  ARM: at91/pm_slowclock: add runtime detection of memory contoller
  ARM: at91: make sdram/ddr register base soc independent
  ARM: at91: move at91rm9200 sdramc defines to at91rm9200_sdramc.h
  ARM: at91/pm_slowclock: function slow_clock() accepts parameters
  ARM: at91/pm_slowclock: rename register to named define
  ARM: at91/ST: remove not needed casts
  ARM: at91: make ST (System Timer) soc independent
  ARM: at91: make matrix register base soc independent
  ARM: at91/at91x40: remove use of at91_sys_read/write

Based on top of the at91/9x5, rmk/for-armsoc, at91/device-board,
at91/pm_cleanup and at91/base.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

1 files changed, 79 insertions, 0 deletions

diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
new file mode 100644
index 000000000000..a297a77d88e2
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -0,0 +1,79 @@
+/*
+ * Chip-specific header file for the AT91SAM9x5 family
+ *
+ *  Copyright (C) 2009-2012 Atmel Corporation.
+ *
+ * Common definitions.
+ * Based on AT91SAM9x5 datasheet.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef AT91SAM9X5_H
+#define AT91SAM9X5_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91SAM9X5_ID_PIOAB     2       /* Parallel I/O Controller A and B */
+#define AT91SAM9X5_ID_PIOCD     3       /* Parallel I/O Controller C and D */
+#define AT91SAM9X5_ID_SMD       4       /* SMD Soft Modem (SMD) */
+#define AT91SAM9X5_ID_USART0    5       /* USART 0 */
+#define AT91SAM9X5_ID_USART1    6       /* USART 1 */
+#define AT91SAM9X5_ID_USART2    7       /* USART 2 */
+#define AT91SAM9X5_ID_USART3    8       /* USART 3 */
+#define AT91SAM9X5_ID_TWI0      9       /* Two-Wire Interface 0 */
+#define AT91SAM9X5_ID_TWI1      10      /* Two-Wire Interface 1 */
+#define AT91SAM9X5_ID_TWI2      11      /* Two-Wire Interface 2 */
+#define AT91SAM9X5_ID_MCI0      12      /* High Speed Multimedia Card Interface 0 */
+#define AT91SAM9X5_ID_SPI0      13      /* Serial Peripheral Interface 0 */
+#define AT91SAM9X5_ID_SPI1      14      /* Serial Peripheral Interface 1 */
+#define AT91SAM9X5_ID_UART0     15      /* UART 0 */
+#define AT91SAM9X5_ID_UART1     16      /* UART 1 */
+#define AT91SAM9X5_ID_TCB       17      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+#define AT91SAM9X5_ID_PWM       18      /* Pulse Width Modulation Controller */
+#define AT91SAM9X5_ID_ADC       19      /* ADC Controller */
+#define AT91SAM9X5_ID_DMA0      20      /* DMA Controller 0 */
+#define AT91SAM9X5_ID_DMA1      21      /* DMA Controller 1 */
+#define AT91SAM9X5_ID_UHPHS     22      /* USB Host High Speed */
+#define AT91SAM9X5_ID_UDPHS     23      /* USB Device High Speed */
+#define AT91SAM9X5_ID_EMAC0     24      /* Ethernet MAC0 */
+#define AT91SAM9X5_ID_LCDC      25      /* LCD Controller */
+#define AT91SAM9X5_ID_ISI       25      /* Image Sensor Interface */
+#define AT91SAM9X5_ID_MCI1      26      /* High Speed Multimedia Card Interface 1 */
+#define AT91SAM9X5_ID_EMAC1     27      /* Ethernet MAC1 */
+#define AT91SAM9X5_ID_SSC       28      /* Synchronous Serial Controller */
+#define AT91SAM9X5_ID_CAN0      29      /* CAN Controller 0 */
+#define AT91SAM9X5_ID_CAN1      30      /* CAN Controller 1 */
+#define AT91SAM9X5_ID_IRQ0      31      /* Advanced Interrupt Controller */
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9X5_BASE_USART0  0xf801c000
+#define AT91SAM9X5_BASE_USART1  0xf8020000
+#define AT91SAM9X5_BASE_USART2  0xf8024000
+
+/*
+ * System Peripherals
+ */
+#define AT91SAM9X5_BASE_DDRSDRC0        0xffffe800
+
+/*
+ * Base addresses for early serial code (uncompress.h)
+ */
+#define AT91_DBGU       AT91_BASE_DBGU0
+#define AT91_USART0     AT91SAM9X5_BASE_USART0
+#define AT91_USART1     AT91SAM9X5_BASE_USART1
+#define AT91_USART2     AT91SAM9X5_BASE_USART2
+
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9X5_SRAM_BASE    0x00300000      /* Internal SRAM base address */
+#define AT91SAM9X5_SRAM_SIZE    SZ_32K          /* Internal SRAM size (32Kb) */
+
+#define AT91SAM9X5_ROM_BASE     0x00400000      /* Internal ROM base address */
+#define AT91SAM9X5_ROM_SIZE     SZ_64K          /* Internal ROM size (64Kb) */
+
+#endif