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authorDavid Brownell <david-b@pacbell.net>2008-01-04 12:30:24 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-02-04 08:16:39 -0500
commite83aff58bf1b7e6b355a0cfa206e9d3aebe5623f (patch)
tree0c5e5d990291cdef1e173a1bed74bb8915c67168 /arch/arm/mach-at91/gpio.c
parentae9458d6a0956aa21cb49e1251e35a8d4dacbe6e (diff)
[ARM] 4739/1: at91sam9263: make gpio bank C and D irqs work
On the at91sam9263, IRQs for GPIO banks C and D don't currently work. This is because banks C, D, and E share one clock and toplevel IRQ, but the AT91 code setting up and handling GPIO IRQs expects no sharing. This patch: - Fixes GPIO IRQ setup and handling to cope with GPIO banks that are shared like on sam9263 chips, by setting up a list of those banks and making the IRQ dispatching logic scan that list. - Precomputes the address of each bank's registers, saving it with other per-bank data so that it no longer needs to be constantly recomputed during IRQs and other GPIO operations. That shrinks hot-path code, while helping the GPIO bank irq updates. - Fixes a minor bug where IRQ_TYPE_NONE was wrongly rejected (it just means "use the default", which is "both edges" here). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Acked-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-at91/gpio.c')
-rw-r--r--arch/arm/mach-at91/gpio.c89
1 files changed, 60 insertions, 29 deletions
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 6aeddd68d8af..f629c2b5f0c5 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -33,12 +33,10 @@ static int gpio_banks;
33 33
34static inline void __iomem *pin_to_controller(unsigned pin) 34static inline void __iomem *pin_to_controller(unsigned pin)
35{ 35{
36 void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS;
37
38 pin -= PIN_BASE; 36 pin -= PIN_BASE;
39 pin /= 32; 37 pin /= 32;
40 if (likely(pin < gpio_banks)) 38 if (likely(pin < gpio_banks))
41 return sys_base + gpio[pin].offset; 39 return gpio[pin].regbase;
42 40
43 return NULL; 41 return NULL;
44} 42}
@@ -294,11 +292,11 @@ void at91_gpio_suspend(void)
294 int i; 292 int i;
295 293
296 for (i = 0; i < gpio_banks; i++) { 294 for (i = 0; i < gpio_banks; i++) {
297 u32 pio = gpio[i].offset; 295 void __iomem *pio = gpio[i].regbase;
298 296
299 backups[i] = at91_sys_read(pio + PIO_IMR); 297 backups[i] = __raw_readl(pio + PIO_IMR);
300 at91_sys_write(pio + PIO_IDR, backups[i]); 298 __raw_writel(backups[i], pio + PIO_IDR);
301 at91_sys_write(pio + PIO_IER, wakeups[i]); 299 __raw_writel(wakeups[i], pio + PIO_IER);
302 300
303 if (!wakeups[i]) 301 if (!wakeups[i])
304 clk_disable(gpio[i].clock); 302 clk_disable(gpio[i].clock);
@@ -315,13 +313,13 @@ void at91_gpio_resume(void)
315 int i; 313 int i;
316 314
317 for (i = 0; i < gpio_banks; i++) { 315 for (i = 0; i < gpio_banks; i++) {
318 u32 pio = gpio[i].offset; 316 void __iomem *pio = gpio[i].regbase;
319 317
320 if (!wakeups[i]) 318 if (!wakeups[i])
321 clk_enable(gpio[i].clock); 319 clk_enable(gpio[i].clock);
322 320
323 at91_sys_write(pio + PIO_IDR, wakeups[i]); 321 __raw_writel(wakeups[i], pio + PIO_IDR);
324 at91_sys_write(pio + PIO_IER, backups[i]); 322 __raw_writel(backups[i], pio + PIO_IER);
325 } 323 }
326} 324}
327 325
@@ -361,7 +359,13 @@ static void gpio_irq_unmask(unsigned pin)
361 359
362static int gpio_irq_type(unsigned pin, unsigned type) 360static int gpio_irq_type(unsigned pin, unsigned type)
363{ 361{
364 return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL; 362 switch (type) {
363 case IRQ_TYPE_NONE:
364 case IRQ_TYPE_EDGE_BOTH:
365 return 0;
366 default:
367 return -EINVAL;
368 }
365} 369}
366 370
367static struct irq_chip gpio_irqchip = { 371static struct irq_chip gpio_irqchip = {
@@ -376,20 +380,30 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
376{ 380{
377 unsigned pin; 381 unsigned pin;
378 struct irq_desc *gpio; 382 struct irq_desc *gpio;
383 struct at91_gpio_bank *bank;
379 void __iomem *pio; 384 void __iomem *pio;
380 u32 isr; 385 u32 isr;
381 386
382 pio = get_irq_chip_data(irq); 387 bank = get_irq_chip_data(irq);
388 pio = bank->regbase;
383 389
384 /* temporarily mask (level sensitive) parent IRQ */ 390 /* temporarily mask (level sensitive) parent IRQ */
385 desc->chip->ack(irq); 391 desc->chip->ack(irq);
386 for (;;) { 392 for (;;) {
387 /* reading ISR acks the pending (edge triggered) GPIO interrupt */ 393 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
394 * When there none are pending, we're finished unless we need
395 * to process multiple banks (like ID_PIOCDE on sam9263).
396 */
388 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); 397 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
389 if (!isr) 398 if (!isr) {
390 break; 399 if (!bank->next)
400 break;
401 bank = bank->next;
402 pio = bank->regbase;
403 continue;
404 }
391 405
392 pin = (unsigned) get_irq_data(irq); 406 pin = bank->chipbase;
393 gpio = &irq_desc[pin]; 407 gpio = &irq_desc[pin];
394 408
395 while (isr) { 409 while (isr) {
@@ -481,24 +495,21 @@ postcore_initcall(at91_gpio_debugfs_init);
481 */ 495 */
482void __init at91_gpio_irq_setup(void) 496void __init at91_gpio_irq_setup(void)
483{ 497{
484 unsigned pioc, pin; 498 unsigned pioc, pin;
499 struct at91_gpio_bank *this, *prev;
485 500
486 for (pioc = 0, pin = PIN_BASE; 501 for (pioc = 0, pin = PIN_BASE, this = gpio, prev = NULL;
487 pioc < gpio_banks; 502 pioc++ < gpio_banks;
488 pioc++) { 503 prev = this, this++) {
489 void __iomem *controller; 504 unsigned id = this->id;
490 unsigned id = gpio[pioc].id;
491 unsigned i; 505 unsigned i;
492 506
493 clk_enable(gpio[pioc].clock); /* enable PIO controller's clock */ 507 /* enable PIO controller's clock */
494 508 clk_enable(this->clock);
495 controller = (void __iomem *) AT91_VA_BASE_SYS + gpio[pioc].offset;
496 __raw_writel(~0, controller + PIO_IDR);
497 509
498 set_irq_data(id, (void *) pin); 510 __raw_writel(~0, this->regbase + PIO_IDR);
499 set_irq_chip_data(id, controller);
500 511
501 for (i = 0; i < 32; i++, pin++) { 512 for (i = 0, pin = this->chipbase; i < 32; i++, pin++) {
502 /* 513 /*
503 * Can use the "simple" and not "edge" handler since it's 514 * Can use the "simple" and not "edge" handler since it's
504 * shorter, and the AIC handles interrupts sanely. 515 * shorter, and the AIC handles interrupts sanely.
@@ -508,6 +519,14 @@ void __init at91_gpio_irq_setup(void)
508 set_irq_flags(pin, IRQF_VALID); 519 set_irq_flags(pin, IRQF_VALID);
509 } 520 }
510 521
522 /* The toplevel handler handles one bank of GPIOs, except
523 * AT91SAM9263_ID_PIOCDE handles three... PIOC is first in
524 * the list, so we only set up that handler.
525 */
526 if (prev && prev->next == this)
527 continue;
528
529 set_irq_chip_data(id, this);
511 set_irq_chained_handler(id, gpio_irq_handler); 530 set_irq_chained_handler(id, gpio_irq_handler);
512 } 531 }
513 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); 532 pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
@@ -518,8 +537,20 @@ void __init at91_gpio_irq_setup(void)
518 */ 537 */
519void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) 538void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
520{ 539{
540 unsigned i;
541 struct at91_gpio_bank *last;
542
521 BUG_ON(nr_banks > MAX_GPIO_BANKS); 543 BUG_ON(nr_banks > MAX_GPIO_BANKS);
522 544
523 gpio = data; 545 gpio = data;
524 gpio_banks = nr_banks; 546 gpio_banks = nr_banks;
547
548 for (i = 0, last = NULL; i < nr_banks; i++, last = data, data++) {
549 data->chipbase = PIN_BASE + i * 32;
550 data->regbase = data->offset + (void __iomem *)AT91_VA_BASE_SYS;
551
552 /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
553 if (last && last->id == data->id)
554 last->next = data;
555 }
525} 556}